From e690fb59f16fc533dafee20f131fa1047d1ce1f7 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 9 Jul 2025 16:11:10 +0200 Subject: [PATCH] docs: fix verilog frontend internals --- .../yosys_internals/flow/verilog_frontend.rst | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/docs/source/yosys_internals/flow/verilog_frontend.rst b/docs/source/yosys_internals/flow/verilog_frontend.rst index 2a26daec3..8381641b3 100644 --- a/docs/source/yosys_internals/flow/verilog_frontend.rst +++ b/docs/source/yosys_internals/flow/verilog_frontend.rst @@ -47,9 +47,9 @@ be found in :file:`frontends/verilog/verilog_lexer.l` in the Yosys source tree. The lexer does little more than identifying all keywords and literals recognised by the Yosys Verilog frontend. -The lexer keeps track of the current location in the Verilog source code using -some VerilogLexer member variables. These variables are used by the constructor of AST nodes -to annotate each node with the source code location it originated from. +The lexer keeps track of the current location in the Verilog source code with +a ``VerilogLexer::out_loc`` and uses it to construct parser-defined +symbol objects. Finally the lexer identifies and handles special comments such as "``// synopsys translate_off``" and "``// synopsys full_case``". (It is recommended to use @@ -178,11 +178,11 @@ properties: - | Source code location | Each ``AST::AstNode`` is automatically annotated with the current source - code location by the ``AST::AstNode`` constructor. It is stored in the - ``std::string filename`` and ``int linenum`` member variables. + code location by the ``AST::AstNode`` constructor. The ``location`` type + is a manual reimplementation of the bison-provided location type. This + type is defined at ``frontends/verilog/verilog_location.h``. -The ``AST::AstNode`` constructor can be called with up to two child nodes that -are automatically added to the list of child nodes for the new object. This +The ``AST::AstNode`` constructor can be called with up to 4 child nodes. This simplifies the creation of AST nodes for simple expressions a bit. For example the bison code for parsing multiplications: @@ -205,7 +205,7 @@ tree respectively. Transforming AST to RTLIL ------------------------- -The AST Frontend converts a set of modules in AST representation to modules in +The AST frontend converts a set of modules in AST representation to modules in RTLIL representation and adds them to the current design. This is done in two steps: simplification and RTLIL generation.