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Update macc test

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This commit is contained in:
Eddie Hung 2019-09-06 23:19:03 -07:00
parent 74a5c802f7
commit e68507a716
2 changed files with 42 additions and 42 deletions
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18
tests/xilinx/macc.ys
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@ -1,17 +1,13 @@
read_verilog macc.v
proc
hierarchy -top macc
equiv_opt -run :restore -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
#equiv_miter -trigger miter equiv
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
#equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
#miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -set-init-zero -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
hierarchy -auto-top
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd macc # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:DSP48E1
select -assert-none t:BUFG t:DSP48E1 %% t:* %D
select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D