mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

Support CEM

Browse source
This commit is contained in:
Eddie Hung 2019-09-04 10:52:51 -07:00
parent 80aec0f006
commit e67e4a5ed6
2 changed files with 33 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

10
passes/pmgen/xilinx_dsp.cc
View file

@ -39,6 +39,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
log("ffB: %s\n", log_id(st.ffB, "--"));
log("dsp: %s\n", log_id(st.dsp, "--"));
log("ffM: %s\n", log_id(st.ffM, "--"));
log("ffMmux: %s\n", log_id(st.ffMmux, "--"));
log("postAdd: %s\n", log_id(st.postAdd, "--"));
log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
log("ffP: %s\n", log_id(st.ffP, "--"));
@ -111,11 +112,12 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
SigSpec Q = st.ffM->getPort("\\Q");
P.replace(pm.sigmap(D), Q);
cell->setParam("\\MREG", State::S1);
if (st.ffM->type == "$dff")
if (st.ffMmux) {
cell->setPort("\\CEM", st.ffMmux->getPort("\\S"));
pm.autoremove(st.ffMmux);
}
else
cell->setPort("\\CEM", State::S1);
//else if (st.ffP->type == "$dffe")
// cell->setPort("\\CEM", st.ffM->getPort("\\EN"));
else log_abort();
pm.autoremove(st.ffM);
}
if (st.ffP) {

32
passes/pmgen/xilinx_dsp.pmg
View file

@ -2,9 +2,8 @@ pattern xilinx_dsp
state <SigBit> clock
state <std::set<SigBit>> sigAset sigBset
state <SigSpec> sigC sigM sigMused sigP sigPused
state <Cell*> postAdd postAddMux
state <IdString> postAddAB postAddMuxAB
state <SigSpec> sigC sigM sigP sigPused
state <IdString> ffMmuxAB postAddAB postAddMuxAB
match dsp
select dsp->type.in(\DSP48E1)
@ -70,22 +69,40 @@ code clock
}
endcode
match ffMmux
select ffMmux->type.in($mux)
select nusers(port(ffMmux, \Y)) == 2
filter GetSize(port(ffMmux, \Y)) <= GetSize(sigM)
choice <IdString> AB {\A, \B}
filter port(ffMmux, AB) == sigM.extract(0, GetSize(port(ffMmux, \Y)))
filter nusers(sigM.extract_end(GetSize(port(ffMmux, AB)))) <= 1
set ffMmuxAB AB
optional
endmatch
code sigM
if (ffMmux)
sigM = port(ffMmux, \Y);
endcode
match ffM
if param(dsp, \MREG).as_int() == 0
select ffM->type.in($dff)
// DSP48E1 does not support clock inversion
select param(ffM, \CLK_POLARITY).as_bool()
select nusers(port(ffM, \D)) == 2
//index <SigSpec> port(ffM, \D) === sigM.extract(0, GetSize(port(ffM, \D))) // TODO: Why doesn't this work!?!
filter GetSize(port(ffM, \D)) <= GetSize(sigM)
filter port(ffM, \D) == sigM.extract(0, GetSize(port(ffM, \D)))
filter nusers(sigM.extract_end(GetSize(port(ffM, \D)))) <= 1
// Check ffMmux (when present) is a $dff enable mux
filter !ffMmux || port(ffM, \Q) == port(ffMmux, ffMmuxAB == \A ? \B : \A)
optional
endmatch
code clock sigM sigP
if (ffM) {
sigM = port(ffM, \Q);
for (auto b : sigM)
if (b.wire->get_bool_attribute(\keep))
reject;
@ -97,6 +114,9 @@ code clock sigM sigP
clock = c;
}
// Cannot have ffMmux enable mux without ffM
else if (ffMmux)
reject;
sigP = sigM;
endcode
@ -108,7 +128,9 @@ match postAdd
select postAdd->type.in($add)
select param(postAdd, \A_SIGNED).as_bool() && param(postAdd, \B_SIGNED).as_bool()
choice <IdString> AB {\A, \B}
select nusers(port(postAdd, AB)) == 2
select nusers(port(postAdd, AB)) <= 3
filter ffMmux || nusers(port(postAdd, AB)) == 2
filter !ffMmux || nusers(port(postAdd, AB)) == 3
filter GetSize(port(postAdd, AB)) <= GetSize(sigP)
filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB)))
filter nusers(sigP.extract_end(GetSize(port(postAdd, AB)))) <= 1