3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 21:27:00 +00:00

Fixed handling of boolean attributes (passes)

This commit is contained in:
Clifford Wolf 2013-10-24 11:37:54 +02:00
parent e9dede01ca
commit e679a5d046
6 changed files with 8 additions and 8 deletions

View file

@ -144,7 +144,7 @@ struct IopadmapPass : public Pass {
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
cell->attributes["\\keep"] = RTLIL::Const();
cell->attributes["\\keep"] = RTLIL::Const(1);
module->add(cell);
wire->port_id = 0;