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Put attributes above port

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This commit is contained in:
Eddie Hung 2019-08-23 11:31:20 -07:00
parent d672b1ddec
commit e658d472c8
2 changed files with 62 additions and 27 deletions
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65
techlibs/xilinx/cells_sim.v
View file

@ -215,8 +215,11 @@ endmodule
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250 // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
module FDRE ((* abc_arrival=303 *) output reg Q, module FDRE (
input C, CE, D, R); (* abc_arrival=303 *)
output reg Q,
input C, CE, D, R
);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
@ -228,8 +231,11 @@ module FDRE ((* abc_arrival=303 *) output reg Q,
endcase endgenerate endcase endgenerate
endmodule endmodule
module FDSE ((* abc_arrival=303 *) output reg Q, module FDSE (
input C, CE, D, S); (* abc_arrival=303 *)
output reg Q,
input C, CE, D, S
);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
@ -241,8 +247,11 @@ module FDSE ((* abc_arrival=303 *) output reg Q,
endcase endgenerate endcase endgenerate
endmodule endmodule
module FDCE ((* abc_arrival=303 *) output reg Q, module FDCE (
input C, CE, D, CLR); (* abc_arrival=303 *)
output reg Q,
input C, CE, D, CLR
);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
@ -256,8 +265,11 @@ module FDCE ((* abc_arrival=303 *) output reg Q,
endcase endgenerate endcase endgenerate
endmodule endmodule
module FDPE ((* abc_arrival=303 *) output reg Q, module FDPE (
input C, CE, D, PRE); (* abc_arrival=303 *)
output reg Q,
input C, CE, D, PRE
);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
@ -271,29 +283,41 @@ module FDPE ((* abc_arrival=303 *) output reg Q,
endcase endgenerate endcase endgenerate
endmodule endmodule
module FDRE_1 ((* abc_arrival=303 *) output reg Q, module FDRE_1 (
input C, CE, D, R); (* abc_arrival=303 *)
output reg Q,
input C, CE, D, R
);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q <= INIT; initial Q <= INIT;
always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D; always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
endmodule endmodule
module FDSE_1 ((* abc_arrival=303 *) output reg Q, module FDSE_1 (
input C, CE, D, S); (* abc_arrival=303 *)
output reg Q,
input C, CE, D, S
);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q <= INIT; initial Q <= INIT;
always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D; always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
endmodule endmodule
module FDCE_1 ((* abc_arrival=303 *) output reg Q, module FDCE_1 (
input C, CE, D, CLR); (* abc_arrival=303 *)
output reg Q,
input C, CE, D, CLR
);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q <= INIT; initial Q <= INIT;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule endmodule
module FDPE_1 ((* abc_arrival=303 *) output reg Q, module FDPE_1 (
input C, CE, D, PRE); (* abc_arrival=303 *)
output reg Q,
input C, CE, D, PRE
);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q <= INIT; initial Q <= INIT;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
@ -361,7 +385,8 @@ endmodule
module SRL16E ( module SRL16E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
(* abc_arrival=1472 *) output Q, (* abc_arrival=1472 *)
output Q,
input A0, A1, A2, A3, CE, CLK, D input A0, A1, A2, A3, CE, CLK, D
); );
parameter [15:0] INIT = 16'h0000; parameter [15:0] INIT = 16'h0000;
@ -380,8 +405,10 @@ endmodule
module SRLC32E ( module SRLC32E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
(* abc_arrival=1472 *) output Q, (* abc_arrival=1472 *)
(* abc_arrival=1114 *) output Q31, output Q,
(* abc_arrival=1114 *)
output Q31,
input [4:0] A, input [4:0] A,
input CE, CLK, D input CE, CLK, D
); );

24
techlibs/xilinx/xc7_brams_bb.v
View file

@ -21,10 +21,14 @@ module RAMB18E1 (
input [1:0] WEA, input [1:0] WEA,
input [3:0] WEBWE, input [3:0] WEBWE,
(* abc_arrival=2454 *) output [15:0] DOADO, (* abc_arrival=2454 *)
(* abc_arrival=2454 *) output [15:0] DOBDO, output [15:0] DOADO,
(* abc_arrival=2454 *) output [1:0] DOPADOP, (* abc_arrival=2454 *)
(* abc_arrival=2454 *) output [1:0] DOPBDOP output [15:0] DOBDO,
(* abc_arrival=2454 *)
output [1:0] DOPADOP,
(* abc_arrival=2454 *)
output [1:0] DOPBDOP
); );
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -145,10 +149,14 @@ module RAMB36E1 (
input [3:0] WEA, input [3:0] WEA,
input [7:0] WEBWE, input [7:0] WEBWE,
(* abc_arrival=2454 *) output [31:0] DOADO, (* abc_arrival=2454 *)
(* abc_arrival=2454 *) output [31:0] DOBDO, output [31:0] DOADO,
(* abc_arrival=2454 *) output [3:0] DOPADOP, (* abc_arrival=2454 *)
(* abc_arrival=2454 *) output [3:0] DOPBDOP output [31:0] DOBDO,
(* abc_arrival=2454 *)
output [3:0] DOPADOP,
(* abc_arrival=2454 *)
output [3:0] DOPBDOP
); );
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;