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extract_reduce: Refactor and fix input signal construction.

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Fixes #3047.
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Marcelina Kościelnicka 2021-10-21 02:58:10 +02:00
parent a0e9d9fef9
commit e64456f920
2 changed files with 46 additions and 63 deletions
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tests/opt/bug3047.ys Normal file
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read_verilog << EOT
module test (A, B, C, D, Y);
input A, B, C, D;
output Y;
assign Y = A^B^C^D^A;
endmodule
EOT
techmap
equiv_opt -assert extract_reduce