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Restore write_xaiger's holes_mode since port_id order causes QoR

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regressions inside abc9
This commit is contained in:
Eddie Hung 2020-01-03 12:30:22 -08:00
parent dedea5a58d
commit e62eb02c1d
1 changed files with 19 additions and 27 deletions
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46
backends/aiger/xaiger.cc
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@ -137,7 +137,7 @@ struct XAigerWriter
return a; return a;
} }
XAigerWriter(Module *module) : module(module), sigmap(module) XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
{ {
pool<SigBit> undriven_bits; pool<SigBit> undriven_bits;
pool<SigBit> unused_bits; pool<SigBit> unused_bits;
@ -157,12 +157,8 @@ struct XAigerWriter
if (wire->get_bool_attribute(ID::keep)) if (wire->get_bool_attribute(ID::keep))
sigmap.add(wire); sigmap.add(wire);
// First, collect all the ports in port_id order
// since module->wires() could be sorted for (auto wire : module->wires())
// alphabetically
for (auto port : module->ports) {
auto wire = module->wire(port);
log_assert(wire);
for (int i = 0; i < GetSize(wire); i++) for (int i = 0; i < GetSize(wire); i++)
{ {
SigBit wirebit(wire, i); SigBit wirebit(wire, i);
@ -176,6 +172,9 @@ struct XAigerWriter
continue; continue;
} }
undriven_bits.insert(bit);
unused_bits.insert(bit);
if (wire->port_input) if (wire->port_input)
input_bits.insert(bit); input_bits.insert(bit);
@ -185,19 +184,6 @@ struct XAigerWriter
output_bits.insert(wirebit); output_bits.insert(wirebit);
} }
} }
}
for (auto wire : module->wires())
for (int i = 0; i < GetSize(wire); i++)
{
SigBit wirebit(wire, i);
SigBit bit = sigmap(wirebit);
if (bit.wire) {
undriven_bits.insert(bit);
unused_bits.insert(bit);
}
}
// TODO: Speed up toposort -- ultimately we care about // TODO: Speed up toposort -- ultimately we care about
// box ordering, but not individual AIG cells // box ordering, but not individual AIG cells
@ -485,12 +471,20 @@ struct XAigerWriter
undriven_bits.erase(bit); undriven_bits.erase(bit);
} }
if (holes_mode) {
struct sort_by_port_id {
bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
return a.wire->port_id < b.wire->port_id;
}
};
input_bits.sort(sort_by_port_id());
output_bits.sort(sort_by_port_id());
}
aig_map[State::S0] = 0; aig_map[State::S0] = 0;
aig_map[State::S1] = 1; aig_map[State::S1] = 1;
// pool<> iterates in LIFO order... for (const auto &bit : input_bits) {
for (int i = input_bits.size()-1; i >= 0; i--) {
const auto &bit = *input_bits.element(i);
aig_m++, aig_i++; aig_m++, aig_i++;
log_assert(!aig_map.count(bit)); log_assert(!aig_map.count(bit));
aig_map[bit] = 2*aig_m; aig_map[bit] = 2*aig_m;
@ -515,9 +509,7 @@ struct XAigerWriter
aig_outputs.push_back(bit2aig(bit)); aig_outputs.push_back(bit2aig(bit));
} }
// pool<> iterates in LIFO order... for (const auto &bit : output_bits) {
for (int i = output_bits.size()-1; i >= 0; i--) {
const auto &bit = *output_bits.element(i);
ordered_outputs[bit] = aig_o++; ordered_outputs[bit] = aig_o++;
aig_outputs.push_back(bit2aig(bit)); aig_outputs.push_back(bit2aig(bit));
} }
@ -816,7 +808,7 @@ struct XAigerWriter
Pass::call(holes_design, "opt -purge"); Pass::call(holes_design, "opt -purge");
std::stringstream a_buffer; std::stringstream a_buffer;
XAigerWriter writer(holes_module); XAigerWriter writer(holes_module, true /* holes_mode */);
writer.write_aiger(a_buffer, false /*ascii_mode*/); writer.write_aiger(a_buffer, false /*ascii_mode*/);
delete holes_design; delete holes_design;