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Removed SigSpec::extend_xx() api

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This commit is contained in:
Clifford Wolf 2015-01-01 11:41:52 +01:00
parent 327a5d42b6
commit e62d838bd4
3 changed files with 1 additions and 20 deletions
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18
kernel/rtlil.cc
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@ -2673,24 +2673,6 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
check(); check();
} }
void RTLIL::SigSpec::extend_xx(int width, bool is_signed)
{
cover("kernel.rtlil.sigspec.extend_xx");
pack();
if (width_ > width)
remove(width, width_ - width);
if (width_ < width) {
RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
if (!is_signed && (padding == RTLIL::State::S1 || padding.wire))
padding = RTLIL::State::S0;
while (width_ < width)
append(padding);
}
}
void RTLIL::SigSpec::extend_u0(int width, bool is_signed) void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
{ {
cover("kernel.rtlil.sigspec.extend_u0"); cover("kernel.rtlil.sigspec.extend_u0");

1
kernel/rtlil.h
View file

@ -651,7 +651,6 @@ public:
void append(const RTLIL::SigSpec &signal); void append(const RTLIL::SigSpec &signal);
void append_bit(const RTLIL::SigBit &bit); void append_bit(const RTLIL::SigBit &bit);
void extend_xx(int width, bool is_signed = false);
void extend_u0(int width, bool is_signed = false); void extend_u0(int width, bool is_signed = false);
RTLIL::SigSpec repeat(int num) const; RTLIL::SigSpec repeat(int num) const;

2
passes/proc/proc_arst.cc
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@ -262,7 +262,7 @@ struct ProcArstPass : public Pass {
for (auto &chunk : act.first.chunks()) for (auto &chunk : act.first.chunks())
if (chunk.wire && chunk.wire->attributes.count("\\init")) { if (chunk.wire && chunk.wire->attributes.count("\\init")) {
RTLIL::SigSpec value = chunk.wire->attributes.at("\\init"); RTLIL::SigSpec value = chunk.wire->attributes.at("\\init");
value.extend_xx(chunk.wire->width, false); value.extend_u0(chunk.wire->width, false);
arst_sig.append(chunk); arst_sig.append(chunk);
arst_val.append(value.extract(chunk.offset, chunk.width)); arst_val.append(value.extract(chunk.offset, chunk.width));
} }