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prevent IdString construction when looking up module from instance type

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This commit is contained in:
Emil J. Tywoniak 2026-06-16 13:16:18 +02:00
parent 45c1654938
commit e5f6755ffd
40 changed files with 94 additions and 94 deletions
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22
passes/techmap/abc9_ops.cc
View file

@ -99,7 +99,7 @@ void check(RTLIL::Design *design, bool dff_mode)
};
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
if (!inst_module)
continue;
IdString derived_type;
@ -160,7 +160,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
if (!inst_module)
continue;
IdString derived_type;
@ -280,7 +280,7 @@ void prep_bypass(RTLIL::Design *design)
for (auto cell : module->cells()) {
if (!processed.insert(cell->type).second)
continue;
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
if (!inst_module)
continue;
if (!inst_module->get_bool_attribute(ID::abc9_bypass))
@ -461,7 +461,7 @@ void prep_dff(RTLIL::Design *design)
for (auto cell : module->cells()) {
if (modules_sel.selected_whole_module(cell->type.ref()))
continue;
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
if (!inst_module)
continue;
if (!inst_module->get_bool_attribute(ID::abc9_flop))
@ -575,7 +575,7 @@ void break_scc(RTLIL::Module *module)
if (it == cell->attributes.end())
continue;
scc_cells.insert(cell);
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
if (inst_module && inst_module->has_attribute(ID::abc9_bypass))
ids_seen.insert(it->second);
}
@ -629,7 +629,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
continue;
log_assert(!cell->type.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
RTLIL::Module* inst_module = design->module(cell->type);
RTLIL::Module* inst_module = design->module(cell->type_impl);
if (!inst_module)
continue;
if (!inst_module->get_blackbox_attribute())
@ -661,7 +661,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
log_assert(delay_module);
for (auto cell : cells) {
auto module = cell->module;
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
log_assert(inst_module);
for (auto &i : timing.at(cell->type).required) {
@ -719,7 +719,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
if (cell->has_keep_attr())
continue;
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
bool abc9_flop = inst_module && inst_module->get_bool_attribute(ID::abc9_flop);
if (abc9_flop && !dff)
continue;
@ -764,7 +764,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
if (cell->has_keep_attr())
continue;
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
bool abc9_flop = inst_module && inst_module->get_bool_attribute(ID::abc9_flop);
if (abc9_flop && !dff)
continue;
@ -813,7 +813,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
continue;
auto cell = module->cell(cell_name);
log_assert(cell);
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
if (inst_module && inst_module->get_bool_attribute(ID::abc9_box))
continue;
for (auto &c : cell->connections_) {
@ -870,7 +870,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
RTLIL::Cell *cell = module->cell(cell_name);
log_assert(cell);
RTLIL::Module* box_module = design->module(cell->type);
RTLIL::Module* box_module = design->module(cell->type_impl);
if (!box_module)
continue;
if (!box_module->get_bool_attribute(ID::abc9_box))

2
passes/techmap/abc_new.cc
View file

@ -34,7 +34,7 @@ std::vector<Module*> order_modules(Design *design, std::vector<Module *> modules
sort.node(m);
for (auto cell : m->cells()) {
Module *submodule = design->module(cell->type);
Module *submodule = design->module(cell->type_impl);
if (modules_set.count(submodule))
sort.edge(submodule, m);
}

2
passes/techmap/clkbufmap.cc
View file

@ -68,7 +68,7 @@ struct ClkbufmapPass : public Pass {
if (modules_processed.count(module))
return;
for (auto cell : module->cells()) {
Module *submodule = design->module(cell->type);
Module *submodule = design->module(cell->type_impl);
if (!submodule)
continue;
module_queue(design, submodule, modules_sorted, modules_processed);

2
passes/techmap/extractinv.cc
View file

@ -84,7 +84,7 @@ struct ExtractinvPass : public Pass {
{
for (auto cell : module->selected_cells())
for (auto port : cell->connections()) {
auto cell_module = design->module(cell->type);
auto cell_module = design->module(cell->type_impl);
if (!cell_module)
continue;
auto cell_wire = cell_module->wire(port.first);

2
passes/techmap/iopadmap.cc
View file

@ -90,7 +90,7 @@ struct IopadmapPass : public Pass {
if (modules_processed.count(module))
return;
for (auto cell : module->cells()) {
Module *submodule = design->module(cell->type);
Module *submodule = design->module(cell->type_impl);
if (!submodule)
continue;
module_queue(design, submodule, modules_sorted, modules_processed);