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prevent IdString construction when looking up module from instance type

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This commit is contained in:
Emil J. Tywoniak 2026-06-16 13:16:18 +02:00
parent 45c1654938
commit e5f6755ffd
40 changed files with 94 additions and 94 deletions
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6
backends/aiger/xaiger.cc
View file

@ -228,7 +228,7 @@ struct XAigerWriter
continue;
}
RTLIL::Module* inst_module = design->module(cell->type);
RTLIL::Module* inst_module = design->module(cell->type_impl);
if (inst_module && inst_module->get_blackbox_attribute()) {
bool abc9_flop = false;
@ -315,7 +315,7 @@ struct XAigerWriter
for (auto cell : box_list) {
log_assert(cell);
RTLIL::Module* box_module = design->module(cell->type);
RTLIL::Module* box_module = design->module(cell->type_impl);
log_assert(box_module);
log_assert(box_module->has_attribute(ID::abc9_box_id));
@ -572,7 +572,7 @@ struct XAigerWriter
auto r = cell_cache.insert(cell->type);
auto &v = r.first->second;
if (r.second) {
RTLIL::Module* box_module = design->module(cell->type);
RTLIL::Module* box_module = design->module(cell->type_impl);
log_assert(box_module);
int box_inputs = 0, box_outputs = 0;

4
backends/aiger2/aiger.cc
View file

@ -112,7 +112,7 @@ struct Index {
if (known_ops(cell->type) || cell->type.in(TW($scopeinfo), TW($specify2), TW($specify3), TW($input_port), TW($output_port), TW($public)))
continue;
Module *submodule = m->design->module(cell->type);
Module *submodule = m->design->module(cell->type_impl);
if (submodule && flatten &&
!submodule->get_bool_attribute(ID::keep_hierarchy) &&
@ -538,7 +538,7 @@ struct Index {
auto &minfo = leaf_minfo(index);
if (!minfo.suboffsets.count(cell))
log_error("Reached unsupported cell %s (%s in %s)\n", cell->type.unescaped(), cell, cell->module);
Module *def = design->module(cell->type);
Module *def = design->module(cell->type_impl);
log_assert(def);
levels.push_back(Level(index.modules.at(def), cell));
instance_offset += minfo.suboffsets.at(cell);

2
backends/blif/blif.cc
View file

@ -426,7 +426,7 @@ struct BlifDumper
continue;
}
Module *m = design->module(cell->type);
Module *m = design->module(cell->type_impl);
Wire *w = m ? m->wire(conn.first) : nullptr;
if (w == nullptr) {

16
backends/cxxrtl/cxxrtl_backend.cc
View file

@ -224,7 +224,7 @@ bool is_effectful_cell(TwineRef type)
bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
{
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
RTLIL::Module *cell_module = cell->module->design->module(cell->type_impl);
log_assert(cell_module != nullptr);
return cell_module->get_bool_attribute(ID(cxxrtl_blackbox));
}
@ -261,7 +261,7 @@ CxxrtlPortType cxxrtl_port_type(RTLIL::Module *module, TwineRef port)
CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, TwineRef port)
{
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
RTLIL::Module *cell_module = cell->module->design->module(cell->type_impl);
if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
return CxxrtlPortType::UNKNOWN;
return cxxrtl_port_type(cell_module, port);
@ -904,7 +904,7 @@ struct CxxrtlWorker {
std::string template_args(const RTLIL::Cell *cell)
{
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
RTLIL::Module *cell_module = cell->module->design->module(cell->type_impl);
log_assert(cell_module != nullptr);
if (!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
return "";
@ -1546,7 +1546,7 @@ struct CxxrtlWorker {
const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
for (auto conn : cell->connections())
if (cell->input(conn.first)) {
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
RTLIL::Module *cell_module = cell->module->design->module(cell->type_impl);
log_assert(cell_module != nullptr && cell_module->wire(conn.first));
RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first);
f << indent << mangle(cell) << access << mangle_wire_name(conn.first, cell->module->design);
@ -2170,7 +2170,7 @@ struct CxxrtlWorker {
if (is_internal_cell(cell->type))
continue;
f << indent << mangle(cell);
RTLIL::Module *cell_module = module->design->module(cell->type);
RTLIL::Module *cell_module = module->design->module(cell->type_impl);
if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
f << "->reset();\n";
} else {
@ -2705,7 +2705,7 @@ struct CxxrtlWorker {
if (is_internal_cell(cell->type))
continue;
dump_attrs(cell);
RTLIL::Module *cell_module = module->design->module(cell->type);
RTLIL::Module *cell_module = module->design->module(cell->type_impl);
log_assert(cell_module != nullptr);
if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
@ -2822,7 +2822,7 @@ struct CxxrtlWorker {
for (auto cell : module->cells()) {
if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
continue;
RTLIL::Module *cell_module = design->module(cell->type);
RTLIL::Module *cell_module = design->module(cell->type_impl);
log_assert(cell_module != nullptr);
topo_design.edge(cell_module, module);
}
@ -3013,7 +3013,7 @@ struct CxxrtlWorker {
if (cell->is_mem_cell())
continue;
RTLIL::Module *cell_module = design->module(cell->type);
RTLIL::Module *cell_module = design->module(cell->type_impl);
if (cell_module &&
cell_module->get_blackbox_attribute() &&
!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))

8
backends/edif/edif.cc
View file

@ -219,7 +219,7 @@ struct EdifBackend : public Backend {
if (cell->type == TW($scopeinfo))
continue;
if (design->module(cell->type) == nullptr || design->module(cell->type)->get_blackbox_attribute()) {
if (design->module(cell->type_impl) == nullptr || design->module(cell->type_impl)->get_blackbox_attribute()) {
lib_cell_ports[cell->type];
for (auto p : cell->connections())
lib_cell_ports[cell->type][p.first] = std::max(lib_cell_ports[cell->type][p.first], GetSize(p.second));
@ -309,8 +309,8 @@ struct EdifBackend : public Backend {
for (auto module : design->modules()) {
module_deps[module] = std::set<RTLIL::Module*>();
for (auto cell : module->cells())
if (design->module(cell->type) != nullptr)
module_deps[module].insert(design->module(cell->type));
if (design->module(cell->type_impl) != nullptr)
module_deps[module].insert(design->module(cell->type_impl));
}
// simple good-enough topological sort
@ -496,7 +496,7 @@ struct EdifBackend : public Backend {
i, module, cell, port_name_str, log_signal(sig[i]));
else {
int member_idx = lsbidx ? i : GetSize(sig)-i-1;
auto m = design->module(cell->type);
auto m = design->module(cell->type_impl);
int width = sig.size();
if (m) {
auto w = m->wire(p.first);

6
backends/firrtl/firrtl.cc
View file

@ -344,7 +344,7 @@ void emit_elaborated_extmodules(RTLIL::Design *design, std::ostream &f)
if (cellIsModuleInstance)
{
// Find the module corresponding to this instance.
auto modInstance = design->module(cell->type);
auto modInstance = design->module(cell->type_impl);
// Ensure that we actually have a module instance
if (modInstance == nullptr) {
log_error("Unknown cell type %s\n", cell->type);
@ -461,7 +461,7 @@ struct FirrtlWorker
else
cell_name_comment = "";
// Find the module corresponding to this instance.
auto instModule = design->module(cell->type);
auto instModule = design->module(cell->type_impl);
// If there is no instance for this, just return.
if (instModule == NULL)
{
@ -579,7 +579,7 @@ struct FirrtlWorker
Const ndef(0, 0);
// Is this cell is a module instance?
if (module->design->module(cell->type))
if (module->design->module(cell->type_impl))
{
process_instance(cell, wire_exprs);
continue;

2
backends/simplec/simplec.cc
View file

@ -76,7 +76,7 @@ struct HierDirtyFlags
dirty(0), module(module), hiername(hiername), parent(parent), prefix(prefix), log_prefix(log_prefix)
{
for (Cell *cell : module->cells()) {
Module *mod = module->design->module(cell->type);
Module *mod = module->design->module(cell->type_impl);
if (mod) children[cell->name] = new HierDirtyFlags(mod, cell->name, this,
prefix + cid(cell->name) + ".", log_prefix + "." + prefix + cell->module->design->twines.str(cell->meta_->name));
}

6
backends/smt2/smt2.cc
View file

@ -887,7 +887,7 @@ struct Smt2Worker
return;
}
Module *m = module->design->module(cell->type);
Module *m = module->design->module(cell->type_impl);
if (m != nullptr)
{
@ -1166,7 +1166,7 @@ struct Smt2Worker
if (verbose) log("=> export logic driving hierarchical cells\n");
for (auto cell : module->cells())
if (module->design->module(cell->type) != nullptr)
if (module->design->module(cell->type_impl) != nullptr)
export_cell(cell);
while (!hiercells_queue.empty())
@ -1177,7 +1177,7 @@ struct Smt2Worker
for (auto cell : queue)
{
string cell_state = stringf("(|%s_h %s| state)", get_id(module), get_id(cell->name));
Module *m = module->design->module(cell->type);
Module *m = module->design->module(cell->type_impl);
log_assert(m != nullptr);
hier.push_back(stringf(" (= (|%s_is| state) (|%s_is| %s))\n",

4
backends/spice/spice.cc
View file

@ -79,7 +79,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
std::vector<RTLIL::SigSpec> port_sigs;
if (design->module(cell->type) == nullptr)
if (design->module(cell->type_impl) == nullptr)
{
log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
cell->type.unescape(), module, cell);
@ -90,7 +90,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
}
else
{
RTLIL::Module *mod = design->module(cell->type);
RTLIL::Module *mod = design->module(cell->type_impl);
std::vector<RTLIL::Wire*> ports;
for (auto wire : mod->wires()) {