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prevent IdString construction when looking up module from instance type

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This commit is contained in:
Emil J. Tywoniak 2026-06-16 13:16:18 +02:00
parent 45c1654938
commit e5f6755ffd
40 changed files with 94 additions and 94 deletions
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6
backends/aiger/xaiger.cc
View file

@ -228,7 +228,7 @@ struct XAigerWriter
continue;
}
RTLIL::Module* inst_module = design->module(cell->type);
RTLIL::Module* inst_module = design->module(cell->type_impl);
if (inst_module && inst_module->get_blackbox_attribute()) {
bool abc9_flop = false;
@ -315,7 +315,7 @@ struct XAigerWriter
for (auto cell : box_list) {
log_assert(cell);
RTLIL::Module* box_module = design->module(cell->type);
RTLIL::Module* box_module = design->module(cell->type_impl);
log_assert(box_module);
log_assert(box_module->has_attribute(ID::abc9_box_id));
@ -572,7 +572,7 @@ struct XAigerWriter
auto r = cell_cache.insert(cell->type);
auto &v = r.first->second;
if (r.second) {
RTLIL::Module* box_module = design->module(cell->type);
RTLIL::Module* box_module = design->module(cell->type_impl);
log_assert(box_module);
int box_inputs = 0, box_outputs = 0;

4
backends/aiger2/aiger.cc
View file

@ -112,7 +112,7 @@ struct Index {
if (known_ops(cell->type) || cell->type.in(TW($scopeinfo), TW($specify2), TW($specify3), TW($input_port), TW($output_port), TW($public)))
continue;
Module *submodule = m->design->module(cell->type);
Module *submodule = m->design->module(cell->type_impl);
if (submodule && flatten &&
!submodule->get_bool_attribute(ID::keep_hierarchy) &&
@ -538,7 +538,7 @@ struct Index {
auto &minfo = leaf_minfo(index);
if (!minfo.suboffsets.count(cell))
log_error("Reached unsupported cell %s (%s in %s)\n", cell->type.unescaped(), cell, cell->module);
Module *def = design->module(cell->type);
Module *def = design->module(cell->type_impl);
log_assert(def);
levels.push_back(Level(index.modules.at(def), cell));
instance_offset += minfo.suboffsets.at(cell);

2
backends/blif/blif.cc
View file

@ -426,7 +426,7 @@ struct BlifDumper
continue;
}
Module *m = design->module(cell->type);
Module *m = design->module(cell->type_impl);
Wire *w = m ? m->wire(conn.first) : nullptr;
if (w == nullptr) {

16
backends/cxxrtl/cxxrtl_backend.cc
View file

@ -224,7 +224,7 @@ bool is_effectful_cell(TwineRef type)
bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
{
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
RTLIL::Module *cell_module = cell->module->design->module(cell->type_impl);
log_assert(cell_module != nullptr);
return cell_module->get_bool_attribute(ID(cxxrtl_blackbox));
}
@ -261,7 +261,7 @@ CxxrtlPortType cxxrtl_port_type(RTLIL::Module *module, TwineRef port)
CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, TwineRef port)
{
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
RTLIL::Module *cell_module = cell->module->design->module(cell->type_impl);
if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
return CxxrtlPortType::UNKNOWN;
return cxxrtl_port_type(cell_module, port);
@ -904,7 +904,7 @@ struct CxxrtlWorker {
std::string template_args(const RTLIL::Cell *cell)
{
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
RTLIL::Module *cell_module = cell->module->design->module(cell->type_impl);
log_assert(cell_module != nullptr);
if (!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
return "";
@ -1546,7 +1546,7 @@ struct CxxrtlWorker {
const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
for (auto conn : cell->connections())
if (cell->input(conn.first)) {
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
RTLIL::Module *cell_module = cell->module->design->module(cell->type_impl);
log_assert(cell_module != nullptr && cell_module->wire(conn.first));
RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first);
f << indent << mangle(cell) << access << mangle_wire_name(conn.first, cell->module->design);
@ -2170,7 +2170,7 @@ struct CxxrtlWorker {
if (is_internal_cell(cell->type))
continue;
f << indent << mangle(cell);
RTLIL::Module *cell_module = module->design->module(cell->type);
RTLIL::Module *cell_module = module->design->module(cell->type_impl);
if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
f << "->reset();\n";
} else {
@ -2705,7 +2705,7 @@ struct CxxrtlWorker {
if (is_internal_cell(cell->type))
continue;
dump_attrs(cell);
RTLIL::Module *cell_module = module->design->module(cell->type);
RTLIL::Module *cell_module = module->design->module(cell->type_impl);
log_assert(cell_module != nullptr);
if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
@ -2822,7 +2822,7 @@ struct CxxrtlWorker {
for (auto cell : module->cells()) {
if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
continue;
RTLIL::Module *cell_module = design->module(cell->type);
RTLIL::Module *cell_module = design->module(cell->type_impl);
log_assert(cell_module != nullptr);
topo_design.edge(cell_module, module);
}
@ -3013,7 +3013,7 @@ struct CxxrtlWorker {
if (cell->is_mem_cell())
continue;
RTLIL::Module *cell_module = design->module(cell->type);
RTLIL::Module *cell_module = design->module(cell->type_impl);
if (cell_module &&
cell_module->get_blackbox_attribute() &&
!cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))

8
backends/edif/edif.cc
View file

@ -219,7 +219,7 @@ struct EdifBackend : public Backend {
if (cell->type == TW($scopeinfo))
continue;
if (design->module(cell->type) == nullptr || design->module(cell->type)->get_blackbox_attribute()) {
if (design->module(cell->type_impl) == nullptr || design->module(cell->type_impl)->get_blackbox_attribute()) {
lib_cell_ports[cell->type];
for (auto p : cell->connections())
lib_cell_ports[cell->type][p.first] = std::max(lib_cell_ports[cell->type][p.first], GetSize(p.second));
@ -309,8 +309,8 @@ struct EdifBackend : public Backend {
for (auto module : design->modules()) {
module_deps[module] = std::set<RTLIL::Module*>();
for (auto cell : module->cells())
if (design->module(cell->type) != nullptr)
module_deps[module].insert(design->module(cell->type));
if (design->module(cell->type_impl) != nullptr)
module_deps[module].insert(design->module(cell->type_impl));
}
// simple good-enough topological sort
@ -496,7 +496,7 @@ struct EdifBackend : public Backend {
i, module, cell, port_name_str, log_signal(sig[i]));
else {
int member_idx = lsbidx ? i : GetSize(sig)-i-1;
auto m = design->module(cell->type);
auto m = design->module(cell->type_impl);
int width = sig.size();
if (m) {
auto w = m->wire(p.first);

6
backends/firrtl/firrtl.cc
View file

@ -344,7 +344,7 @@ void emit_elaborated_extmodules(RTLIL::Design *design, std::ostream &f)
if (cellIsModuleInstance)
{
// Find the module corresponding to this instance.
auto modInstance = design->module(cell->type);
auto modInstance = design->module(cell->type_impl);
// Ensure that we actually have a module instance
if (modInstance == nullptr) {
log_error("Unknown cell type %s\n", cell->type);
@ -461,7 +461,7 @@ struct FirrtlWorker
else
cell_name_comment = "";
// Find the module corresponding to this instance.
auto instModule = design->module(cell->type);
auto instModule = design->module(cell->type_impl);
// If there is no instance for this, just return.
if (instModule == NULL)
{
@ -579,7 +579,7 @@ struct FirrtlWorker
Const ndef(0, 0);
// Is this cell is a module instance?
if (module->design->module(cell->type))
if (module->design->module(cell->type_impl))
{
process_instance(cell, wire_exprs);
continue;

2
backends/simplec/simplec.cc
View file

@ -76,7 +76,7 @@ struct HierDirtyFlags
dirty(0), module(module), hiername(hiername), parent(parent), prefix(prefix), log_prefix(log_prefix)
{
for (Cell *cell : module->cells()) {
Module *mod = module->design->module(cell->type);
Module *mod = module->design->module(cell->type_impl);
if (mod) children[cell->name] = new HierDirtyFlags(mod, cell->name, this,
prefix + cid(cell->name) + ".", log_prefix + "." + prefix + cell->module->design->twines.str(cell->meta_->name));
}

6
backends/smt2/smt2.cc
View file

@ -887,7 +887,7 @@ struct Smt2Worker
return;
}
Module *m = module->design->module(cell->type);
Module *m = module->design->module(cell->type_impl);
if (m != nullptr)
{
@ -1166,7 +1166,7 @@ struct Smt2Worker
if (verbose) log("=> export logic driving hierarchical cells\n");
for (auto cell : module->cells())
if (module->design->module(cell->type) != nullptr)
if (module->design->module(cell->type_impl) != nullptr)
export_cell(cell);
while (!hiercells_queue.empty())
@ -1177,7 +1177,7 @@ struct Smt2Worker
for (auto cell : queue)
{
string cell_state = stringf("(|%s_h %s| state)", get_id(module), get_id(cell->name));
Module *m = module->design->module(cell->type);
Module *m = module->design->module(cell->type_impl);
log_assert(m != nullptr);
hier.push_back(stringf(" (= (|%s_is| state) (|%s_is| %s))\n",

4
backends/spice/spice.cc
View file

@ -79,7 +79,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
std::vector<RTLIL::SigSpec> port_sigs;
if (design->module(cell->type) == nullptr)
if (design->module(cell->type_impl) == nullptr)
{
log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
cell->type.unescape(), module, cell);
@ -90,7 +90,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
}
else
{
RTLIL::Module *mod = design->module(cell->type);
RTLIL::Module *mod = design->module(cell->type_impl);
std::vector<RTLIL::Wire*> ports;
for (auto wire : mod->wires()) {

4
kernel/cost.cc
View file

@ -142,9 +142,9 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
if (cmos_gate_cost().count(cell->type_impl))
return 1;
if (design_ && design_->module(cell->type) && cell->parameters.empty()) {
if (design_ && design_->module(cell->type_impl) && cell->parameters.empty()) {
log_debug("%s is a module, recurse\n", cell->name);
return get(design_->module(cell->type));
return get(design_->module(cell->type_impl));
} else if (cell->is_builtin_ff()) {
log_assert(cell->hasPort(TW::Q) && "Weird flip flop");
log_debug("%s is ff\n", cell->name);

2
kernel/yw.h
View file

@ -123,7 +123,7 @@ void witness_hierarchy_recursion(IdPath &path, int hdlname_mode, RTLIL::Module *
for (auto cell : module->cells())
{
Module *child = module->design->module(cell->type);
Module *child = module->design->module(cell->type_impl);
if (child == nullptr)
continue;

2
passes/cmds/add.cc
View file

@ -102,7 +102,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
for (auto cell : module->cells())
{
RTLIL::Module *mod = design->module(cell->type);
RTLIL::Module *mod = design->module(cell->type_impl);
if (mod == nullptr)
continue;
if (!mod->is_selected_whole())

2
passes/cmds/box_derive.cc
View file

@ -86,7 +86,7 @@ struct BoxDerivePass : Pass {
for (auto module : d->selected_modules()) {
for (auto cell : module->selected_cells()) {
Module *inst_module = d->module(cell->type);
Module *inst_module = d->module(cell->type_impl);
if (!inst_module || !inst_module->get_blackbox_attribute())
continue;

2
passes/cmds/check.cc
View file

@ -361,7 +361,7 @@ struct CheckPass : public Pass {
if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
continue;
if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
if (mapped && cell->type.begins_with("$") && design->module(cell->type_impl) == nullptr) {
if (allow_tbuf && cell->type == TW($_TBUF_)) goto cell_allowed;
log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", module, cell, cell->type.unescaped());
counter++;

2
passes/cmds/design.cc
View file

@ -283,7 +283,7 @@ struct DesignPass : public Pass {
for (auto mod : old_queue)
for (auto cell : mod->cells())
{
Module *fmod = copy_from_design->module(cell->type);
Module *fmod = copy_from_design->module(cell->type_impl);
if (fmod == nullptr)
continue;

8
passes/cmds/glift.cc
View file

@ -184,7 +184,7 @@ private:
std::vector<RTLIL::SigSig> connections(module->connections());
for(auto &cell : module->cells().to_vector()) {
if (!cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_MUX_), TW($_NMUX_), TW($_NOT_), TW($anyconst), TW($allconst), TW($assume), TW($assert)) && module->design->module(cell->type) == nullptr) {
if (!cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_MUX_), TW($_NMUX_), TW($_NOT_), TW($anyconst), TW($allconst), TW($assume), TW($assert)) && module->design->module(cell->type_impl) == nullptr) {
log_cmd_error("Unsupported cell type \"%s\" found. Run `techmap` first.\n", cell->type);
}
if (cell->type.in(TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_))) {
@ -337,12 +337,12 @@ private:
}
else log_cmd_error("This is a bug (3).\n");
}
else if (module->design->module(cell->type) != nullptr) {
else if (module->design->module(cell->type_impl) != nullptr) {
//User cell type
//This function is called on modules according to topological order, so we do not need to
//recurse to GLIFT model the child module. However, we need to augment the ports list
//with taint signals and connect the new ports to the corresponding taint signals.
RTLIL::Module *cell_module_def = module->design->module(cell->type);
RTLIL::Module *cell_module_def = module->design->module(cell->type_impl);
auto orig_ports = cell->connections();
log("Adding cell %s\n", module->design->twines.str(cell_module_def->meta_->name).c_str());
for (auto &it : orig_ports) {
@ -592,7 +592,7 @@ struct GliftPass : public Pass {
topo_modules.node(module);
for (auto cell : module->selected_cells()) {
RTLIL::Module *tpl = design->module(cell->type);
RTLIL::Module *tpl = design->module(cell->type_impl);
if (tpl != nullptr) {
if (!topo_modules.has_node(tpl))
worklist.push_back(tpl);

2
passes/cmds/icell_liberty.cc
View file

@ -190,7 +190,7 @@ struct IcellLiberty : Pass {
for (auto module : d->selected_modules()) {
for (auto cell : module->selected_cells()) {
Module *inst_module = d->module(cell->type);
Module *inst_module = d->module(cell->type_impl);
if (!inst_module || !inst_module->get_blackbox_attribute())
continue;
Module *base = inst_module;

2
passes/cmds/rename.cc
View file

@ -135,7 +135,7 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
bool has_witness_signals = false;
for (auto cell : module->cells())
{
RTLIL::Module *impl = design->module(cell->type);
RTLIL::Module *impl = design->module(cell->type_impl);
if (impl != nullptr) {
bool witness_in_cell = rename_witness(design, cache, impl);
has_witness_signals |= witness_in_cell;

2
passes/cmds/scc.cc
View file

@ -147,7 +147,7 @@ struct SccWorker
if (specifyCells.cell_known(cell->type.ref())) {
// Use specify rules of the type `(X => Y) = NN` to look for asynchronous paths in boxes.
for (auto subcell : design->module(cell->type)->cells())
for (auto subcell : design->module(cell->type_impl)->cells())
{
if (subcell->type != TW($specify2))
continue;

4
passes/cmds/sdc/sdc.cc
View file

@ -154,7 +154,7 @@ struct SdcObjects {
std::string pin_name_sdc = path + "/" + design->twines.unescaped_str(pin.first);
design_pins.push_back(std::make_pair(pin_name_sdc, std::make_pair(cell, pin_name)));
}
if (auto sub_mod = mod->design->module(cell->type)) {
if (auto sub_mod = mod->design->module(cell->type_impl)) {
hierarchy.push_back(name);
sniff_module(hierarchy, sub_mod);
hierarchy.pop_back();
@ -264,7 +264,7 @@ struct SdcObjects {
Design* design = nullptr;
bool mark(Module* mod) {
for (auto* cell : mod->cells()) {
if (auto* submod = design->module(cell->type))
if (auto* submod = design->module(cell->type_impl))
if (mark(submod)) {
mod->set_bool_attribute(ID::keep_hierarchy);
return true;

6
passes/cmds/select.cc
View file

@ -271,7 +271,7 @@ static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs)
{
for (auto cell : mod->cells())
{
if (design->module(cell->type) == nullptr)
if (design->module(cell->type_impl) == nullptr)
continue;
lhs.selected_modules.insert(design->twines.add(Twine{cell->type.str()}));
}
@ -285,7 +285,7 @@ static void select_op_cells_to_modules(RTLIL::Design *design, RTLIL::Selection &
for (auto mod : design->modules())
if (lhs.selected_module(mod->meta_->name))
for (auto cell : mod->cells())
if (lhs.selected_member(mod->meta_->name, cell->meta_->name) && (design->module(cell->type) != nullptr))
if (lhs.selected_member(mod->meta_->name, cell->meta_->name) && (design->module(cell->type_impl) != nullptr))
new_sel.selected_modules.insert(design->twines.add(Twine{cell->type.str()}));
lhs = new_sel;
}
@ -295,7 +295,7 @@ static void select_op_module_to_cells(RTLIL::Design *design, RTLIL::Selection &l
RTLIL::Selection new_sel(false, lhs.selects_boxes, design);
for (auto mod : design->modules())
for (auto cell : mod->cells())
if ((design->module(cell->type) != nullptr) && lhs.selected_whole_module(design->twines.add(Twine{cell->type.str()})))
if ((design->module(cell->type_impl) != nullptr) && lhs.selected_whole_module(design->twines.add(Twine{cell->type.str()})))
new_sel.selected_members[mod->meta_->name].insert(cell->meta_->name);
lhs = new_sel;
}

2
passes/cmds/splitnets.cc
View file

@ -276,7 +276,7 @@ struct SplitnetsPass : public Pass {
for (auto nid : new_port_ids)
{
int nlen = GetSize(design->module(cell->type)->wire(nid));
int nlen = GetSize(design->module(cell->type_impl)->wire(nid));
if (offset + nlen > GetSize(sig))
nlen = GetSize(sig) - offset;
if (nlen > 0)

2
passes/cmds/sta.cc
View file

@ -63,7 +63,7 @@ struct StaWorker
for (auto cell : module->cells())
{
Module *inst_module = design->module(cell->type);
Module *inst_module = design->module(cell->type_impl);
if (!inst_module) {
if (unrecognised_cells.insert(cell->type).second)
log_warning("Cell type '%s' not recognised! Ignoring.\n", cell->type.unescaped());

12
passes/cmds/stat.cc
View file

@ -765,10 +765,10 @@ statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod
for (auto cell : top_mod->selected_cells()) {
if (cell_area.count(cell->type) == 0) {
if (design->has(cell->type_impl)) {
if (!(design->module(cell->type)->attributes.count(ID::blackbox))) {
if (!(design->module(cell->type_impl)->attributes.count(ID::blackbox))) {
// deal with modules
mod_data.add(
hierarchy_builder(design, design->module(cell->type), mod_stat, width_mode, cell_area, techname));
hierarchy_builder(design, design->module(cell->type_impl), mod_stat, width_mode, cell_area, techname));
mod_data.num_submodules_by_type[cell->type]++;
mod_data.submodules_area_by_type[cell->type] += mod_stat.at(cell->type).area;
mod_data.submodule_area += mod_stat.at(cell->type).area;
@ -784,13 +784,13 @@ statdata_t hierarchy_builder(RTLIL::Design *design, const RTLIL::Module *top_mod
mod_data.local_area_cells_by_type.erase(cell->type);
} else {
// deal with blackbox cells
if (design->module(cell->type)->attributes.count(ID::area) &&
design->module(cell->type)->attributes.at(ID::area).size() == 0) {
if (design->module(cell->type_impl)->attributes.count(ID::area) &&
design->module(cell->type_impl)->attributes.at(ID::area).size() == 0) {
mod_data.num_submodules_by_type[cell->type]++;
mod_data.num_submodules++;
mod_data.submodules_area_by_type[cell->type] +=
double(design->module(cell->type)->attributes.at(ID::area).as_int());
mod_data.area += double(design->module(cell->type)->attributes.at(ID::area).as_int());
double(design->module(cell->type_impl)->attributes.at(ID::area).as_int());
mod_data.area += double(design->module(cell->type_impl)->attributes.at(ID::area).as_int());
mod_data.unknown_cell_area.erase(cell->type);
mod_data.num_cells -=
(mod_data.num_cells_by_type.count(cell->type) != 0) ? mod_data.num_cells_by_type.at(cell->type) : 0;

2
passes/equiv/equiv_struct.cc
View file

@ -132,7 +132,7 @@ struct EquivStructWorker
equiv_inputs.insert(sig_b);
cells.insert(cell->meta_->name);
} else {
if (mode_icells || module->design->module(cell->type))
if (mode_icells || module->design->module(cell->type_impl))
cells.insert(cell->meta_->name);
}

2
passes/hierarchy/flatten.cc
View file

@ -471,7 +471,7 @@ struct FlattenPass : public Pass {
while (!worklist.empty()) {
RTLIL::Module *module = worklist.pop();
for (auto cell : module->selected_cells()) {
RTLIL::Module *tpl = design->module(cell->type);
RTLIL::Module *tpl = design->module(cell->type_impl);
if (tpl != nullptr) {
if (!topo_modules.has_node(tpl))
worklist.insert(tpl);

22
passes/hierarchy/hierarchy.cc
View file

@ -45,7 +45,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
for (auto mod : design->modules())
for (auto cell : mod->cells())
{
if (design->module(cell->type) != nullptr)
if (design->module(cell->type_impl) != nullptr)
continue;
if (cell->type.begins_with("$") && !cell->type.begins_with("$__"))
continue;
@ -195,7 +195,7 @@ struct IFExpander
if(!cell->get_bool_attribute(ID::is_interface))
continue;
interfaces_in_module[cell->name] = design.module(cell->type);
interfaces_in_module[cell->name] = design.module(cell->type_impl);
}
}
@ -520,7 +520,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
dict<TwineRef, RTLIL::Module*> interfaces_by_name;
dict<TwineRef, TwineRef> modports_by_name;
RTLIL::Module *mod = design->module(cell->type);
RTLIL::Module *mod = design->module(cell->type_impl);
if (!mod)
{
mod = get_module(*design, *cell, *module, flag_check || flag_simcheck || flag_smtcheck, libdirs);
@ -589,7 +589,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
// an interface instance:
if (mod->get_bool_attribute(ID::is_interface) && cell->get_bool_attribute(ID::module_not_derived)) {
cell->set_bool_attribute(ID::is_interface);
RTLIL::Module *derived_module = design->module(cell->type);
RTLIL::Module *derived_module = design->module(cell->type_impl);
if_expander.interfaces_in_module[cell->name] = derived_module;
did_something = true;
}
@ -618,10 +618,10 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
RTLIL::Cell *cell = it.first;
int idx = it.second.first, num = it.second.second;
if (design->module(cell->type) == nullptr)
if (design->module(cell->type_impl) == nullptr)
log_error("Array cell `%s.%s' of unknown type `%s'.\n", module, cell, cell->type.unescaped());
RTLIL::Module *mod = design->module(cell->type);
RTLIL::Module *mod = design->module(cell->type_impl);
for (auto &conn : cell->connections_) {
int conn_size = conn.second.size();
@ -1245,13 +1245,13 @@ struct HierarchyPass : public Pass {
for (auto mod : design->modules())
for (auto cell : mod->cells()) {
RTLIL::Module *cell_mod = design->module(cell->type);
RTLIL::Module *cell_mod = design->module(cell->type_impl);
if (cell_mod == nullptr)
continue;
for (auto &conn : cell->connections()) {
std::string conn_name = design->twines.str(conn.first);
if (!conn_name.empty() && conn_name[0] == '$' && '0' <= conn_name[1] && conn_name[1] <= '9') {
pos_mods.insert(design->module(cell->type));
pos_mods.insert(design->module(cell->type_impl));
pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod, cell));
break;
}
@ -1290,7 +1290,7 @@ struct HierarchyPass : public Pass {
for (auto &conn : cell->connections()) {
int id;
if (read_id_num(*design, conn.first, &id)) {
std::pair<RTLIL::Module*,int> key(design->module(cell->type), id);
std::pair<RTLIL::Module*,int> key(design->module(cell->type_impl), id);
if (pos_map.count(key) == 0) {
log(" Failed to map positional argument %d of cell %s.%s (%s).\n",
id, module, cell, cell->type.unescaped());
@ -1323,7 +1323,7 @@ struct HierarchyPass : public Pass {
{
if (!cell->get_bool_attribute(ID::wildcard_port_conns))
continue;
Module *m = design->module(cell->type);
Module *m = design->module(cell->type_impl);
if (m == nullptr)
log_error("Cell %s.%s (%s) has implicit port connections but the module it instantiates is unknown.\n",
@ -1513,7 +1513,7 @@ struct HierarchyPass : public Pass {
for (auto cell : module->cells())
{
Module *m = design->module(cell->type);
Module *m = design->module(cell->type_impl);
if (m == nullptr)
continue;

2
passes/hierarchy/keep_hierarchy.cc
View file

@ -58,7 +58,7 @@ struct ThresholdHierarchyKeeping {
if (!cell->type.isPublic()) {
size += costs.get(cell);
} else {
RTLIL::Module *submodule = design->module(cell->type);
RTLIL::Module *submodule = design->module(cell->type_impl);
if (!submodule)
log_error("Hierarchy contains unknown module '%s' (instanced as %s in %s)\n",
cell->type.unescaped(), cell, module);

2
passes/hierarchy/uniquify.cc
View file

@ -70,7 +70,7 @@ struct UniquifyPass : public Pass {
for (auto cell : module->selected_cells())
{
Module *tmod = design->module(cell->type);
Module *tmod = design->module(cell->type_impl);
std::string tmod_name_str(design->twines.str(tmod->meta_->name));
IdString newname = design->twines.str(module->meta_->name).data() + std::string(".") + cell->module->design->twines.str(cell->meta_->name);

4
passes/opt/opt_clean/keep_cache.h
View file

@ -78,7 +78,7 @@ struct KeepCache
if (cell->type.in(TW($specify2), TW($specify3), TW($specrule)))
return true;
if (cell->module && cell->module->design) {
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
RTLIL::Module *cell_module = cell->module->design->module(cell->type_impl);
return cell_module != nullptr && keep_modules.at(cell_module);
}
return false;
@ -117,7 +117,7 @@ private:
keep = true;
}
if (const_module->design) {
RTLIL::Module *cell_module = const_module->design->module(cell->type);
RTLIL::Module *cell_module = const_module->design->module(cell->type_impl);
if (cell_module != nullptr)
deps.insert(ctx, cell_module);
}

2
passes/sat/cutpoint.cc
View file

@ -89,7 +89,7 @@ struct CutpointPass : public Pass {
auto &selection = design->selection();
for (auto module : design->modules())
for (auto cell : module->cells())
if (selection.boxed_module(cell->type))
if (selection.boxed_module(cell->type_impl))
selection.select(module, cell);
}

6
passes/sat/expose.cc
View file

@ -52,7 +52,7 @@ bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells,
{
if (cell->name[0] == '$' || dff_cells.count(cell->name))
return false;
if (cell->type[0] == '\\' && (design->module(cell->type) == nullptr))
if (cell->type[0] == '\\' && (design->module(cell->type_impl) == nullptr))
return false;
return true;
}
@ -623,9 +623,9 @@ struct ExposePass : public Pass {
continue;
}
if (design->module(cell->type) != nullptr)
if (design->module(cell->type_impl) != nullptr)
{
RTLIL::Module *mod = design->module(cell->type);
RTLIL::Module *mod = design->module(cell->type_impl);
for (auto p : mod->wires())
{

2
passes/sat/fmcombine.cc
View file

@ -109,7 +109,7 @@ struct FmcombineWorker
module->fixup_ports();
for (auto cell : original->cells()) {
if (design->module(cell->type) == nullptr) {
if (design->module(cell->type_impl) == nullptr) {
if (opts.anyeq && cell->type.in(TW($anyseq), TW($anyconst))) {
Cell *gold = import_prim_cell(cell, "_gold");
for (auto &conn : cell->connections())

2
passes/sat/sim.cc
View file

@ -313,7 +313,7 @@ struct SimInstance
for (auto cell : module->cells())
{
Module *mod = module->design->module(cell->type);
Module *mod = module->design->module(cell->type_impl);
if (mod != nullptr) {
dirty_children.insert(new SimInstance(shared, scope + "." + cell->module->design->twines.str(cell->meta_->name), mod, cell, this));

4
passes/sat/synthprop.cc
View file

@ -72,7 +72,7 @@ void SynthPropWorker::tracing(RTLIL::Module *mod, int depth, TrackingData &traci
}
cnt++;
}
else if (RTLIL::Module *submod = design->module(cell->type)) {
else if (RTLIL::Module *submod = design->module(cell->type_impl)) {
tracing(submod, depth+1, tracing_data, hier_path + "." + cell->module->design->twines.str(cell->meta_->name));
if (!or_outputs) {
for (size_t i = 0; i < tracing_data[submod].names.size(); i++)
@ -127,7 +127,7 @@ void SynthPropWorker::run()
}
for (auto cell : data.first->cells()) {
if (RTLIL::Module *submod = design->module(cell->type)) {
if (RTLIL::Module *submod = design->module(cell->type_impl)) {
if (tracing_data[submod].names.size() > 0) {
if (!or_outputs) {
cell->setPort(port_name, SigChunk(port_wire, num, tracing_data[submod].names.size()));

22
passes/techmap/abc9_ops.cc
View file

@ -99,7 +99,7 @@ void check(RTLIL::Design *design, bool dff_mode)
};
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
if (!inst_module)
continue;
IdString derived_type;
@ -160,7 +160,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
if (!inst_module)
continue;
IdString derived_type;
@ -280,7 +280,7 @@ void prep_bypass(RTLIL::Design *design)
for (auto cell : module->cells()) {
if (!processed.insert(cell->type).second)
continue;
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
if (!inst_module)
continue;
if (!inst_module->get_bool_attribute(ID::abc9_bypass))
@ -461,7 +461,7 @@ void prep_dff(RTLIL::Design *design)
for (auto cell : module->cells()) {
if (modules_sel.selected_whole_module(cell->type.ref()))
continue;
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
if (!inst_module)
continue;
if (!inst_module->get_bool_attribute(ID::abc9_flop))
@ -575,7 +575,7 @@ void break_scc(RTLIL::Module *module)
if (it == cell->attributes.end())
continue;
scc_cells.insert(cell);
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
if (inst_module && inst_module->has_attribute(ID::abc9_bypass))
ids_seen.insert(it->second);
}
@ -629,7 +629,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
continue;
log_assert(!cell->type.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
RTLIL::Module* inst_module = design->module(cell->type);
RTLIL::Module* inst_module = design->module(cell->type_impl);
if (!inst_module)
continue;
if (!inst_module->get_blackbox_attribute())
@ -661,7 +661,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
log_assert(delay_module);
for (auto cell : cells) {
auto module = cell->module;
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
log_assert(inst_module);
for (auto &i : timing.at(cell->type).required) {
@ -719,7 +719,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
if (cell->has_keep_attr())
continue;
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
bool abc9_flop = inst_module && inst_module->get_bool_attribute(ID::abc9_flop);
if (abc9_flop && !dff)
continue;
@ -764,7 +764,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
if (cell->has_keep_attr())
continue;
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
bool abc9_flop = inst_module && inst_module->get_bool_attribute(ID::abc9_flop);
if (abc9_flop && !dff)
continue;
@ -813,7 +813,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
continue;
auto cell = module->cell(cell_name);
log_assert(cell);
auto inst_module = design->module(cell->type);
auto inst_module = design->module(cell->type_impl);
if (inst_module && inst_module->get_bool_attribute(ID::abc9_box))
continue;
for (auto &c : cell->connections_) {
@ -870,7 +870,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
RTLIL::Cell *cell = module->cell(cell_name);
log_assert(cell);
RTLIL::Module* box_module = design->module(cell->type);
RTLIL::Module* box_module = design->module(cell->type_impl);
if (!box_module)
continue;
if (!box_module->get_bool_attribute(ID::abc9_box))

2
passes/techmap/abc_new.cc
View file

@ -34,7 +34,7 @@ std::vector<Module*> order_modules(Design *design, std::vector<Module *> modules
sort.node(m);
for (auto cell : m->cells()) {
Module *submodule = design->module(cell->type);
Module *submodule = design->module(cell->type_impl);
if (modules_set.count(submodule))
sort.edge(submodule, m);
}

2
passes/techmap/clkbufmap.cc
View file

@ -68,7 +68,7 @@ struct ClkbufmapPass : public Pass {
if (modules_processed.count(module))
return;
for (auto cell : module->cells()) {
Module *submodule = design->module(cell->type);
Module *submodule = design->module(cell->type_impl);
if (!submodule)
continue;
module_queue(design, submodule, modules_sorted, modules_processed);

2
passes/techmap/extractinv.cc
View file

@ -84,7 +84,7 @@ struct ExtractinvPass : public Pass {
{
for (auto cell : module->selected_cells())
for (auto port : cell->connections()) {
auto cell_module = design->module(cell->type);
auto cell_module = design->module(cell->type_impl);
if (!cell_module)
continue;
auto cell_wire = cell_module->wire(port.first);

2
passes/techmap/iopadmap.cc
View file

@ -90,7 +90,7 @@ struct IopadmapPass : public Pass {
if (modules_processed.count(module))
return;
for (auto cell : module->cells()) {
Module *submodule = design->module(cell->type);
Module *submodule = design->module(cell->type_impl);
if (!submodule)
continue;
module_queue(design, submodule, modules_sorted, modules_processed);