mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-21 14:45:50 +00:00
Code Activity

Merge remote-tracking branch 'upstream/main' into silimate

Browse source
This commit is contained in:
Mohamed Gaber 2026-06-09 16:22:51 +03:00
commit e58125b605
No known key found for this signature in database
834 changed files with 25281 additions and 8780 deletions
Download patch file Download diff file Expand all files Collapse all files

1
tests/various/.gitignore vendored
View file

@ -16,3 +16,4 @@
/ports_only_in_*.txt
/ports_nets_in_*.v
/ports_only_in_*.v
/*.aig

8
tests/various/async.sh
View file

@ -1,9 +1,9 @@
#!/usr/bin/env bash
set -ex
../../yosys -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v
../../yosys -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v
../../yosys -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v
../../yosys -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v
${YOSYS} -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v
${YOSYS} -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v
${YOSYS} -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v
${YOSYS} -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v
iverilog -o async_sim -DTESTBENCH async.v async_???.v
vvp -N async_sim > async.out
tail async.out

8
tests/various/chparam.sh
View file

@ -35,18 +35,18 @@ module top #(
endmodule
EOT
if ../../yosys -q -p 'verific -sv chparam1.sv'; then
../../yosys -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
if ${YOSYS} -q -p 'verific -sv chparam1.sv'; then
${YOSYS} -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
-p 'async2sync' \
-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
../../yosys -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
${YOSYS} -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
-p 'async2sync' \
-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
fi
../../yosys -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
${YOSYS} -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
-p 'async2sync' \
-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'

4
tests/various/clk2fflogic_effects.sh
View file

@ -3,14 +3,14 @@ set -e
# TODO: when sim gets native $check support, remove the -DNO_ASSERT here
echo Running yosys sim
../../yosys -q -p "
${YOSYS} -q -p "
read_verilog -formal -DNO_ASSERT clk2fflogic_effects.sv
hierarchy -top top; proc;;
tee -q -o clk2fflogic_effects.sim.log sim -q -n 32
"
echo Running yosys clk2fflogic sim
../../yosys -q -p "
${YOSYS} -q -p "
read_verilog -formal clk2fflogic_effects.sv
hierarchy -top top; proc;;
clk2fflogic;;

49
tests/various/const_shift_empty_arg.ys Normal file
View file

@ -0,0 +1,49 @@
# Regression test for #5684: const_shift_worker must not crash when arg1 is
# empty.
read_json << EOF
{
"modules": {
"sshl": {
"cells": {
"sshlCell": {
"connections": {
"A": [],
"B": [3],
"Y": [1]
},
"parameters": {
"A_SIGNED": "1",
"A_WIDTH": "0",
"B_SIGNED": "0",
"B_WIDTH": "1",
"Y_WIDTH": "1"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"type": "$sshl"
}
},
"ports": {
"A": {
"bits": [],
"direction": "input"
},
"B": {
"bits": [3],
"direction": "input"
},
"Y": {
"bits": [1],
"direction": "output"
}
}
}
}
}
EOF
eval -set B 0 -show Y sshl

2
tests/various/ezcmdline_dummy_solver
View file

@ -1,4 +1,4 @@
#!/bin/sh
#!/usr/bin/env sh
# Dummy SAT solver for ezCmdlineSAT tests.
# Accepts exactly two CNF shapes:
# - SAT: p cnf 1 1; clause: "1 0" -> exits 10 with v 1

10
tests/various/ezcmdline_plugin.sh
View file

@ -4,9 +4,9 @@ DIR=$(cd "$(dirname "$0")" && pwd)
BASEDIR=$(cd "$DIR/../.." && pwd)
rm -f "$DIR/ezcmdline_plugin.so"
chmod +x "$DIR/ezcmdline_dummy_solver"
CXXFLAGS=$("$BASEDIR/yosys-config" --cxxflags)
DATDIR=$("$BASEDIR/yosys-config" --datdir)
CXXFLAGS=$(${YOSYS_CONFIG} --cxxflags)
DATDIR=$(${YOSYS_CONFIG} --datdir)
DATDIR=${DATDIR//\//\\\/}
CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share}
"$BASEDIR/yosys-config" --exec --cxx ${CXXFLAGS} -I"$BASEDIR" --ldflags -shared -o "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc"
"$BASEDIR/yosys" -m "$DIR/ezcmdline_plugin.so" -p "ezcmdline_test -cmd $DIR/ezcmdline_dummy_solver" | grep -q "ezcmdline_test passed!"
CXXFLAGS=${CXXFLAGS//$DATDIR/$BUILD_DIR/share}
${YOSYS_CONFIG} --exec --cxx ${CXXFLAGS} -I"$BASEDIR" --ldflags -shared -o "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc"
${YOSYS} -m "$DIR/ezcmdline_plugin.so" -p "ezcmdline_test -cmd $DIR/ezcmdline_dummy_solver" | grep -q "ezcmdline_test passed!"

8
tests/various/generate_mk.py Normal file
View file

@ -0,0 +1,8 @@
#!/usr/bin/env python3
import sys
sys.path.append("..")
import gen_tests_makefile
gen_tests_makefile.generate(["--yosys-scripts", "--bash"])

6
tests/various/hierarchy.sh
View file

@ -4,7 +4,7 @@
set -e
echo -n " TOP first - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
${YOSYS} -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module TOP(a, y);
input a;
@ -23,7 +23,7 @@ echo -n " TOP first - "
EOY
echo -n " TOP last - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
${YOSYS} -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module aoi12(a, y);
input a;
@ -42,7 +42,7 @@ echo -n " TOP last - "
EOY
echo -n " no explicit top - "
../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
${YOSYS} -s - <<- EOY | grep "Automatically selected noTop as design top module."
read_verilog << EOV
module aoi12(a, y);
input a;

2
tests/various/logger_cmd_error.sh
View file

@ -2,7 +2,7 @@
trap 'echo "ERROR in logger_cmd_error.sh" >&2; exit 1' ERR
(../../yosys -v 3 -C <<EOF
(${YOSYS} -v 3 -C <<EOF
yosys -import
hierarchy -top nonexistent
EOF

2
tests/various/logger_fail.sh
View file

@ -10,7 +10,7 @@ runTest() {
want="$2"
shift 2
echo "running '$desc' with args $@"
output=`../../yosys -q "$@" 2>&1`
output=`${YOSYS} -q "$@" 2>&1`
if [ $? -ne 1 ]; then
fail "exit code for '$desc' was not 1"
fi

9
tests/various/muxpack_wide_y.ys Normal file
View file

@ -0,0 +1,9 @@
# Regression test for issue #5734: muxpack crash when $logic_not / $eq / $reduce_or
# has Y port width > 1 (e.g. boolean result assigned to a wide wire).
read_verilog <<EOT
module top(input b, output [18:0] h);
assign h = ~|b;
endmodule
EOT
proc
muxpack

163
tests/various/peepopt.ys
View file

@ -8,8 +8,8 @@ prep -nokeepdc
equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 1 t:$shiftx
select -assert-count 0 t:$shiftx t:* %D
select -assert-count 1 t:$bmux
select -assert-count 0 t:$bmux t:* %D
####################
@ -72,9 +72,10 @@ design -import gate -as gate peepopt_shiftmul_3
miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
sat -verify -show-public -enable_undef -prove-asserts miter
cd gate
select -assert-count 1 t:$shr
select -assert-count 1 t:$mul
select -assert-count 0 t:$shr t:$mul %% t:* %D
clean
select -assert-count 1 t:$bmux
select -assert-count 0 t:$shr
select -assert-count 0 t:$mul
####################
@ -92,3 +93,155 @@ equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 0 t:*
####################
# shiftpow2: a power-of-two part-select i[s*W+:W] becomes a $bmux word mux
design -reset
read_verilog <<EOT
module peepopt_shiftpow2_0 #(parameter M=8, parameter W=4) (input [M*W-1:0] i, input [$clog2(M)-1:0] s, output [W-1:0] o);
assign o = i[s*W+:W];
endmodule
EOT
prep -nokeepdc
equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 1 t:$bmux
select -assert-count 0 t:$bmux t:* %D
####################
# shiftpow2: explicit aligned right shift D >> (S*8), checked by SAT miter
design -reset
read_verilog <<EOT
module peepopt_shiftpow2_1 (input [63:0] D, input [2:0] S, output [7:0] Y);
assign Y = D >> (S*8);
endmodule
EOT
prep
design -save gold
peepopt
design -stash gate
design -import gold -as gold peepopt_shiftpow2_1
design -import gate -as gate peepopt_shiftpow2_1
miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
sat -verify -show-public -enable_undef -prove-asserts miter
cd gate
clean
select -assert-count 1 t:$bmux
select -assert-count 0 t:$shr
####################
# shiftpow2: width smaller than stride is non-overlapping
design -reset
read_verilog <<EOT
module peepopt_shiftpow2_narrow (input [31:0] D, input [2:0] S, output [3:0] Y);
assign Y = D >> (S*8);
endmodule
EOT
prep
design -save gold
peepopt
design -stash gate
design -import gold -as gold peepopt_shiftpow2_narrow
design -import gate -as gate peepopt_shiftpow2_narrow
miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
sat -verify -show-public -enable_undef -prove-asserts miter
cd gate
clean
select -assert-count 1 t:$bmux
select -assert-count 0 t:$shr
####################
# shiftpow2: signed part-select with out-of-range padding
design -reset
read_verilog <<EOT
module peepopt_shiftpow2_signed (input signed [15:0] i, input [2:0] s, output [3:0] o);
assign o = i[s*4 +: 4];
endmodule
EOT
prep
# drive wreduce to a fixed point before checking for the reduced shift
wreduce
design -save gold
peepopt
design -stash gate
design -import gold -as gold peepopt_shiftpow2_signed
design -import gate -as gate peepopt_shiftpow2_signed
miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
sat -verify -show-public -enable_undef -prove-asserts miter
cd gate
clean
select -assert-count 1 t:$bmux
select -assert-count 0 t:$shiftx
####################
# shiftpow2: signed $shr extends A to Y_WIDTH
design -reset
read_verilog <<EOT
module peepopt_shiftpow2_signed_shr (input signed [3:0] D, input S, output [7:0] Y);
assign Y = D >> (S*8);
endmodule
EOT
prep
design -save gold
peepopt
design -stash gate
design -import gold -as gold peepopt_shiftpow2_signed_shr
design -import gate -as gate peepopt_shiftpow2_signed_shr
miter -equiv -make_assert -make_outputs -flatten gold gate miter
sat -verify -show-public -prove-asserts miter
cd gate
clean
select -assert-count 1 t:$bmux
select -assert-count 0 t:$shr
####################
# shiftpow2 must NOT fire for overlapping selections
design -reset
read_verilog <<EOT
module peepopt_shiftpow2_overlap (input [31:0] D, input [1:0] S, output [7:0] Y);
assign Y = D >> (S*4);
endmodule
EOT
prep -nokeepdc
peepopt
clean
select -assert-count 0 t:$bmux
select -assert-count 1 t:$shr
####################
# shiftpow2: shiftmul can expose a non-overlapping power-of-two stride
design -reset
read_verilog <<EOT
module peepopt_shiftpow2_shiftmul #(parameter M=8, parameter W=3) (input [M*W-1:0] i, input [2:0] s, output [W-1:0] o);
assign o = i[s*W+:W];
endmodule
EOT
prep -nokeepdc
equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 1 t:$bmux
select -assert-count 0 t:$bmux t:* %D

12
tests/various/plugin.sh
View file

@ -1,12 +1,12 @@
set -e
rm -f plugin.so
rm -rf plugin_search
CXXFLAGS=$(../../yosys-config --cxxflags)
DATDIR=$(../../yosys-config --datdir)
CXXFLAGS=$(${YOSYS_CONFIG} --cxxflags)
DATDIR=$(${YOSYS_CONFIG} --datdir)
DATDIR=${DATDIR//\//\\\/}
CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share}
../../yosys-config --exec --cxx ${CXXFLAGS} --ldflags -shared -o plugin.so plugin.cc
../../yosys -m ./plugin.so -p "test" | grep -q "Plugin test passed!"
CXXFLAGS=${CXXFLAGS//$DATDIR/$BUILD_DIR/share}
${YOSYS_CONFIG} --exec --cxx ${CXXFLAGS} --ldflags -shared -o plugin.so plugin.cc
${YOSYS} -m ./plugin.so -p "test" | grep -q "Plugin test passed!"
mkdir -p plugin_search
mv plugin.so plugin_search/plugin.so
YOSYS_PLUGIN_PATH=$PWD/plugin_search ../../yosys -m plugin.so -p "test" | grep -q "Plugin test passed!"
YOSYS_PLUGIN_PATH=$PWD/plugin_search ${YOSYS} -m plugin.so -p "test" | grep -q "Plugin test passed!"

4
tests/various/run-test.sh
View file

@ -1,4 +0,0 @@
#!/usr/bin/env bash
set -eu
source ../gen-tests-makefile.sh
generate_mk --yosys-scripts --bash

32
tests/various/setundef_selection.ys Normal file
View file

@ -0,0 +1,32 @@
# Test that setundef -zero respects wire selection: only selected wire is changed
read_verilog <<EOT
module test;
wire a = 1'bx;
wire b = 1'bx;
endmodule
EOT
setundef -zero w:a
sat -prove a 0
sat -enable_undef -prove b 0 -falsify
design -reset
# Test that setundef -undriven -zero respects wire selection
read_verilog setundef_selection_undriven.v
setundef -undriven -zero w:b
sat -prove b 0
sat -enable_undef -prove a 0 -falsify
design -reset
# Test that setundef -init respects cell selection: only selected FF gets init set
read_rtlil setundef_selection_ff.il
setundef -init -zero c:myff_a
select -assert-count 1 w:* a:init %i
select -assert-count 0 w:b a:init %i
design -reset
# Test that setundef -init works with wire selection
read_rtlil setundef_selection_ff.il
setundef -init -zero w:a
select -assert-count 1 w:* a:init %i
select -assert-count 0 w:b a:init %i
design -reset

19
tests/various/setundef_selection_ff.il Normal file
View file

@ -0,0 +1,19 @@
module \test
wire input 1 \clk
wire output 2 \a
wire output 3 \b
cell $dff \myff_a
parameter \WIDTH 1
parameter \CLK_POLARITY 1'1
connect \D \a
connect \Q \a
connect \CLK \clk
end
cell $dff \myff_b
parameter \WIDTH 1
parameter \CLK_POLARITY 1'1
connect \D \b
connect \Q \b
connect \CLK \clk
end
end

4
tests/various/setundef_selection_undriven.v Normal file
View file

@ -0,0 +1,4 @@
module test;
wire a;
wire b;
endmodule

4
tests/various/specify.ys
View file

@ -43,7 +43,7 @@ select n:C_* -assert-count 2
equiv_make gold gate equiv
hierarchy -top equiv
equiv_struct
equiv_induct -seq 5
equiv_induct -ignore-unknown-cells -seq 5
equiv_status -assert
design -reset
@ -57,7 +57,7 @@ select n:B_* -assert-count 2
equiv_make gold gate equiv
hierarchy -top equiv
equiv_struct
equiv_induct -seq 5
equiv_induct -ignore-unknown-cells -seq 5
equiv_status -assert
design -reset

20
tests/various/sv_implicit_ports.sh
View file

@ -3,7 +3,7 @@
trap 'echo "ERROR in sv_implicit_ports.sh" >&2; exit 1' ERR
# Simple case
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -15,7 +15,7 @@ endmodule
EOT
# Generate block
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -31,7 +31,7 @@ endmodule
EOT
# Missing wire
((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
((${YOSYS} -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -43,7 +43,7 @@ EOT
) 2>&1 | grep -F "ERROR: No matching wire for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
# Incorrectly sized wire
((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
((${YOSYS} -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -56,7 +56,7 @@ EOT
) 2>&1 | grep -F "ERROR: Width mismatch between wire (7 bits) and port (8 bits) for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
# Defaults
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a = 8'd00, input [7:0] b = 8'd01, output [7:0] q);
assign q = a + b;
endmodule
@ -67,7 +67,7 @@ endmodule
EOT
# Parameterised module
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add #(parameter N=3) (input [N-1:0] a = 8'd00, input [N-1:0] b = 8'd01, output [N-1:0] q);
assign q = a + b;
endmodule
@ -78,7 +78,7 @@ endmodule
EOT
# Parameterised blackbox module
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - <<EOT
(* blackbox *)
module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
endmodule
@ -89,7 +89,7 @@ endmodule
EOT
# Parameterised blackbox module - incorrect width
((../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - || true) <<EOT
((${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - || true) <<EOT
(* blackbox *)
module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
endmodule
@ -101,7 +101,7 @@ EOT
) 2>&1 | grep -F "ERROR: Width mismatch between wire (8 bits) and port (6 bits) for implicit port connection \`q' of cell top.add_i (add)." > /dev/null
# Mixed implicit and explicit 1
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -112,7 +112,7 @@ endmodule
EOT
# Mixed implicit and explicit 2
(../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
(${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule

24
tests/various/svalways.sh
View file

@ -3,7 +3,7 @@
trap 'echo "ERROR in svalways.sh" >&2; exit 1' ERR
# Good case
../../yosys -f "verilog -sv" -qp proc - <<EOT
${YOSYS} -f "verilog -sv" -qp proc - <<EOT
module top(input clk, en, d, output reg p, q, r);
always_ff @(posedge clk)
@ -18,8 +18,22 @@ always_latch
endmodule
EOT
# Good case: dynamic memory writes in always_latch create nosync mem2reg
# temporaries, but only the memory words themselves should be checked for
# latch inference.
${YOSYS} -f "verilog -sv" -qp proc - <<EOT
module top(input [3:0] addr, input we, input [31:0] data);
logic [31:0] regs [0:15];
always_latch
if (we)
regs[addr] = data;
endmodule
EOT
# Incorrect always_comb syntax
((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
((${YOSYS} -f "verilog -sv" -qp proc -|| true) <<EOT
module top(input d, output reg q);
always_comb @(d)
@ -30,7 +44,7 @@ EOT
) 2>&1 | grep -F "<stdin>:3: ERROR: syntax error, unexpected '@'" > /dev/null
# Incorrect use of always_comb
((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
((${YOSYS} -f "verilog -sv" -qp proc -|| true) <<EOT
module top(input en, d, output reg q);
always_comb
@ -41,7 +55,7 @@ EOT
) 2>&1 | grep -F "ERROR: Latch inferred for signal \`\\top.\\q' from always_comb process" > /dev/null
# Incorrect use of always_latch
((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
((${YOSYS} -f "verilog -sv" -qp proc -|| true) <<EOT
module top(input en, d, output reg q);
always_latch
@ -52,7 +66,7 @@ EOT
) 2>&1 | grep -F "ERROR: No latch inferred for signal \`\\top.\\q' from always_latch process" > /dev/null
# Incorrect use of always_ff
((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
((${YOSYS} -f "verilog -sv" -qp proc -|| true) <<EOT
module top(input en, d, output reg q);
always_ff @(*)

2
tests/various/wrapcell.ys
View file

@ -45,7 +45,7 @@ module top(
endmodule
EOF
opt_clean -unusedbitsattr
opt_clean
wreduce
wrapcell -setattr foo -formatattr bar w{Y_WIDTH} -name OR_{A_WIDTH}_{B_WIDTH}_{Y_WIDTH}{%unused}
check -assert