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Merge remote-tracking branch 'upstream/main' into silimate

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Mohamed Gaber 2026-06-09 16:22:51 +03:00
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125
techlibs/xilinx/CMakeLists.txt Normal file
View file

@ -0,0 +1,125 @@
yosys_pass(xilinx_dffopt
xilinx_dffopt.cc
)
pmgen_command(xilinx_dsp
xilinx_dsp.pmg
)
pmgen_command(xilinx_dsp48a
xilinx_dsp48a.pmg
)
pmgen_command(xilinx_dsp_CREG
xilinx_dsp_CREG.pmg
)
pmgen_command(xilinx_dsp_cascade
xilinx_dsp_cascade.pmg
)
yosys_pass(xilinx_dsp
xilinx_dsp.cc
${PMGEN_xilinx_dsp_OUTPUT}
${PMGEN_xilinx_dsp48a_OUTPUT}
${PMGEN_xilinx_dsp_CREG_OUTPUT}
${PMGEN_xilinx_dsp_cascade_OUTPUT}
)
pmgen_command(xilinx_srl
xilinx_srl.pmg
)
yosys_pass(xilinx_srl
xilinx_srl.cc
${PMGEN_xilinx_srl_OUTPUT}
)
yosys_pass(synth_xilinx
synth_xilinx.cc
REQUIRES
abc
alumacc
blackbox
check
chtype
clean
clkbufmap
deminout
dfflegalize
extractinv
flatten
fsm
hierarchy
iopadmap
memory
memory_dff
memory_libmap
memory_map
muxcover
muxpack
opt
opt_clean
opt_expr
opt_lut_ins
peepopt
pmux2shiftx
proc
read_verilog
select
setattr
share
simplemap
sort
stat
techmap
tribuf
wreduce
write_blif
write_edif
write_json
xilinx_dffopt
xilinx_dsp
xilinx_srl
zinit
DATA_DIR
xilinx
DATA_FILES
cells_map.v
cells_sim.v
cells_xtra.v
lutrams_xcv.txt
lutrams_xcv_map.v
lutrams_xc5v.txt
lutrams_xcu.txt
lutrams_xc5v_map.v
brams_xcv.txt
brams_xcv_map.v
brams_defs.vh
brams_xc2v.txt
brams_xc2v_map.v
brams_xc3sda.txt
brams_xc3sda_map.v
brams_xc4v.txt
brams_xc4v_map.v
brams_xc5v_map.v
brams_xc6v_map.v
brams_xcu_map.v
urams.txt
urams_map.v
arith_map.v
ff_map.v
lut_map.v
mux_map.v
xc3s_mult_map.v
xc3sda_dsp_map.v
xc6s_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc7_dsp_map.v
xcu_dsp_map.v
abc9_model.v
)

64
techlibs/xilinx/Makefile.inc
View file

@ -1,64 +0,0 @@
OBJS += techlibs/xilinx/synth_xilinx.o
OBJS += techlibs/xilinx/xilinx_dffopt.o
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xcv.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xcv_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xc5v.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xcu.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xc5v_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xcv.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xcv_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_defs.vh))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc2v.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc2v_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc3sda.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc3sda_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc4v.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc4v_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc5v_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc6v_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xcu_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/urams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/urams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3s_mult_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc4v_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc5v_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
OBJS += techlibs/xilinx/xilinx_dsp.o
GENFILES += techlibs/xilinx/xilinx_dsp_pm.h
GENFILES += techlibs/xilinx/xilinx_dsp48a_pm.h
GENFILES += techlibs/xilinx/xilinx_dsp_CREG_pm.h
GENFILES += techlibs/xilinx/xilinx_dsp_cascade_pm.h
techlibs/xilinx/xilinx_dsp.o: techlibs/xilinx/xilinx_dsp_pm.h techlibs/xilinx/xilinx_dsp48a_pm.h techlibs/xilinx/xilinx_dsp_CREG_pm.h techlibs/xilinx/xilinx_dsp_cascade_pm.h
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp_pm.h))
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp48a_pm.h))
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp_CREG_pm.h))
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_dsp_cascade_pm.h))
OBJS += techlibs/xilinx/xilinx_srl.o
GENFILES += techlibs/xilinx/xilinx_srl_pm.h
techlibs/xilinx/xilinx_srl.o: techlibs/xilinx/xilinx_srl_pm.h
$(eval $(call add_extra_objs,techlibs/xilinx/xilinx_srl_pm.h))

2
techlibs/xilinx/brams_xc6v_map.v
View file

@ -275,7 +275,7 @@ end else if (OPTION_MODE == "FULL") begin
.DIADI(DI[31:0]),
.DIBDI(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]),
.DIPADIP(DIP[3:0]),
.DIPBDIP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]),
.DIPBDIP(PORT_W_WIDTH == 72 ? DIP[7:4] : DIP[3:0]),
);
end

2
techlibs/xilinx/brams_xcu_map.v
View file

@ -215,7 +215,7 @@ end else if (OPTION_MODE == "FULL") begin
.DINADIN(DI[31:0]),
.DINBDIN(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]),
.DINPADINP(DIP[3:0]),
.DINPBDINP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]),
.DINPBDINP(PORT_W_WIDTH == 72 ? DIP[7:4] : DIP[3:0]),
);
end

8
techlibs/xilinx/synth_xilinx.cc
View file

@ -355,8 +355,10 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("prepare")) {
run("proc");
if (flatten || help_mode)
if (flatten || help_mode) {
run("check");
run("flatten", "(with '-flatten')");
}
if (active_design)
active_design->scratchpad_unset("tribuf.added_something");
run("tribuf -logic");
@ -635,8 +637,10 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_luts")) {
run("opt_expr -mux_undef -noclkinv");
if (flatten_before_abc)
if (flatten_before_abc) {
run("check");
run("flatten");
}
if (help_mode)
run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
else if (abc9) {

4
techlibs/xilinx/xilinx_dffopt.cc
View file

@ -131,7 +131,7 @@ struct XilinxDffOptPass : public Pass {
for (auto module : design->selected_modules())
{
log("Optimizing FFs in %s.\n", log_id(module));
log("Optimizing FFs in %s.\n", module);
SigMap sigmap(module);
dict<SigBit, pair<LutData, Cell *>> bit_to_lut;
@ -305,7 +305,7 @@ unmap:
if (worthy_post_r) ports += " + R";
if (worthy_post_s) ports += " + S";
if (worthy_post_ce) ports += " + CE";
log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, cell, sig_Q.wire, GetSize(lut_d.second), GetSize(final_lut.second));
// Okay, we're doing it. Unmap ports.
if (worthy_post_r) {

104
techlibs/xilinx/xilinx_dsp.cc
View file

@ -140,7 +140,7 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
}
}
log("Analysing %s.%s for Xilinx DSP SIMD12 packing.\n", log_id(module), log_id(lane1));
log("Analysing %s.%s for Xilinx DSP SIMD12 packing.\n", module, lane1);
Cell *cell = addDsp(module);
cell->setParam(ID(USE_SIMD), Const("FOUR12"));
@ -221,7 +221,7 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
Cell *lane2 = simd24.front();
simd24.pop_front();
log("Analysing %s.%s for Xilinx DSP SIMD24 packing.\n", log_id(module), log_id(lane1));
log("Analysing %s.%s for Xilinx DSP SIMD24 packing.\n", module, lane1);
Cell *cell = addDsp(module);
cell->setParam(ID(USE_SIMD), Const("TWO24"));
@ -260,29 +260,29 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
{
auto &st = pm.st_xilinx_dsp_pack;
log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
log("Analysing %s.%s for Xilinx DSP packing.\n", pm.module, st.dsp);
log_debug("preAdd: %s\n", log_id(st.preAdd, "--"));
log_debug("preSub: %s\n", log_id(st.preSub, "--"));
log_debug("ffAD: %s\n", log_id(st.ffAD, "--"));
log_debug("ffA2: %s\n", log_id(st.ffA2, "--"));
log_debug("ffA1: %s\n", log_id(st.ffA1, "--"));
log_debug("ffB2: %s\n", log_id(st.ffB2, "--"));
log_debug("ffB1: %s\n", log_id(st.ffB1, "--"));
log_debug("ffD: %s\n", log_id(st.ffD, "--"));
log_debug("dsp: %s\n", log_id(st.dsp, "--"));
log_debug("ffM: %s\n", log_id(st.ffM, "--"));
log_debug("postAdd: %s\n", log_id(st.postAdd, "--"));
log_debug("postAddMux: %s\n", log_id(st.postAddMux, "--"));
log_debug("ffP: %s\n", log_id(st.ffP, "--"));
log_debug("overflow: %s\n", log_id(st.overflow, "--"));
log_debug("preAdd: %s\n", st.preAdd ? st.preAdd->name.unescape() : "--");
log_debug("preSub: %s\n", st.preSub ? st.preSub->name.unescape() : "--");
log_debug("ffAD: %s\n", st.ffAD ? st.ffAD->name.unescape() : "--");
log_debug("ffA2: %s\n", st.ffA2 ? st.ffA2->name.unescape() : "--");
log_debug("ffA1: %s\n", st.ffA1 ? st.ffA1->name.unescape() : "--");
log_debug("ffB2: %s\n", st.ffB2 ? st.ffB2->name.unescape() : "--");
log_debug("ffB1: %s\n", st.ffB1 ? st.ffB1->name.unescape() : "--");
log_debug("ffD: %s\n", st.ffD ? st.ffD->name.unescape() : "--");
log_debug("dsp: %s\n", st.dsp ? st.dsp->name.unescape() : "--");
log_debug("ffM: %s\n", st.ffM ? st.ffM->name.unescape() : "--");
log_debug("postAdd: %s\n", st.postAdd ? st.postAdd->name.unescape() : "--");
log_debug("postAddMux: %s\n", st.postAddMux ? st.postAddMux->name.unescape() : "--");
log_debug("ffP: %s\n", st.ffP ? st.ffP->name.unescape() : "--");
log_debug("overflow: %s\n", st.overflow ? st.overflow->name.unescape() : "--");
Cell *cell = st.dsp;
if (st.preAdd || st.preSub) {
Cell* preAdder = st.preAdd ? st.preAdd : st.preSub;
log(" preadder %s (%s)\n", log_id(preAdder), log_id(preAdder->type));
log(" preadder %s (%s)\n", preAdder, preAdder->type.unescape());
bool A_SIGNED = preAdder->getParam(ID::A_SIGNED).as_bool();
bool D_SIGNED = preAdder->getParam(ID::B_SIGNED).as_bool();
if (st.sigA == preAdder->getPort(ID::B))
@ -312,7 +312,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
pm.autoremove(preAdder);
}
if (st.postAdd) {
log(" postadder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
log(" postadder %s (%s)\n", st.postAdd, st.postAdd->type.unescape());
SigSpec &opmode = cell->connections_.at(ID(OPMODE));
if (st.postAddMux) {
@ -338,7 +338,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
pm.autoremove(st.postAdd);
}
if (st.overflow) {
log(" overflow %s (%s)\n", log_id(st.overflow), log_id(st.overflow->type));
log(" overflow %s (%s)\n", st.overflow, st.overflow->type.unescape());
cell->setParam(ID(USE_PATTERN_DETECT), Const("PATDET"));
cell->setParam(ID(SEL_PATTERN), Const("PATTERN"));
cell->setParam(ID(SEL_MASK), Const("MASK"));
@ -456,28 +456,28 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), "posedge");
if (st.ffA2) {
log(" ffA2:%s", log_id(st.ffA2));
log(" ffA2:%s", st.ffA2);
if (st.ffA1)
log(" ffA1:%s", log_id(st.ffA1));
log(" ffA1:%s", st.ffA1);
}
if (st.ffAD)
log(" ffAD:%s", log_id(st.ffAD));
log(" ffAD:%s", st.ffAD);
if (st.ffB2) {
log(" ffB2:%s", log_id(st.ffB2));
log(" ffB2:%s", st.ffB2);
if (st.ffB1)
log(" ffB1:%s", log_id(st.ffB1));
log(" ffB1:%s", st.ffB1);
}
if (st.ffD)
log(" ffD:%s", log_id(st.ffD));
log(" ffD:%s", st.ffD);
if (st.ffM)
log(" ffM:%s", log_id(st.ffM));
log(" ffM:%s", st.ffM);
if (st.ffP)
log(" ffP:%s", log_id(st.ffP));
log(" ffP:%s", st.ffP);
}
log("\n");
@ -493,25 +493,25 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
{
auto &st = pm.st_xilinx_dsp48a_pack;
log("Analysing %s.%s for Xilinx DSP48A/DSP48A1 packing.\n", log_id(pm.module), log_id(st.dsp));
log("Analysing %s.%s for Xilinx DSP48A/DSP48A1 packing.\n", pm.module, st.dsp);
log_debug("preAdd: %s\n", log_id(st.preAdd, "--"));
log_debug("ffA1: %s\n", log_id(st.ffA1, "--"));
log_debug("ffA0: %s\n", log_id(st.ffA0, "--"));
log_debug("ffB1: %s\n", log_id(st.ffB1, "--"));
log_debug("ffB0: %s\n", log_id(st.ffB0, "--"));
log_debug("ffD: %s\n", log_id(st.ffD, "--"));
log_debug("dsp: %s\n", log_id(st.dsp, "--"));
log_debug("ffM: %s\n", log_id(st.ffM, "--"));
log_debug("postAdd: %s\n", log_id(st.postAdd, "--"));
log_debug("postAddMux: %s\n", log_id(st.postAddMux, "--"));
log_debug("ffP: %s\n", log_id(st.ffP, "--"));
log_debug("preAdd: %s\n", st.preAdd ? st.preAdd->name.unescape() : "--");
log_debug("ffA1: %s\n", st.ffA1 ? st.ffA1->name.unescape() : "--");
log_debug("ffA0: %s\n", st.ffA0 ? st.ffA0->name.unescape() : "--");
log_debug("ffB1: %s\n", st.ffB1 ? st.ffB1->name.unescape() : "--");
log_debug("ffB0: %s\n", st.ffB0 ? st.ffB0->name.unescape() : "--");
log_debug("ffD: %s\n", st.ffD ? st.ffD->name.unescape() : "--");
log_debug("dsp: %s\n", st.dsp ? st.dsp->name.unescape() : "--");
log_debug("ffM: %s\n", st.ffM ? st.ffM->name.unescape() : "--");
log_debug("postAdd: %s\n", st.postAdd ? st.postAdd->name.unescape() : "--");
log_debug("postAddMux: %s\n", st.postAddMux ? st.postAddMux->name.unescape() : "--");
log_debug("ffP: %s\n", st.ffP ? st.ffP->name.unescape() : "--");
Cell *cell = st.dsp;
SigSpec &opmode = cell->connections_.at(ID(OPMODE));
if (st.preAdd) {
log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
log(" preadder %s (%s)\n", st.preAdd, st.preAdd->type.unescape());
bool D_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
st.sigB.extend_u0(18, B_SIGNED);
@ -529,7 +529,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
pm.autoremove(st.preAdd);
}
if (st.postAdd) {
log(" postadder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
log(" postadder %s (%s)\n", st.postAdd, st.postAdd->type.unescape());
if (st.postAddMux) {
log_assert(st.ffP);
@ -639,23 +639,23 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), "posedge");
if (st.ffA0)
log(" ffA0:%s", log_id(st.ffA0));
log(" ffA0:%s", st.ffA0);
if (st.ffA1)
log(" ffA1:%s", log_id(st.ffA1));
log(" ffA1:%s", st.ffA1);
if (st.ffB0)
log(" ffB0:%s", log_id(st.ffB0));
log(" ffB0:%s", st.ffB0);
if (st.ffB1)
log(" ffB1:%s", log_id(st.ffB1));
log(" ffB1:%s", st.ffB1);
if (st.ffD)
log(" ffD:%s", log_id(st.ffD));
log(" ffD:%s", st.ffD);
if (st.ffM)
log(" ffM:%s", log_id(st.ffM));
log(" ffM:%s", st.ffM);
if (st.ffP)
log(" ffP:%s", log_id(st.ffP));
log(" ffP:%s", st.ffP);
}
log("\n");
@ -671,8 +671,8 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
{
auto &st = pm.st_xilinx_dsp_packC;
log_debug("Analysing %s.%s for Xilinx DSP packing (CREG).\n", log_id(pm.module), log_id(st.dsp));
log_debug("ffC: %s\n", log_id(st.ffC, "--"));
log_debug("Analysing %s.%s for Xilinx DSP packing (CREG).\n", pm.module, st.dsp);
log_debug("ffC: %s\n", st.ffC ? st.ffC->name.unescape() : "--");
Cell *cell = st.dsp;
@ -724,7 +724,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), "posedge");
if (st.ffC)
log(" ffC:%s", log_id(st.ffC));
log(" ffC:%s", st.ffC);
log("\n");
}

8
techlibs/xilinx/xilinx_dsp_cascade.pmg
View file

@ -114,7 +114,7 @@ finally
}
dsp_pcin->setPort(\OPMODE, opmode);
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", dsp, dsp_pcin);
}
if (AREG >= 0) {
Wire *cascade = module->addWire(NEW_ID, 30);
@ -128,7 +128,7 @@ finally
dsp->setParam(\ACASCREG, AREG);
dsp_pcin->setParam(\A_INPUT, Const("CASCADE"));
log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
log_debug("ACOUT -> ACIN cascade for %s -> %s\n", dsp, dsp_pcin);
}
if (BREG >= 0) {
Wire *cascade = module->addWire(NEW_ID, 18);
@ -161,11 +161,11 @@ finally
dsp_pcin->setParam(\B_INPUT, Const("CASCADE"));
}
log_debug("BCOUT -> BCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
log_debug("BCOUT -> BCIN cascade for %s -> %s\n", dsp, dsp_pcin);
}
}
else {
log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE);
log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", dsp, dsp_pcin, MAX_DSP_CASCADE);
}
dsp = dsp_pcin;

12
techlibs/xilinx/xilinx_srl.cc
View file

@ -30,11 +30,11 @@ void run_fixed(xilinx_srl_pm &pm)
{
auto &st = pm.st_fixed;
auto &ud = pm.ud_fixed;
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), st.first->type.unescape());
SigSpec initval;
for (auto cell : ud.longest_chain) {
log_debug(" %s\n", log_id(cell));
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
SigBit Q = cell->getPort(ID::Q);
log_assert(Q.wire);
@ -100,7 +100,7 @@ void run_fixed(xilinx_srl_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
log(" -> %s (%s)\n", c, c->type.unescape());
}
void run_variable(xilinx_srl_pm &pm)
@ -108,13 +108,13 @@ void run_variable(xilinx_srl_pm &pm)
auto &st = pm.st_variable;
auto &ud = pm.ud_variable;
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type));
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), st.first->type.unescape());
SigSpec initval;
for (const auto &i : ud.chain) {
auto cell = i.first;
auto slice = i.second;
log_debug(" %s\n", log_id(cell));
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
SigBit Q = cell->getPort(ID::Q)[slice];
log_assert(Q.wire);
@ -181,7 +181,7 @@ void run_variable(xilinx_srl_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
log(" -> %s (%s)\n", c, c->type.unescape());
}
struct XilinxSrlPass : public Pass {