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Merge remote-tracking branch 'upstream/main' into silimate

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This commit is contained in:
Mohamed Gaber 2026-06-09 16:22:51 +03:00
commit e58125b605
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834 changed files with 25281 additions and 8780 deletions
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84
techlibs/ice40/CMakeLists.txt Normal file
View file

@ -0,0 +1,84 @@
yosys_pass(ice40_braminit
ice40_braminit.cc
)
yosys_pass(ice40_opt
ice40_opt.cc
REQUIRES
opt_expr
opt_merge
opt_dff
opt_clean
)
pmgen_command(ice40_dsp
ice40_dsp.pmg
)
yosys_pass(ice40_dsp
ice40_dsp.cc
${PMGEN_ice40_dsp_OUTPUT}
)
pmgen_command(ice40_wrapcarry
ice40_wrapcarry.pmg
)
yosys_pass(ice40_wrapcarry
ice40_wrapcarry.cc
${PMGEN_ice40_wrapcarry_OUTPUT}
)
yosys_pass(synth_ice40
synth_ice40.cc
REQUIRES
abc
abc9
alumacc
autoname
blackbox
check
chtype
clean
deminout
dfflegalize
flatten
flowmap
fsm
hierarchy
ice40_braminit
ice40_dsp
ice40_opt
ice40_wrapcarry
memory
memory_dff
memory_libmap
memory_map
opt
opt_clean
opt_expr
opt_lut
peepopt
proc
read_verilog
select
setattr
share
simplemap
stat
techmap
tribuf
wreduce
write_blif
write_edif
write_json
DATA_DIR
ice40
DATA_FILES
arith_map.v
cells_map.v
ff_map.v
cells_sim.v
latches_map.v
brams.txt
brams_map.v
spram.txt
spram_map.v
dsp_map.v
abc9_model.v
)

26
techlibs/ice40/Makefile.inc
View file

@ -1,26 +0,0 @@
OBJS += techlibs/ice40/synth_ice40.o
OBJS += techlibs/ice40/ice40_braminit.o
OBJS += techlibs/ice40/ice40_opt.o
$(eval $(call add_share_file,share/ice40,techlibs/ice40/arith_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/ff_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/spram.txt))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/spram_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_model.v))
OBJS += techlibs/ice40/ice40_dsp.o
GENFILES += techlibs/ice40/ice40_dsp_pm.h
techlibs/ice40/ice40_dsp.o: techlibs/ice40/ice40_dsp_pm.h
$(eval $(call add_extra_objs,techlibs/ice40/ice40_dsp_pm.h))
OBJS += techlibs/ice40/ice40_wrapcarry.o
GENFILES += techlibs/ice40/ice40_wrapcarry_pm.h
techlibs/ice40/ice40_wrapcarry.o: techlibs/ice40/ice40_wrapcarry_pm.h
$(eval $(call add_extra_objs,techlibs/ice40/ice40_wrapcarry_pm.h))

2
techlibs/ice40/ice40_braminit.cc
View file

@ -46,7 +46,7 @@ static void run_ice40_braminit(Module *module)
continue;
/* Open file */
log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file);
log("Processing %s : %s\n", cell, init_file);
std::ifstream f;
f.open(init_file.c_str());

38
techlibs/ice40/ice40_dsp.cc
View file

@ -29,17 +29,17 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
{
auto &st = pm.st_ice40_dsp;
log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
log("Checking %s.%s for iCE40 DSP inference.\n", pm.module, st.mul);
log_debug("ffA: %s\n", log_id(st.ffA, "--"));
log_debug("ffB: %s\n", log_id(st.ffB, "--"));
log_debug("ffCD: %s\n", log_id(st.ffCD, "--"));
log_debug("mul: %s\n", log_id(st.mul, "--"));
log_debug("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
log_debug("ffH: %s\n", log_id(st.ffH, "--"));
log_debug("add: %s\n", log_id(st.add, "--"));
log_debug("mux: %s\n", log_id(st.mux, "--"));
log_debug("ffO: %s\n", log_id(st.ffO, "--"));
log_debug("ffA: %s\n", st.ffA ? st.ffA->name.unescape() : "--");
log_debug("ffB: %s\n", st.ffB ? st.ffB->name.unescape() : "--");
log_debug("ffCD: %s\n", st.ffCD ? st.ffCD->name.unescape() : "--");
log_debug("mul: %s\n", st.mul ? st.mul->name.unescape() : "--");
log_debug("ffFJKG: %s\n", st.ffFJKG ? st.ffFJKG->name.unescape() : "--");
log_debug("ffH: %s\n", st.ffH ? st.ffH->name.unescape() : "--");
log_debug("add: %s\n", st.add ? st.add->name.unescape() : "--");
log_debug("mux: %s\n", st.mux ? st.mux->name.unescape() : "--");
log_debug("ffO: %s\n", st.ffO ? st.ffO->name.unescape() : "--");
log_debug("\n");
if (GetSize(st.sigA) > 16) {
@ -64,7 +64,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
Cell *cell = st.mul;
if (cell->type == ID($mul)) {
log(" replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
log(" replacing %s with SB_MAC16 cell.\n", st.mul->type.unescape());
cell = pm.module->addCell(NEW_ID, ID(SB_MAC16));
pm.module->swap_names(cell, st.mul);
@ -135,22 +135,22 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), st.clock_pol ? "posedge" : "negedge");
if (st.ffA)
log(" ffA:%s", log_id(st.ffA));
log(" ffA:%s", st.ffA);
if (st.ffB)
log(" ffB:%s", log_id(st.ffB));
log(" ffB:%s", st.ffB);
if (st.ffCD)
log(" ffCD:%s", log_id(st.ffCD));
log(" ffCD:%s", st.ffCD);
if (st.ffFJKG)
log(" ffFJKG:%s", log_id(st.ffFJKG));
log(" ffFJKG:%s", st.ffFJKG);
if (st.ffH)
log(" ffH:%s", log_id(st.ffH));
log(" ffH:%s", st.ffH);
if (st.ffO)
log(" ffO:%s", log_id(st.ffO));
log(" ffO:%s", st.ffO);
log("\n");
}
@ -196,9 +196,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
if (st.add) {
accum = (st.ffO && st.add->getPort(st.addAB == ID::A ? ID::B : ID::A) == st.sigO);
if (accum)
log(" accumulator %s (%s)\n", log_id(st.add), log_id(st.add->type));
log(" accumulator %s (%s)\n", st.add, st.add->type.unescape());
else
log(" adder %s (%s)\n", log_id(st.add), log_id(st.add->type));
log(" adder %s (%s)\n", st.add, st.add->type.unescape());
cell->setPort(ID(ADDSUBTOP), st.add->type == ID($add) ? State::S0 : State::S1);
cell->setPort(ID(ADDSUBBOT), st.add->type == ID($add) ? State::S0 : State::S1);
} else {

6
techlibs/ice40/ice40_opt.cc
View file

@ -83,7 +83,7 @@ static void run_ice40_opts(Module *module)
module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
module, cell, log_signal(replacement_output));
module->remove(cell);
}
continue;
@ -137,7 +137,7 @@ static void run_ice40_opts(Module *module)
module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
module, cell, log_signal(replacement_output));
cell->type = ID($lut);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) });
@ -175,7 +175,7 @@ static void run_ice40_opts(Module *module)
remap_lut:
module->design->scratchpad_set_bool("opt.did_something", true);
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", log_id(module), log_id(cell));
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", module, cell);
cell->type = ID($lut);
cell->setParam(ID::WIDTH, 4);

4
techlibs/ice40/ice40_wrapcarry.cc
View file

@ -31,8 +31,8 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
#if 0
log("\n");
log("carry: %s\n", log_id(st.carry, "--"));
log("lut: %s\n", log_id(st.lut, "--"));
log("carry: %s\n", st.carry ? st.carry->name.unescape() : "--");
log("lut: %s\n", st.lut ? st.lut->name.unescape() : "--");
#endif
log(" replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n");

1
techlibs/ice40/synth_ice40.cc
View file

@ -309,6 +309,7 @@ struct SynthIce40Pass : public ScriptPass
if (check_label("flatten", "(unless -noflatten)"))
{
if (flatten) {
run("check");
run("flatten");
run("tribuf -logic");
run("deminout");