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Merge remote-tracking branch 'upstream/main' into silimate

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Mohamed Gaber 2026-06-09 16:22:51 +03:00
commit e58125b605
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834 changed files with 25281 additions and 8780 deletions
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55
techlibs/gowin/CMakeLists.txt Normal file
View file

@ -0,0 +1,55 @@
yosys_pass(synth_gowin
synth_gowin.cc
REQUIRES
abc
abc9
alumacc
autoname
blackbox
check
clean
deminout
dfflegalize
flatten
fsm
hierarchy
hilomap
iopadmap
memory
memory_libmap
memory_map
opt
opt_clean
opt_expr
opt_lut_ins
peepopt
proc
read_verilog
setundef
share
simplemap
sort
splitnets
stat
techmap
tribuf
wreduce
write_json
write_verilog
DATA_DIR
gowin
DATA_FILES
cells_map.v
cells_sim.v
cells_latch.v
cells_xtra_gw1n.v
cells_xtra_gw2a.v
cells_xtra_gw5a.v
arith_map.v
brams_map.v
brams_map_gw5a.v
brams.txt
lutrams_map.v
lutrams.txt
dsp_map.v
)

15
techlibs/gowin/Makefile.inc
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@ -1,15 +0,0 @@
OBJS += techlibs/gowin/synth_gowin.o
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra_gw1n.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra_gw2a.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra_gw5a.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map_gw5a.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/dsp_map.v))

5
techlibs/gowin/brams.txt
View file

@ -51,11 +51,6 @@ ram block $__GOWIN_DP_ {
portoption "WRITE_MODE" 1 {
rdwr new;
}
ifndef gw5a {
portoption "WRITE_MODE" 2 {
rdwr old;
}
}
wrbe_separate;
}
}

2
techlibs/gowin/brams_map.v
View file

@ -205,7 +205,7 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST;
wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_B_WR_BE);
wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE);
generate

2
techlibs/gowin/brams_map_gw5a.v
View file

@ -205,7 +205,7 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST;
wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_B_WR_BE);
wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE);
generate

37
techlibs/gowin/cells_latch.v Normal file
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@ -0,0 +1,37 @@
`default_nettype none
// DL D Latch with Positive Gate
module \$_DLATCH_P_ (input E, D, output Q);
DL _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DLN D Latch with Negative Gate
module \$_DLATCH_N_ (input E, D, output Q);
DLN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DLC D Latch with Positive Gate and Asynchronous Clear
module \$_DLATCH_PP0_ (input E, R, D, output Q);
DLC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E), .CLEAR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DLNC D Latch with Negative Gate and Asynchronous Clear
module \$_DLATCH_NP0_ (input E, R, D, output Q);
DLNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E), .CLEAR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DLP D Latch with Positive Gate and Asynchronous Preset
module \$_DLATCH_PP1_ (input E, R, D, output Q);
DLP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E), .PRESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DLNP D Latch with Negative Gate and Asynchronous Preset
module \$_DLATCH_NP1_ (input E, R, D, output Q);
DLNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E), .PRESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule

95
techlibs/gowin/cells_sim.v
View file

@ -540,6 +540,101 @@ module DFFNCE (output reg Q, input D, CLK, CE, CLEAR);
end
endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)
// Latch sim cells
// Gate signal uses CLK port name to match the physical DFF BEL pin
module DL (output reg Q, input D, CLK);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (CLK) Q <= D;
endmodule
module DLN (output reg Q, input D, CLK);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (!CLK) Q <= D;
endmodule
module DLE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (CLK && CE) Q <= D;
endmodule
module DLNE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (!CLK && CE) Q <= D;
endmodule
module DLC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (CLEAR) Q <= 1'b0;
else if (CLK) Q <= D;
endmodule
module DLCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (CLEAR) Q <= 1'b0;
else if (CLK && CE) Q <= D;
endmodule
module DLNC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (CLEAR) Q <= 1'b0;
else if (!CLK) Q <= D;
endmodule
module DLNCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (CLEAR) Q <= 1'b0;
else if (!CLK && CE) Q <= D;
endmodule
module DLP (output reg Q, input D, CLK, PRESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (PRESET) Q <= 1'b1;
else if (CLK) Q <= D;
endmodule
module DLPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (PRESET) Q <= 1'b1;
else if (CLK && CE) Q <= D;
endmodule
module DLNP (output reg Q, input D, CLK, PRESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (PRESET) Q <= 1'b1;
else if (!CLK) Q <= D;
endmodule
module DLNPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (PRESET) Q <= 1'b1;
else if (!CLK && CE) Q <= D;
endmodule
// TODO add more DFF sim cells
module VCC(output V);

15
techlibs/gowin/synth_gowin.cc
View file

@ -265,8 +265,10 @@ struct SynthGowinPass : public ScriptPass
if (check_label("coarse"))
{
run("proc");
if (flatten || help_mode)
if (flatten || help_mode) {
run("check");
run("flatten", "(unless -noflatten)");
}
run("tribuf -logic");
run("deminout");
run("opt_expr");
@ -309,7 +311,7 @@ struct SynthGowinPass : public ScriptPass
if (nolutram)
args += " -no-auto-distributed";
}
run(stringf("memory_libmap -lib +/gowin/lutrams.txt -lib +/gowin/brams.txt -D %s", family) + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
run(stringf("memory_libmap -lib +/gowin/lutrams.txt -lib +/gowin/brams.txt%s", family == "gw5a" ? " -D gw5a" : "") + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
run(stringf("techmap -map +/gowin/lutrams_map.v -map +/gowin/brams_map%s.v", family == "gw5a" ? "_gw5a" : ""));
}
@ -340,17 +342,18 @@ struct SynthGowinPass : public ScriptPass
run("opt_clean");
if (family == "gw5a") {
if (strict_gw5a_dffs) {
run("dfflegalize -cell $_SDFFE_PP?P_ r -cell $_DFFE_PP?P_ r");
run("dfflegalize -cell $_SDFFE_PP?P_ r -cell $_DFFE_PP?P_ r -cell $_DLATCH_?_ x -cell $_DLATCH_?P?_ x");
} else {
run("dfflegalize -cell $_DFF_?_ 0 -cell $_SDFFE_PP?P_ r -cell $_DFFE_PP?P_ r");
run("dfflegalize -cell $_DFF_?_ 0 -cell $_SDFFE_PP?P_ r -cell $_DFFE_PP?P_ r -cell $_DLATCH_?_ x -cell $_DLATCH_?P?_ x");
}
} else {
if (nodffe)
run("dfflegalize -cell $_DFF_?_ 0 -cell $_SDFF_?P?_ r -cell $_DFF_?P?_ r");
run("dfflegalize -cell $_DFF_?_ 0 -cell $_SDFF_?P?_ r -cell $_DFF_?P?_ r -cell $_DLATCH_?_ x -cell $_DLATCH_?P?_ x");
else
run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r");
run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r -cell $_DLATCH_?_ x -cell $_DLATCH_?P?_ x");
}
run("techmap -map +/gowin/cells_map.v");
run("techmap -map +/gowin/cells_latch.v");
run("opt_expr -mux_undef");
run("simplemap");
}