mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-18 05:05:45 +00:00
Merge remote-tracking branch 'upstream/main' into silimate
This commit is contained in:
Mohamed Gaber
commit
e58125b605
834 changed files with 25281 additions and 8780 deletions
2
techlibs/common/.gitignore
vendored
2
techlibs/common/.gitignore
vendored
|
|
@ -1,2 +0,0 @@
|
|||
simlib_help.inc
|
||||
simcells_help.inc
|
||||
87
techlibs/common/CMakeLists.txt
Normal file
87
techlibs/common/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
if (YOSYS_ENABLE_ABC)
|
||||
set(abc_requires abc abc9)
|
||||
endif()
|
||||
yosys_pass(synth
|
||||
synth.cc
|
||||
DEFINITIONS
|
||||
$<$<BOOL:${YOSYS_ENABLE_ABC}>:YOSYS_ENABLE_ABC>
|
||||
REQUIRES
|
||||
${abc_requires}
|
||||
alumacc
|
||||
arith_tree
|
||||
booth
|
||||
check
|
||||
clean
|
||||
flatten
|
||||
flowmap
|
||||
fsm
|
||||
hierarchy
|
||||
memory
|
||||
memory_map
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
peepopt
|
||||
proc
|
||||
share
|
||||
stat
|
||||
techmap
|
||||
wreduce
|
||||
DATA_FILES
|
||||
simlib.v
|
||||
simcells.v
|
||||
techmap.v
|
||||
smtmap.v
|
||||
pmux2mux.v
|
||||
adff2dff.v
|
||||
dff2ff.v
|
||||
gate2lut.v
|
||||
cmp2lut.v
|
||||
mul2dsp.v
|
||||
abc9_model.v
|
||||
abc9_map.v
|
||||
abc9_unmap.v
|
||||
cmp2lcu.v
|
||||
cmp2softlogic.v
|
||||
|
||||
choices/kogge-stone.v
|
||||
choices/han-carlson.v
|
||||
choices/sklansky.v
|
||||
)
|
||||
|
||||
yosys_pass(prep
|
||||
prep.cc
|
||||
REQUIRES
|
||||
check
|
||||
flatten
|
||||
future
|
||||
hierarchy
|
||||
memory_collect
|
||||
memory_dff
|
||||
memory_memx
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
proc
|
||||
sort
|
||||
stat
|
||||
wreduce
|
||||
)
|
||||
|
||||
yosys_pass(opensta
|
||||
opensta.cc
|
||||
)
|
||||
|
||||
yosys_pass(sdc_expand
|
||||
sdc_expand.cc
|
||||
REQUIRES
|
||||
chtype
|
||||
design
|
||||
hierarchy
|
||||
icell_liberty
|
||||
memory
|
||||
opensta
|
||||
proc
|
||||
read_verilog
|
||||
write_verilog
|
||||
)
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
|
||||
ifneq ($(SMALL),1)
|
||||
OBJS += techlibs/common/synth.o
|
||||
OBJS += techlibs/common/prep.o
|
||||
OBJS += techlibs/common/opensta.o
|
||||
OBJS += techlibs/common/sdc_expand.o
|
||||
endif
|
||||
|
||||
GENFILES += techlibs/common/simlib_help.inc
|
||||
GENFILES += techlibs/common/simcells_help.inc
|
||||
|
||||
techlibs/common/simlib_help.inc: techlibs/common/cellhelp.py techlibs/common/simlib.v
|
||||
$(Q) mkdir -p techlibs/common
|
||||
$(P) $(PYTHON_EXECUTABLE) $^ > $@.new
|
||||
$(Q) mv $@.new $@
|
||||
|
||||
techlibs/common/simcells_help.inc: techlibs/common/cellhelp.py techlibs/common/simcells.v
|
||||
$(Q) mkdir -p techlibs/common
|
||||
$(P) $(PYTHON_EXECUTABLE) $^ > $@.new
|
||||
$(Q) mv $@.new $@
|
||||
|
||||
kernel/register.o: techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc
|
||||
|
||||
$(eval $(call add_share_file,share,techlibs/common/simlib.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/simcells.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/techmap.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/smtmap.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/abc9_model.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/abc9_map.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/abc9_unmap.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v))
|
||||
$(eval $(call add_share_file,share,techlibs/common/cmp2softlogic.v))
|
||||
$(eval $(call add_share_file,share/choices,techlibs/common/choices/kogge-stone.v))
|
||||
$(eval $(call add_share_file,share/choices,techlibs/common/choices/han-carlson.v))
|
||||
$(eval $(call add_share_file,share/choices,techlibs/common/choices/sklansky.v))
|
||||
|
|
@ -1,100 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
from __future__ import annotations
|
||||
import fileinput
|
||||
import json
|
||||
from pathlib import Path
|
||||
|
||||
class SimHelper:
|
||||
name: str = ""
|
||||
title: str = ""
|
||||
ports: str = ""
|
||||
source: str = ""
|
||||
desc: list[str]
|
||||
code: list[str]
|
||||
group: str = ""
|
||||
ver: str = "1"
|
||||
tags: list[str]
|
||||
|
||||
def __init__(self) -> None:
|
||||
self.desc = []
|
||||
self.tags = []
|
||||
|
||||
def __str__(self) -> str:
|
||||
printed_fields = [
|
||||
"name", "title", "ports", "source", "desc", "code", "group", "ver",
|
||||
"tags",
|
||||
]
|
||||
# generate C++ struct
|
||||
val = f"cell_help[{json.dumps(self.name)}] = "
|
||||
val += "{\n"
|
||||
for field in printed_fields:
|
||||
field_val = getattr(self, field)
|
||||
if isinstance(field_val, list):
|
||||
field_val = "\n".join(field_val)
|
||||
field_val = field_val.strip()
|
||||
val += f' {json.dumps(field_val)},\n'
|
||||
val += "};\n"
|
||||
return val
|
||||
|
||||
def simcells_reparse(cell: SimHelper):
|
||||
# cut manual signature
|
||||
cell.desc = cell.desc[3:]
|
||||
|
||||
# code-block truth table
|
||||
new_desc = []
|
||||
indent = ""
|
||||
for line in cell.desc:
|
||||
if line.startswith("Truth table:"):
|
||||
indent = " "
|
||||
new_desc.pop()
|
||||
new_desc.extend(["::", ""])
|
||||
new_desc.append(indent + line)
|
||||
cell.desc = new_desc
|
||||
|
||||
# set version
|
||||
cell.ver = "2a"
|
||||
|
||||
simHelper = SimHelper()
|
||||
|
||||
for line in fileinput.input():
|
||||
line = line.rstrip()
|
||||
# special comments
|
||||
if line.startswith("//-"):
|
||||
simHelper.desc.append(line[4:] if len(line) > 4 else "")
|
||||
elif line.startswith("//* "):
|
||||
_, key, val = line.split(maxsplit=2)
|
||||
setattr(simHelper, key, val)
|
||||
|
||||
# code parsing
|
||||
if line.startswith("module "):
|
||||
clean_line = line[7:].replace("\\", "").replace(";", "")
|
||||
simHelper.name, simHelper.ports = clean_line.split(maxsplit=1)
|
||||
simHelper.code = []
|
||||
short_filename = Path(fileinput.filename()).name
|
||||
simHelper.source = f'{short_filename}:{fileinput.filelineno()}'
|
||||
elif not line.startswith("endmodule"):
|
||||
line = " " + line
|
||||
try:
|
||||
simHelper.code.append(line.replace("\t", " "))
|
||||
except AttributeError:
|
||||
# no module definition, ignore line
|
||||
pass
|
||||
if line.startswith("endmodule"):
|
||||
short_filename = Path(fileinput.filename()).name
|
||||
if simHelper.ver == "1" and short_filename == "simcells.v":
|
||||
# default simcells parsing
|
||||
simcells_reparse(simHelper)
|
||||
|
||||
# check help
|
||||
if simHelper.desc and simHelper.ver == "1" and short_filename == "simlib.v" and simHelper.desc[1].startswith(' '):
|
||||
simHelper.desc.pop(1)
|
||||
|
||||
# check group
|
||||
assert simHelper.group, f"techlibs/common/{simHelper.source}: {simHelper.name} cell missing group"
|
||||
|
||||
# dump
|
||||
print(simHelper)
|
||||
# new
|
||||
simHelper = SimHelper()
|
||||
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
#if !defined(YOSYS_DISABLE_SPAWN)
|
||||
#if defined(YOSYS_ENABLE_SPAWN)
|
||||
struct OpenstaPass : public Pass
|
||||
{
|
||||
OpenstaPass() : Pass("opensta", "run OpenSTA") { }
|
||||
|
|
@ -98,7 +98,7 @@ struct OpenstaPass : public Pass
|
|||
|
||||
f_script << "read_verilog " << verilog_filename << "\n";
|
||||
f_script << "read_lib " << liberty_filename << "\n";
|
||||
f_script << "link_design " << RTLIL::unescape_id(top_mod->name) << "\n";
|
||||
f_script << "link_design " << top_mod->name.unescape() << "\n";
|
||||
f_script << "read_sdc " << sdc_filename << "\n";
|
||||
f_script << "write_sdc " << sdc_expanded_filename << "\n";
|
||||
f_script.close();
|
||||
|
|
|
|||
|
|
@ -1613,6 +1613,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R D | Q
|
||||
//- ---------+---
|
||||
//- - 0 0 - | x
|
||||
//- - - 0 - | 0
|
||||
//- - 0 - - | 1
|
||||
//- \ - - d | d
|
||||
|
|
@ -1641,6 +1642,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R D | Q
|
||||
//- ---------+---
|
||||
//- - 0 1 - | x
|
||||
//- - - 1 - | 0
|
||||
//- - 0 - - | 1
|
||||
//- \ - - d | d
|
||||
|
|
@ -1669,6 +1671,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R D | Q
|
||||
//- ---------+---
|
||||
//- - 1 0 - | x
|
||||
//- - - 0 - | 0
|
||||
//- - 1 - - | 1
|
||||
//- \ - - d | d
|
||||
|
|
@ -1697,6 +1700,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R D | Q
|
||||
//- ---------+---
|
||||
//- - 1 1 - | x
|
||||
//- - - 1 - | 0
|
||||
//- - 1 - - | 1
|
||||
//- \ - - d | d
|
||||
|
|
@ -1725,6 +1729,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R D | Q
|
||||
//- ---------+---
|
||||
//- - 0 0 - | x
|
||||
//- - - 0 - | 0
|
||||
//- - 0 - - | 1
|
||||
//- / - - d | d
|
||||
|
|
@ -1753,6 +1758,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R D | Q
|
||||
//- ---------+---
|
||||
//- - 0 1 - | x
|
||||
//- - - 1 - | 0
|
||||
//- - 0 - - | 1
|
||||
//- / - - d | d
|
||||
|
|
@ -1781,6 +1787,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R D | Q
|
||||
//- ---------+---
|
||||
//- - 1 0 - | x
|
||||
//- - - 0 - | 0
|
||||
//- - 1 - - | 1
|
||||
//- / - - d | d
|
||||
|
|
@ -1809,6 +1816,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R D | Q
|
||||
//- ---------+---
|
||||
//- - 1 1 - | x
|
||||
//- - - 1 - | 0
|
||||
//- - 1 - - | 1
|
||||
//- / - - d | d
|
||||
|
|
@ -1837,6 +1845,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 0 0 - - | x
|
||||
//- - - 0 - - | 0
|
||||
//- - 0 - - - | 1
|
||||
//- \ - - 0 d | d
|
||||
|
|
@ -1865,6 +1874,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 0 0 - - | x
|
||||
//- - - 0 - - | 0
|
||||
//- - 0 - - - | 1
|
||||
//- \ - - 1 d | d
|
||||
|
|
@ -1893,6 +1903,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 0 1 - - | x
|
||||
//- - - 1 - - | 0
|
||||
//- - 0 - - - | 1
|
||||
//- \ - - 0 d | d
|
||||
|
|
@ -1921,6 +1932,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 0 1 - - | x
|
||||
//- - - 1 - - | 0
|
||||
//- - 0 - - - | 1
|
||||
//- \ - - 1 d | d
|
||||
|
|
@ -1949,6 +1961,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 1 0 - - | x
|
||||
//- - - 0 - - | 0
|
||||
//- - 1 - - - | 1
|
||||
//- \ - - 0 d | d
|
||||
|
|
@ -1977,6 +1990,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 1 0 - - | x
|
||||
//- - - 0 - - | 0
|
||||
//- - 1 - - - | 1
|
||||
//- \ - - 1 d | d
|
||||
|
|
@ -2005,6 +2019,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 1 1 - - | x
|
||||
//- - - 1 - - | 0
|
||||
//- - 1 - - - | 1
|
||||
//- \ - - 0 d | d
|
||||
|
|
@ -2033,6 +2048,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 1 1 - - | x
|
||||
//- - - 1 - - | 0
|
||||
//- - 1 - - - | 1
|
||||
//- \ - - 1 d | d
|
||||
|
|
@ -2061,6 +2077,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 0 0 - - | x
|
||||
//- - - 0 - - | 0
|
||||
//- - 0 - - - | 1
|
||||
//- / - - 0 d | d
|
||||
|
|
@ -2089,6 +2106,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 0 0 - - | x
|
||||
//- - - 0 - - | 0
|
||||
//- - 0 - - - | 1
|
||||
//- / - - 1 d | d
|
||||
|
|
@ -2117,6 +2135,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 0 1 - - | x
|
||||
//- - - 1 - - | 0
|
||||
//- - 0 - - - | 1
|
||||
//- / - - 0 d | d
|
||||
|
|
@ -2145,6 +2164,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 0 1 - - | x
|
||||
//- - - 1 - - | 0
|
||||
//- - 0 - - - | 1
|
||||
//- / - - 1 d | d
|
||||
|
|
@ -2173,6 +2193,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 1 0 - - | x
|
||||
//- - - 0 - - | 0
|
||||
//- - 1 - - - | 1
|
||||
//- / - - 0 d | d
|
||||
|
|
@ -2201,6 +2222,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 1 0 - - | x
|
||||
//- - - 0 - - | 0
|
||||
//- - 1 - - - | 1
|
||||
//- / - - 1 d | d
|
||||
|
|
@ -2229,6 +2251,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 1 1 - - | x
|
||||
//- - - 1 - - | 0
|
||||
//- - 1 - - - | 1
|
||||
//- / - - 0 d | d
|
||||
|
|
@ -2257,6 +2280,7 @@ endmodule
|
|||
//-
|
||||
//- Truth table: C S R E D | Q
|
||||
//- -----------+---
|
||||
//- - 1 1 - - | x
|
||||
//- - - 1 - - | 0
|
||||
//- - 1 - - - | 1
|
||||
//- / - - 1 d | d
|
||||
|
|
|
|||
|
|
@ -1976,7 +1976,7 @@ endmodule
|
|||
// --------------------------------------------------------
|
||||
//* group spec
|
||||
|
||||
module \$specrule (EN_SRC, EN_DST, SRC, DST);
|
||||
module \$specrule (SRC_EN, DST_EN, SRC, DST);
|
||||
|
||||
parameter TYPE = "";
|
||||
parameter T_LIMIT = 0;
|
||||
|
|
@ -1991,7 +1991,7 @@ parameter SRC_POL = 0;
|
|||
parameter DST_PEN = 0;
|
||||
parameter DST_POL = 0;
|
||||
|
||||
input EN_SRC, EN_DST;
|
||||
input SRC_EN, DST_EN;
|
||||
input [SRC_WIDTH-1:0] SRC;
|
||||
input [DST_WIDTH-1:0] DST;
|
||||
|
||||
|
|
|
|||
|
|
@ -67,6 +67,10 @@ struct SynthPass : public ScriptPass {
|
|||
log(" -booth\n");
|
||||
log(" run the booth pass to map $mul to Booth encoded multipliers\n");
|
||||
log("\n");
|
||||
log(" -arith_tree\n");
|
||||
log(" run the arith_tree pass to convert $add/$sub chains and $macc cells to\n");
|
||||
log(" carry-save adder trees.\n");
|
||||
log("\n");
|
||||
log(" -noalumacc\n");
|
||||
log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n");
|
||||
log(" their direct form ($add, $sub, etc.).\n");
|
||||
|
|
@ -108,7 +112,7 @@ struct SynthPass : public ScriptPass {
|
|||
}
|
||||
|
||||
string top_module, fsm_opts, memory_opts, abc;
|
||||
bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, hieropt, relative_share;
|
||||
bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, arith_tree, hieropt, relative_share;
|
||||
int lut;
|
||||
std::vector<std::string> techmap_maps;
|
||||
|
||||
|
|
@ -127,6 +131,7 @@ struct SynthPass : public ScriptPass {
|
|||
noshare = false;
|
||||
flowmap = false;
|
||||
booth = false;
|
||||
arith_tree = false;
|
||||
hieropt = false;
|
||||
relative_share = false;
|
||||
abc = "abc";
|
||||
|
|
@ -187,7 +192,10 @@ struct SynthPass : public ScriptPass {
|
|||
booth = true;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (args[argidx] == "-arith_tree") {
|
||||
arith_tree = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nordff") {
|
||||
memory_opts += " -nordff";
|
||||
continue;
|
||||
|
|
@ -269,8 +277,10 @@ struct SynthPass : public ScriptPass {
|
|||
|
||||
if (check_label("coarse")) {
|
||||
run("proc");
|
||||
if (flatten || help_mode)
|
||||
if (flatten || help_mode) {
|
||||
run("check");
|
||||
run("flatten", " (if -flatten)");
|
||||
}
|
||||
run("opt_expr");
|
||||
run("opt_clean");
|
||||
run("check");
|
||||
|
|
@ -289,6 +299,8 @@ struct SynthPass : public ScriptPass {
|
|||
run("booth", " (if -booth)");
|
||||
if (!noalumacc)
|
||||
run("alumacc", " (unless -noalumacc)");
|
||||
if (arith_tree || help_mode)
|
||||
run("arith_tree", " (if -arith_tree)");
|
||||
if (!noshare)
|
||||
run("share", " (unless -noshare)");
|
||||
run("opt" + hieropt_flag);
|
||||
|
|
@ -301,7 +313,7 @@ struct SynthPass : public ScriptPass {
|
|||
run("memory_map");
|
||||
run("opt -full");
|
||||
if (help_mode) {
|
||||
run(techmap_cmd, " (unless -extra-map)");
|
||||
run(techmap_cmd, " (unless -extra-map)");
|
||||
run(techmap_cmd + " -map +/techmap.v -map <inject>", " (if -extra-map)");
|
||||
} else {
|
||||
std::string techmap_opts;
|
||||
|
|
@ -326,13 +338,13 @@ struct SynthPass : public ScriptPass {
|
|||
if ((!noabc && !flowmap) || help_mode) {
|
||||
#ifdef YOSYS_ENABLE_ABC
|
||||
if (help_mode) {
|
||||
run(abc + " -fast", " (unless -noabc, unless -lut)");
|
||||
run(abc + " -fast -lut k", "(unless -noabc, if -lut)");
|
||||
run(abc, " (unless -noabc, unless -lut)");
|
||||
run(abc + " -lut k", "(unless -noabc, if -lut)");
|
||||
} else {
|
||||
if (lut)
|
||||
run(stringf("%s -fast -lut %d", abc, lut));
|
||||
run(stringf("%s -lut %d", abc, lut));
|
||||
else
|
||||
run(abc + " -fast");
|
||||
run(abc);
|
||||
}
|
||||
run("opt -fast", " (unless -noabc)");
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ module _90_simplemap_compare_ops;
|
|||
endmodule
|
||||
|
||||
(* techmap_simplemap *)
|
||||
(* techmap_celltype = "$buf $pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx" *)
|
||||
(* techmap_celltype = "$buf $pos $slice $concat $mux $pmux $tribuf $bmux $bwmux $bweqx" *)
|
||||
module _90_simplemap_various;
|
||||
endmodule
|
||||
|
||||
|
|
@ -563,48 +563,6 @@ module _90_pow (A, B, Y);
|
|||
wire _TECHMAP_FAIL_ = 1;
|
||||
endmodule
|
||||
|
||||
|
||||
// --------------------------------------------------------
|
||||
// Parallel Multiplexers
|
||||
// --------------------------------------------------------
|
||||
|
||||
(* techmap_celltype = "$pmux" *)
|
||||
module _90_pmux (A, B, S, Y);
|
||||
parameter WIDTH = 1;
|
||||
parameter S_WIDTH = 1;
|
||||
|
||||
(* force_downto *)
|
||||
input [WIDTH-1:0] A;
|
||||
(* force_downto *)
|
||||
input [WIDTH*S_WIDTH-1:0] B;
|
||||
(* force_downto *)
|
||||
input [S_WIDTH-1:0] S;
|
||||
(* force_downto *)
|
||||
output [WIDTH-1:0] Y;
|
||||
|
||||
(* force_downto *)
|
||||
wire [WIDTH-1:0] Y_B;
|
||||
|
||||
genvar i, j;
|
||||
generate
|
||||
(* force_downto *)
|
||||
wire [WIDTH*S_WIDTH-1:0] B_AND_S;
|
||||
for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
|
||||
assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
|
||||
end:B_AND
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
|
||||
(* force_downto *)
|
||||
wire [S_WIDTH-1:0] B_AND_BITS;
|
||||
for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
|
||||
assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
|
||||
end:B_AND_BITS_COLLECT
|
||||
assign Y_B[i] = |B_AND_BITS;
|
||||
end:B_OR
|
||||
endgenerate
|
||||
|
||||
assign Y = |S ? Y_B : A;
|
||||
endmodule
|
||||
|
||||
// --------------------------------------------------------
|
||||
// Demultiplexers
|
||||
// --------------------------------------------------------
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue