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Merge remote-tracking branch 'upstream/main' into silimate

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This commit is contained in:
Mohamed Gaber 2026-06-09 16:22:51 +03:00
commit e58125b605
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834 changed files with 25281 additions and 8780 deletions
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2
techlibs/.gitignore vendored
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@ -1,2 +0,0 @@
blackbox.v
*_pm.h

20
techlibs/CMakeLists.txt Normal file
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@ -0,0 +1,20 @@
add_subdirectory(achronix)
add_subdirectory(analogdevices)
add_subdirectory(anlogic)
add_subdirectory(common)
add_subdirectory(coolrunner2)
add_subdirectory(easic)
add_subdirectory(efinix)
add_subdirectory(fabulous)
add_subdirectory(gatemate)
add_subdirectory(gowin)
add_subdirectory(greenpak4)
add_subdirectory(ice40)
add_subdirectory(intel)
add_subdirectory(intel_alm)
add_subdirectory(lattice)
add_subdirectory(microchip)
add_subdirectory(nanoxplore)
add_subdirectory(quicklogic)
add_subdirectory(sf2)
add_subdirectory(xilinx)

28
techlibs/achronix/CMakeLists.txt Normal file
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@ -0,0 +1,28 @@
yosys_pass(synth_achronix
synth_achronix.cc
REQUIRES
abc
blackbox
check
clean
deminout
dfflegalize
flatten
hierarchy
iopadmap
memory_map
opt
proc
read_verilog
setundef
stat
synth
techmap
tribuf
write_verilog
DATA_DIR
achronix
DATA_FILES
speedster22i/cells_sim.v
speedster22i/cells_map.v
)

6
techlibs/achronix/Makefile.inc
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@ -1,6 +0,0 @@
OBJS += techlibs/achronix/synth_achronix.o
$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v))
$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v))

1
techlibs/achronix/synth_achronix.cc
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@ -129,6 +129,7 @@ struct SynthAchronixPass : public ScriptPass {
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc");
run("check");
run("flatten");
run("tribuf -logic");
run("deminout");

65
techlibs/analogdevices/CMakeLists.txt Normal file
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@ -0,0 +1,65 @@
yosys_pass(synth_analogdevices
synth_analogdevices.cc
REQUIRES
abc
alumacc
blackbox
check
chtype
clean
delete
deminout
dfflegalize
flatten
fsm
hierarchy
iopadmap
memory
memory_dff
memory_libmap
memory_map
muxcover
muxpack
opt
opt_clean
opt_expr
opt_lut_ins
peepopt
pmux2shiftx
proc
read_verilog
select
setattr
share
simplemap
stat
techmap
tribuf
wreduce
write_edif
xilinx_dffopt
xilinx_dsp
xilinx_srl
zinit
DATA_DIR
analogdevices
DATA_FILES
cells_map.v
cells_sim.v
lutrams.txt
lutrams_map.v
brams_defs.vh
brams.txt
brams_map.v
arith_map.v
ff_map.v
lut_map.v
mux_map.v
dsp_map.v
abc9_model.v
)

39
techlibs/analogdevices/abc9_model.v Normal file
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@ -0,0 +1,39 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// ============================================================================
// Box containing MUXF7.[AB] + MUXF8,
// Necessary to make these an atomic unit so that
// ABC cannot optimise just one of the MUXF7 away
// and expect to save on its delay
(* abc9_box, lib_whitebox *)
module \$__ANALOGDEVICES_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
assign O = S1 ? (S0 ? I3 : I2)
: (S0 ? I1 : I0);
specify
(I0 => O) = 294;
(I1 => O) = 297;
(I2 => O) = 311;
(I3 => O) = 317;
(S0 => O) = 390;
(S1 => O) = 273;
endspecify
endmodule

173
techlibs/analogdevices/arith_map.v Normal file
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@ -0,0 +1,173 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// ============================================================================
// LCU
(* techmap_celltype = "$lcu" *)
module _80_analogdevices_lcu (P, G, CI, CO);
parameter WIDTH = 2;
(* force_downto *)
input [WIDTH-1:0] P, G;
input CI;
(* force_downto *)
output [WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = WIDTH <= 2;
genvar i;
generate
localparam CARRY4_COUNT = (WIDTH + 3) / 4;
localparam MAX_WIDTH = CARRY4_COUNT * 4;
localparam PAD_WIDTH = MAX_WIDTH - WIDTH;
(* force_downto *)
wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G};
(* force_downto *)
wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};
(* force_downto *)
wire [MAX_WIDTH-1:0] C;
assign CO = C;
generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
if (i == 0) begin
wire INITCO;
CRY4INIT init
(
.CYINIT(CI),
.CO (INITCO)
);
CRY4 carry4
(
.CYINIT(1'd0),
.CI (INITCO),
.DI (GG[i*4 +: 4]),
.S (S [i*4 +: 4]),
.CO (C [i*4 +: 4]),
);
end else begin
CRY4 carry4
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (GG[i*4 +: 4]),
.S (S [i*4 +: 4]),
.CO (C [i*4 +: 4]),
);
end
end endgenerate
endgenerate
endmodule
// ============================================================================
// ALU
(* techmap_celltype = "$alu" *)
module _80_analogdevices_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
genvar i;
localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
localparam MAX_WIDTH = CARRY4_COUNT * 4;
localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH;
(* force_downto *)
wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};
(* force_downto *)
wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA};
(* force_downto *)
wire [MAX_WIDTH-1:0] O;
(* force_downto *)
wire [MAX_WIDTH-1:0] C;
assign Y = O, CO = C;
genvar i;
generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
if (i == 0) begin
wire INITCO;
CRY4INIT init
(
.CYINIT(CI),
.CO (INITCO)
);
CRY4 carry4
(
.CYINIT(1'd0),
.CI (INITCO),
.DI (DI[i*4 +: 4]),
.S (S [i*4 +: 4]),
.O (O [i*4 +: 4]),
.CO (C [i*4 +: 4])
);
end else begin
CRY4 carry4
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (DI[i*4 +: 4]),
.S (S [i*4 +: 4]),
.O (O [i*4 +: 4]),
.CO (C [i*4 +: 4])
);
end
end endgenerate
assign X = S;
endmodule

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techlibs/analogdevices/brams.txt Normal file
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@ -0,0 +1,285 @@
ifdef IS_T16FFC {
ram block $__ANALOGDEVICES_BLOCKRAM_FULL_ {
option "ERR" "ECC" {
style "ECC";
option "SIZE" "2048x32" {
abits 11;
width 32;
byte 32;
option "MODE" "TDP" cost 4502;
option "MODE" "SDP" forbid;
option "MODE" "SP" forbid;
}
option "SIZE" "1024x32" {
abits 10;
width 32;
byte 32;
option "MODE" "TDP" forbid;
option "MODE" "SDP" cost 2402;
option "MODE" "SP" forbid;
}
}
option "ERR" "BP" {
style "BP";
option "SIZE" "2048x36" {
abits 11;
width 36;
byte 9;
option "MODE" "TDP" cost 4504;
option "MODE" "SDP" forbid;
option "MODE" "SP" forbid;
}
option "SIZE" "1024x36" {
abits 10;
width 36;
byte 9;
option "MODE" "TDP" forbid;
option "MODE" "SDP" cost 2404;
option "MODE" "SP" forbid;
}
}
option "ERR" "FP" {
style "FP";
option "SIZE" "2048x18" {
abits 11;
width 18;
byte 18;
option "MODE" "TDP" cost 2501;
option "MODE" "SDP" cost 2401;
option "MODE" "SP" forbid;
}
}
option "ERR" "NONE" {
option "SIZE" "8192x05" {
abits 13;
width 5;
byte 1;
option "MODE" "TDP" cost 2505;
option "MODE" "SDP" forbid;
option "MODE" "SP" forbid;
}
option "SIZE" "4096x09" {
abits 12;
width 9;
byte 1;
option "MODE" "TDP" cost 2509;
option "MODE" "SDP" forbid;
option "MODE" "SP" forbid;
}
option "SIZE" "4096x10" {
abits 12;
width 10;
byte 1;
option "MODE" "TDP" forbid;
option "MODE" "SDP" cost 2410;
option "MODE" "SP" forbid;
}
option "SIZE" "2048x20" {
abits 11;
width 20;
byte 1;
option "MODE" "TDP" forbid;
option "MODE" "SDP" forbid;
option "MODE" "SP" cost 2320;
}
option "SIZE" "2048x40" {
abits 11;
width 40;
byte 8;
option "MODE" "TDP" cost 4505;
option "MODE" "SDP" forbid;
option "MODE" "SP" forbid;
}
}
# supports any initialization value, but need to export memory files
init any;
option "MODE" "TDP" {
port srsw "A" {
clock anyedge;
clken;
rdwr no_change;
}
port srsw "B" {
clock anyedge;
clken;
rdwr no_change;
}
}
option "MODE" "SDP" {
port sw "A" {
clock anyedge;
clken;
}
port sr "B" {
clock anyedge;
clken;
}
}
option "MODE" "SP" {
port srsw "A" {
clock anyedge;
clken;
rdwr no_change;
}
}
}
}
ram block $__ANALOGDEVICES_BLOCKRAM_HALF_ {
option "ERR" "ECC" {
style "ECC";
option "SIZE" "1024x32" {
abits 10;
width 32;
byte 32;
option "MODE" "SDP" cost 2402;
option "MODE" "SP" forbid;
option "MODE" "SP2" forbid;
}
option "SIZE" "512x32" {
abits 9;
width 32;
byte 32;
option "MODE" "SDP" forbid;
option "MODE" "SP" cost 2302;
option "MODE" "SP2" forbid;
}
}
option "ERR" "BP" {
style "BP";
option "SIZE" "1024x36" {
abits 10;
width 36;
byte 9;
option "MODE" "SDP" cost 2404;
option "MODE" "SP" forbid;
option "MODE" "SP2" forbid;
}
option "SIZE" "512x36" {
abits 9;
width 36;
byte 9;
option "MODE" "SDP" forbid;
option "MODE" "SP" cost 2304;
option "MODE" "SP2" forbid;
}
}
option "ERR" "FP" {
style "FP";
option "SIZE" "1024x18" {
abits 10;
width 18;
byte 18;
option "MODE" "SDP" forbid;
option "MODE" "SP" forbid;
option "MODE" "SP2" cost 2301;
}
}
option "ERR" "NONE" {
option "SIZE" "4096x05" {
abits 12;
width 5;
byte 1;
option "MODE" "SDP" cost 2405;
option "MODE" "SP" cost 2305;
option "MODE" "SP2" forbid;
}
option "SIZE" "2048x09" {
abits 11;
width 9;
byte 1;
option "MODE" "SDP" cost 2409;
option "MODE" "SP" forbid;
option "MODE" "SP2" cost 2309;
}
option "SIZE" "2048x10" {
abits 11;
width 10;
byte 1;
option "MODE" "SDP" cost 2410;
option "MODE" "SP" forbid;
option "MODE" "SP2" forbid;
}
option "SIZE" "1024x20" {
abits 10;
width 20;
byte 1;
option "MODE" "SDP" forbid;
option "MODE" "SP" cost 2320;
option "MODE" "SP2" forbid;
}
option "SIZE" "1024x40" {
abits 10;
width 40;
byte 8;
option "MODE" "SDP" cost 2405;
option "MODE" "SP" forbid;
option "MODE" "SP2" forbid;
}
}
option "MODE" "SDP" {
ifdef IS_T16FFC forbid;
port sw "A" {
clock anyedge;
clken;
}
port sr "B" {
clock anyedge;
clken;
}
}
option "MODE" "SP" {
ifdef IS_T16FFC forbid;
port srsw "A" {
clock anyedge;
clken;
rdwr no_change;
}
}
option "MODE" "SP2" {
ifdef IS_T40LP forbid;
port srsw "A" {
clock anyedge;
clken;
rdwr no_change;
}
}
}
ifdef IS_T40LP {
ram block $__ANALOGDEVICES_BLOCKRAM_QUARTER_ {
option "ERR" "BP" {
style "BP";
option "SIZE" "512x18" {
abits 9;
width 18;
byte 9;
option "MODE" "SP2" cost 2202;
}
}
option "ERR" "NONE" {
option "SIZE" "2048x05" {
abits 11;
width 5;
byte 1;
option "MODE" "SP2" cost 2205;
}
option "SIZE" "1024x09" {
abits 10;
width 9;
byte 1;
option "MODE" "SP2" cost 2209;
}
}
option "MODE" "SP2" {
port srsw "A" {
clock anyedge;
clken;
rdwr no_change;
}
}
}
}

561
techlibs/analogdevices/brams_defs.vh Normal file
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@ -0,0 +1,561 @@
`define PARAMS_INIT_9 \
.INIT_00(slice_init('h00)), \
.INIT_01(slice_init('h01)), \
.INIT_02(slice_init('h02)), \
.INIT_03(slice_init('h03)), \
.INIT_04(slice_init('h04)), \
.INIT_05(slice_init('h05)), \
.INIT_06(slice_init('h06)), \
.INIT_07(slice_init('h07)), \
.INIT_08(slice_init('h08)), \
.INIT_09(slice_init('h09)), \
.INIT_0A(slice_init('h0a)), \
.INIT_0B(slice_init('h0b)), \
.INIT_0C(slice_init('h0c)), \
.INIT_0D(slice_init('h0d)), \
.INIT_0E(slice_init('h0e)), \
.INIT_0F(slice_init('h0f)), \
.INIT_10(slice_init('h10)), \
.INIT_11(slice_init('h11)), \
.INIT_12(slice_init('h12)), \
.INIT_13(slice_init('h13)), \
.INIT_14(slice_init('h14)), \
.INIT_15(slice_init('h15)), \
.INIT_16(slice_init('h16)), \
.INIT_17(slice_init('h17)), \
.INIT_18(slice_init('h18)), \
.INIT_19(slice_init('h19)), \
.INIT_1A(slice_init('h1a)), \
.INIT_1B(slice_init('h1b)), \
.INIT_1C(slice_init('h1c)), \
.INIT_1D(slice_init('h1d)), \
.INIT_1E(slice_init('h1e)), \
.INIT_1F(slice_init('h1f)),
`define PARAMS_INITP_9 \
.INITP_00(slice_initp('h00)), \
.INITP_01(slice_initp('h01)), \
.INITP_02(slice_initp('h02)), \
.INITP_03(slice_initp('h03)),
`define PARAMS_INIT_18 \
.INIT_00(slice_init('h00)), \
.INIT_01(slice_init('h01)), \
.INIT_02(slice_init('h02)), \
.INIT_03(slice_init('h03)), \
.INIT_04(slice_init('h04)), \
.INIT_05(slice_init('h05)), \
.INIT_06(slice_init('h06)), \
.INIT_07(slice_init('h07)), \
.INIT_08(slice_init('h08)), \
.INIT_09(slice_init('h09)), \
.INIT_0A(slice_init('h0a)), \
.INIT_0B(slice_init('h0b)), \
.INIT_0C(slice_init('h0c)), \
.INIT_0D(slice_init('h0d)), \
.INIT_0E(slice_init('h0e)), \
.INIT_0F(slice_init('h0f)), \
.INIT_10(slice_init('h10)), \
.INIT_11(slice_init('h11)), \
.INIT_12(slice_init('h12)), \
.INIT_13(slice_init('h13)), \
.INIT_14(slice_init('h14)), \
.INIT_15(slice_init('h15)), \
.INIT_16(slice_init('h16)), \
.INIT_17(slice_init('h17)), \
.INIT_18(slice_init('h18)), \
.INIT_19(slice_init('h19)), \
.INIT_1A(slice_init('h1a)), \
.INIT_1B(slice_init('h1b)), \
.INIT_1C(slice_init('h1c)), \
.INIT_1D(slice_init('h1d)), \
.INIT_1E(slice_init('h1e)), \
.INIT_1F(slice_init('h1f)), \
.INIT_20(slice_init('h20)), \
.INIT_21(slice_init('h21)), \
.INIT_22(slice_init('h22)), \
.INIT_23(slice_init('h23)), \
.INIT_24(slice_init('h24)), \
.INIT_25(slice_init('h25)), \
.INIT_26(slice_init('h26)), \
.INIT_27(slice_init('h27)), \
.INIT_28(slice_init('h28)), \
.INIT_29(slice_init('h29)), \
.INIT_2A(slice_init('h2a)), \
.INIT_2B(slice_init('h2b)), \
.INIT_2C(slice_init('h2c)), \
.INIT_2D(slice_init('h2d)), \
.INIT_2E(slice_init('h2e)), \
.INIT_2F(slice_init('h2f)), \
.INIT_30(slice_init('h30)), \
.INIT_31(slice_init('h31)), \
.INIT_32(slice_init('h32)), \
.INIT_33(slice_init('h33)), \
.INIT_34(slice_init('h34)), \
.INIT_35(slice_init('h35)), \
.INIT_36(slice_init('h36)), \
.INIT_37(slice_init('h37)), \
.INIT_38(slice_init('h38)), \
.INIT_39(slice_init('h39)), \
.INIT_3A(slice_init('h3a)), \
.INIT_3B(slice_init('h3b)), \
.INIT_3C(slice_init('h3c)), \
.INIT_3D(slice_init('h3d)), \
.INIT_3E(slice_init('h3e)), \
.INIT_3F(slice_init('h3f)),
`define PARAMS_INIT_18_U \
.INIT_00(slice_init('h40)), \
.INIT_01(slice_init('h41)), \
.INIT_02(slice_init('h42)), \
.INIT_03(slice_init('h43)), \
.INIT_04(slice_init('h44)), \
.INIT_05(slice_init('h45)), \
.INIT_06(slice_init('h46)), \
.INIT_07(slice_init('h47)), \
.INIT_08(slice_init('h48)), \
.INIT_09(slice_init('h49)), \
.INIT_0A(slice_init('h4a)), \
.INIT_0B(slice_init('h4b)), \
.INIT_0C(slice_init('h4c)), \
.INIT_0D(slice_init('h4d)), \
.INIT_0E(slice_init('h4e)), \
.INIT_0F(slice_init('h4f)), \
.INIT_10(slice_init('h50)), \
.INIT_11(slice_init('h51)), \
.INIT_12(slice_init('h52)), \
.INIT_13(slice_init('h53)), \
.INIT_14(slice_init('h54)), \
.INIT_15(slice_init('h55)), \
.INIT_16(slice_init('h56)), \
.INIT_17(slice_init('h57)), \
.INIT_18(slice_init('h58)), \
.INIT_19(slice_init('h59)), \
.INIT_1A(slice_init('h5a)), \
.INIT_1B(slice_init('h5b)), \
.INIT_1C(slice_init('h5c)), \
.INIT_1D(slice_init('h5d)), \
.INIT_1E(slice_init('h5e)), \
.INIT_1F(slice_init('h5f)), \
.INIT_20(slice_init('h60)), \
.INIT_21(slice_init('h61)), \
.INIT_22(slice_init('h62)), \
.INIT_23(slice_init('h63)), \
.INIT_24(slice_init('h64)), \
.INIT_25(slice_init('h65)), \
.INIT_26(slice_init('h66)), \
.INIT_27(slice_init('h67)), \
.INIT_28(slice_init('h68)), \
.INIT_29(slice_init('h69)), \
.INIT_2A(slice_init('h6a)), \
.INIT_2B(slice_init('h6b)), \
.INIT_2C(slice_init('h6c)), \
.INIT_2D(slice_init('h6d)), \
.INIT_2E(slice_init('h6e)), \
.INIT_2F(slice_init('h6f)), \
.INIT_30(slice_init('h70)), \
.INIT_31(slice_init('h71)), \
.INIT_32(slice_init('h72)), \
.INIT_33(slice_init('h73)), \
.INIT_34(slice_init('h74)), \
.INIT_35(slice_init('h75)), \
.INIT_36(slice_init('h76)), \
.INIT_37(slice_init('h77)), \
.INIT_38(slice_init('h78)), \
.INIT_39(slice_init('h79)), \
.INIT_3A(slice_init('h7a)), \
.INIT_3B(slice_init('h7b)), \
.INIT_3C(slice_init('h7c)), \
.INIT_3D(slice_init('h7d)), \
.INIT_3E(slice_init('h7e)), \
.INIT_3F(slice_init('h7f)),
`define PARAMS_INITP_18 \
.INITP_00(slice_initp('h00)), \
.INITP_01(slice_initp('h01)), \
.INITP_02(slice_initp('h02)), \
.INITP_03(slice_initp('h03)), \
.INITP_04(slice_initp('h04)), \
.INITP_05(slice_initp('h05)), \
.INITP_06(slice_initp('h06)), \
.INITP_07(slice_initp('h07)),
`define PARAMS_INIT_36 \
.INIT_00(slice_init('h00)), \
.INIT_01(slice_init('h01)), \
.INIT_02(slice_init('h02)), \
.INIT_03(slice_init('h03)), \
.INIT_04(slice_init('h04)), \
.INIT_05(slice_init('h05)), \
.INIT_06(slice_init('h06)), \
.INIT_07(slice_init('h07)), \
.INIT_08(slice_init('h08)), \
.INIT_09(slice_init('h09)), \
.INIT_0A(slice_init('h0a)), \
.INIT_0B(slice_init('h0b)), \
.INIT_0C(slice_init('h0c)), \
.INIT_0D(slice_init('h0d)), \
.INIT_0E(slice_init('h0e)), \
.INIT_0F(slice_init('h0f)), \
.INIT_10(slice_init('h10)), \
.INIT_11(slice_init('h11)), \
.INIT_12(slice_init('h12)), \
.INIT_13(slice_init('h13)), \
.INIT_14(slice_init('h14)), \
.INIT_15(slice_init('h15)), \
.INIT_16(slice_init('h16)), \
.INIT_17(slice_init('h17)), \
.INIT_18(slice_init('h18)), \
.INIT_19(slice_init('h19)), \
.INIT_1A(slice_init('h1a)), \
.INIT_1B(slice_init('h1b)), \
.INIT_1C(slice_init('h1c)), \
.INIT_1D(slice_init('h1d)), \
.INIT_1E(slice_init('h1e)), \
.INIT_1F(slice_init('h1f)), \
.INIT_20(slice_init('h20)), \
.INIT_21(slice_init('h21)), \
.INIT_22(slice_init('h22)), \
.INIT_23(slice_init('h23)), \
.INIT_24(slice_init('h24)), \
.INIT_25(slice_init('h25)), \
.INIT_26(slice_init('h26)), \
.INIT_27(slice_init('h27)), \
.INIT_28(slice_init('h28)), \
.INIT_29(slice_init('h29)), \
.INIT_2A(slice_init('h2a)), \
.INIT_2B(slice_init('h2b)), \
.INIT_2C(slice_init('h2c)), \
.INIT_2D(slice_init('h2d)), \
.INIT_2E(slice_init('h2e)), \
.INIT_2F(slice_init('h2f)), \
.INIT_30(slice_init('h30)), \
.INIT_31(slice_init('h31)), \
.INIT_32(slice_init('h32)), \
.INIT_33(slice_init('h33)), \
.INIT_34(slice_init('h34)), \
.INIT_35(slice_init('h35)), \
.INIT_36(slice_init('h36)), \
.INIT_37(slice_init('h37)), \
.INIT_38(slice_init('h38)), \
.INIT_39(slice_init('h39)), \
.INIT_3A(slice_init('h3a)), \
.INIT_3B(slice_init('h3b)), \
.INIT_3C(slice_init('h3c)), \
.INIT_3D(slice_init('h3d)), \
.INIT_3E(slice_init('h3e)), \
.INIT_3F(slice_init('h3f)), \
.INIT_40(slice_init('h40)), \
.INIT_41(slice_init('h41)), \
.INIT_42(slice_init('h42)), \
.INIT_43(slice_init('h43)), \
.INIT_44(slice_init('h44)), \
.INIT_45(slice_init('h45)), \
.INIT_46(slice_init('h46)), \
.INIT_47(slice_init('h47)), \
.INIT_48(slice_init('h48)), \
.INIT_49(slice_init('h49)), \
.INIT_4A(slice_init('h4a)), \
.INIT_4B(slice_init('h4b)), \
.INIT_4C(slice_init('h4c)), \
.INIT_4D(slice_init('h4d)), \
.INIT_4E(slice_init('h4e)), \
.INIT_4F(slice_init('h4f)), \
.INIT_50(slice_init('h50)), \
.INIT_51(slice_init('h51)), \
.INIT_52(slice_init('h52)), \
.INIT_53(slice_init('h53)), \
.INIT_54(slice_init('h54)), \
.INIT_55(slice_init('h55)), \
.INIT_56(slice_init('h56)), \
.INIT_57(slice_init('h57)), \
.INIT_58(slice_init('h58)), \
.INIT_59(slice_init('h59)), \
.INIT_5A(slice_init('h5a)), \
.INIT_5B(slice_init('h5b)), \
.INIT_5C(slice_init('h5c)), \
.INIT_5D(slice_init('h5d)), \
.INIT_5E(slice_init('h5e)), \
.INIT_5F(slice_init('h5f)), \
.INIT_60(slice_init('h60)), \
.INIT_61(slice_init('h61)), \
.INIT_62(slice_init('h62)), \
.INIT_63(slice_init('h63)), \
.INIT_64(slice_init('h64)), \
.INIT_65(slice_init('h65)), \
.INIT_66(slice_init('h66)), \
.INIT_67(slice_init('h67)), \
.INIT_68(slice_init('h68)), \
.INIT_69(slice_init('h69)), \
.INIT_6A(slice_init('h6a)), \
.INIT_6B(slice_init('h6b)), \
.INIT_6C(slice_init('h6c)), \
.INIT_6D(slice_init('h6d)), \
.INIT_6E(slice_init('h6e)), \
.INIT_6F(slice_init('h6f)), \
.INIT_70(slice_init('h70)), \
.INIT_71(slice_init('h71)), \
.INIT_72(slice_init('h72)), \
.INIT_73(slice_init('h73)), \
.INIT_74(slice_init('h74)), \
.INIT_75(slice_init('h75)), \
.INIT_76(slice_init('h76)), \
.INIT_77(slice_init('h77)), \
.INIT_78(slice_init('h78)), \
.INIT_79(slice_init('h79)), \
.INIT_7A(slice_init('h7a)), \
.INIT_7B(slice_init('h7b)), \
.INIT_7C(slice_init('h7c)), \
.INIT_7D(slice_init('h7d)), \
.INIT_7E(slice_init('h7e)), \
.INIT_7F(slice_init('h7f)),
`define PARAMS_INIT_36_U \
.INIT_00(slice_init('h80)), \
.INIT_01(slice_init('h81)), \
.INIT_02(slice_init('h82)), \
.INIT_03(slice_init('h83)), \
.INIT_04(slice_init('h84)), \
.INIT_05(slice_init('h85)), \
.INIT_06(slice_init('h86)), \
.INIT_07(slice_init('h87)), \
.INIT_08(slice_init('h88)), \
.INIT_09(slice_init('h89)), \
.INIT_0A(slice_init('h8a)), \
.INIT_0B(slice_init('h8b)), \
.INIT_0C(slice_init('h8c)), \
.INIT_0D(slice_init('h8d)), \
.INIT_0E(slice_init('h8e)), \
.INIT_0F(slice_init('h8f)), \
.INIT_10(slice_init('h90)), \
.INIT_11(slice_init('h91)), \
.INIT_12(slice_init('h92)), \
.INIT_13(slice_init('h93)), \
.INIT_14(slice_init('h94)), \
.INIT_15(slice_init('h95)), \
.INIT_16(slice_init('h96)), \
.INIT_17(slice_init('h97)), \
.INIT_18(slice_init('h98)), \
.INIT_19(slice_init('h99)), \
.INIT_1A(slice_init('h9a)), \
.INIT_1B(slice_init('h9b)), \
.INIT_1C(slice_init('h9c)), \
.INIT_1D(slice_init('h9d)), \
.INIT_1E(slice_init('h9e)), \
.INIT_1F(slice_init('h9f)), \
.INIT_20(slice_init('ha0)), \
.INIT_21(slice_init('ha1)), \
.INIT_22(slice_init('ha2)), \
.INIT_23(slice_init('ha3)), \
.INIT_24(slice_init('ha4)), \
.INIT_25(slice_init('ha5)), \
.INIT_26(slice_init('ha6)), \
.INIT_27(slice_init('ha7)), \
.INIT_28(slice_init('ha8)), \
.INIT_29(slice_init('ha9)), \
.INIT_2A(slice_init('haa)), \
.INIT_2B(slice_init('hab)), \
.INIT_2C(slice_init('hac)), \
.INIT_2D(slice_init('had)), \
.INIT_2E(slice_init('hae)), \
.INIT_2F(slice_init('haf)), \
.INIT_30(slice_init('hb0)), \
.INIT_31(slice_init('hb1)), \
.INIT_32(slice_init('hb2)), \
.INIT_33(slice_init('hb3)), \
.INIT_34(slice_init('hb4)), \
.INIT_35(slice_init('hb5)), \
.INIT_36(slice_init('hb6)), \
.INIT_37(slice_init('hb7)), \
.INIT_38(slice_init('hb8)), \
.INIT_39(slice_init('hb9)), \
.INIT_3A(slice_init('hba)), \
.INIT_3B(slice_init('hbb)), \
.INIT_3C(slice_init('hbc)), \
.INIT_3D(slice_init('hbd)), \
.INIT_3E(slice_init('hbe)), \
.INIT_3F(slice_init('hbf)), \
.INIT_40(slice_init('hc0)), \
.INIT_41(slice_init('hc1)), \
.INIT_42(slice_init('hc2)), \
.INIT_43(slice_init('hc3)), \
.INIT_44(slice_init('hc4)), \
.INIT_45(slice_init('hc5)), \
.INIT_46(slice_init('hc6)), \
.INIT_47(slice_init('hc7)), \
.INIT_48(slice_init('hc8)), \
.INIT_49(slice_init('hc9)), \
.INIT_4A(slice_init('hca)), \
.INIT_4B(slice_init('hcb)), \
.INIT_4C(slice_init('hcc)), \
.INIT_4D(slice_init('hcd)), \
.INIT_4E(slice_init('hce)), \
.INIT_4F(slice_init('hcf)), \
.INIT_50(slice_init('hd0)), \
.INIT_51(slice_init('hd1)), \
.INIT_52(slice_init('hd2)), \
.INIT_53(slice_init('hd3)), \
.INIT_54(slice_init('hd4)), \
.INIT_55(slice_init('hd5)), \
.INIT_56(slice_init('hd6)), \
.INIT_57(slice_init('hd7)), \
.INIT_58(slice_init('hd8)), \
.INIT_59(slice_init('hd9)), \
.INIT_5A(slice_init('hda)), \
.INIT_5B(slice_init('hdb)), \
.INIT_5C(slice_init('hdc)), \
.INIT_5D(slice_init('hdd)), \
.INIT_5E(slice_init('hde)), \
.INIT_5F(slice_init('hdf)), \
.INIT_60(slice_init('he0)), \
.INIT_61(slice_init('he1)), \
.INIT_62(slice_init('he2)), \
.INIT_63(slice_init('he3)), \
.INIT_64(slice_init('he4)), \
.INIT_65(slice_init('he5)), \
.INIT_66(slice_init('he6)), \
.INIT_67(slice_init('he7)), \
.INIT_68(slice_init('he8)), \
.INIT_69(slice_init('he9)), \
.INIT_6A(slice_init('hea)), \
.INIT_6B(slice_init('heb)), \
.INIT_6C(slice_init('hec)), \
.INIT_6D(slice_init('hed)), \
.INIT_6E(slice_init('hee)), \
.INIT_6F(slice_init('hef)), \
.INIT_70(slice_init('hf0)), \
.INIT_71(slice_init('hf1)), \
.INIT_72(slice_init('hf2)), \
.INIT_73(slice_init('hf3)), \
.INIT_74(slice_init('hf4)), \
.INIT_75(slice_init('hf5)), \
.INIT_76(slice_init('hf6)), \
.INIT_77(slice_init('hf7)), \
.INIT_78(slice_init('hf8)), \
.INIT_79(slice_init('hf9)), \
.INIT_7A(slice_init('hfa)), \
.INIT_7B(slice_init('hfb)), \
.INIT_7C(slice_init('hfc)), \
.INIT_7D(slice_init('hfd)), \
.INIT_7E(slice_init('hfe)), \
.INIT_7F(slice_init('hff)),
`define PARAMS_INITP_36 \
.INITP_00(slice_initp('h00)), \
.INITP_01(slice_initp('h01)), \
.INITP_02(slice_initp('h02)), \
.INITP_03(slice_initp('h03)), \
.INITP_04(slice_initp('h04)), \
.INITP_05(slice_initp('h05)), \
.INITP_06(slice_initp('h06)), \
.INITP_07(slice_initp('h07)), \
.INITP_08(slice_initp('h08)), \
.INITP_09(slice_initp('h09)), \
.INITP_0A(slice_initp('h0a)), \
.INITP_0B(slice_initp('h0b)), \
.INITP_0C(slice_initp('h0c)), \
.INITP_0D(slice_initp('h0d)), \
.INITP_0E(slice_initp('h0e)), \
.INITP_0F(slice_initp('h0f)),
`define MAKE_DO(do, dop, rdata) \
wire [63:0] do; \
wire [7:0] dop; \
assign rdata = { \
dop[7], \
do[63:56], \
dop[6], \
do[55:48], \
dop[5], \
do[47:40], \
dop[4], \
do[39:32], \
dop[3], \
do[31:24], \
dop[2], \
do[23:16], \
dop[1], \
do[15:8], \
dop[0], \
do[7:0] \
};
`define MAKE_DI(di, dip, wdata) \
wire [63:0] di; \
wire [7:0] dip; \
assign { \
dip[7], \
di[63:56], \
dip[6], \
di[55:48], \
dip[5], \
di[47:40], \
dip[4], \
di[39:32], \
dip[3], \
di[31:24], \
dip[2], \
di[23:16], \
dip[1], \
di[15:8], \
dip[0], \
di[7:0] \
} = wdata;
function [71:0] ival;
input integer width;
input [71:0] val;
if (width == 72)
ival = {
val[71],
val[62],
val[53],
val[44],
val[35],
val[26],
val[17],
val[8],
val[70:63],
val[61:54],
val[52:45],
val[43:36],
val[34:27],
val[25:18],
val[16:9],
val[7:0]
};
else if (width == 36)
ival = {
val[35],
val[26],
val[17],
val[8],
val[34:27],
val[25:18],
val[16:9],
val[7:0]
};
else if (width == 18)
ival = {
val[17],
val[8],
val[16:9],
val[7:0]
};
else
ival = val;
endfunction
function [255:0] slice_init;
input integer idx;
integer i;
for (i = 0; i < 32; i = i + 1)
slice_init[i*8+:8] = INIT[(idx * 32 + i)*9+:8];
endfunction
function [255:0] slice_initp;
input integer idx;
integer i;
for (i = 0; i < 256; i = i + 1)
slice_initp[i] = INIT[(idx * 256 + i)*9+8];
endfunction

238
techlibs/analogdevices/brams_map.v Normal file
View file

@ -0,0 +1,238 @@
module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...);
// libmap params
parameter INIT = 0;
parameter OPTION_MODE = "NONE";
parameter OPTION_SIZE = "NONE";
parameter OPTION_ERR = "NONE";
parameter PORT_A_WR_EN_WIDTH = 1;
parameter PORT_A_CLK_POL = 1;
parameter PORT_B_WR_EN_WIDTH = PORT_A_WR_EN_WIDTH;
parameter PORT_B_CLK_POL = 1;
// needs -force-params
parameter WIDTH = 40;
parameter ABITS = 13;
// non libmap params
`ifdef IS_T40LP
localparam NODE = "T40LP_Gen2.4";
`endif
`ifdef IS_T16FFC
localparam NODE = "T16FFC_Gen2.4";
`endif
// localparam BRAM_MODE = "SDP_2048x36_BP";
localparam BRAM_MODE = (OPTION_ERR!="NONE") ? {OPTION_MODE, "_", OPTION_SIZE, "_", OPTION_ERR} :
{OPTION_MODE, "_", OPTION_SIZE};
localparam PBITS = (OPTION_ERR=="BP") ? PORT_A_WR_EN_WIDTH : 1;
// libmap ports
input PORT_A_CLK;
input PORT_A_CLK_EN;
input [ABITS-1:0] PORT_A_ADDR;
input [WIDTH-1:0] PORT_A_WR_DATA;
output [WIDTH-1:0] PORT_A_RD_DATA;
input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
input PORT_B_CLK;
input PORT_B_CLK_EN;
input [ABITS-1:0] PORT_B_ADDR;
input [WIDTH-1:0] PORT_B_WR_DATA;
output [WIDTH-1:0] PORT_B_RD_DATA;
input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
`ifdef IS_T40LP
RBRAM
`endif
`ifdef IS_T16FFC
RBRAM2
`endif
#(
.TARGET_NODE(NODE),
.BRAM_MODE(BRAM_MODE),
.QA_REG((OPTION_ERR=="ECC") ? 1 : 0),
.QB_REG((OPTION_ERR=="ECC") ? 1 : 0),
.CLKA_INV(!PORT_A_CLK_POL),
.CLKB_INV(!PORT_B_CLK_POL),
.DATA_WIDTH(WIDTH),
.ADDR_WIDTH(ABITS),
.WE_WIDTH(PORT_A_WR_EN_WIDTH),
.PERR_WIDTH(PBITS),
)
_TECHMAP_REPLACE_
(
.QA(PORT_A_RD_DATA),
.DA(PORT_A_WR_DATA),
.CEA(PORT_A_CLK_EN),
.WEA(PORT_A_WR_EN),
.AA(PORT_A_ADDR),
.CLKA(PORT_A_CLK),
.QB(PORT_B_RD_DATA),
.DB(PORT_B_WR_DATA),
.CEB(PORT_B_CLK_EN),
.WEB(PORT_B_WR_EN),
.AB(PORT_B_ADDR),
.CLKB(PORT_B_CLK),
);
// check config
generate
if (PORT_A_WR_EN_WIDTH == PORT_B_WR_EN_WIDTH)
case (BRAM_MODE)
`ifdef IS_T40LP
"SDP_1024x18_FP",
"SDP_1024x16_BP",
"SDP_2048x09",
"SDP_4096x05",
"SDP_1024x32_ECC",
"SDP_1024x40",
"SDP_1024x36_BP",
"SDP_512x32_ECC",
"SDP_512x36_BP",
"SDP_2048x10",
"SP_512x32_ECC",
"SP_512x36_BP",
"SP_1024x20",
"SP2_512x18_BP",
"SP2_1024x09",
"SP2_2048x05": wire _TECHMAP_FAIL_ = 0;
`endif
`ifdef IS_T16FFC
"TDP_2048x18_FP",
"TDP_2048x16_BP",
"TDP_4096x09",
"TDP_8192x05",
"TDP_2048x32_ECC",
"TDP_2048x40",
"TDP_2048x36_BP",
"SDP_2048x18_FP",
"SDP_2048x16_BP",
// The following are rejected in eXpreso
// "SDP_4096x09",
// "SDP_8192x05",
// "SDP_2048x32_ECC",
// "SDP_2048x40",
// "SDP_2048x36_BP",
"SDP_1024x32_ECC",
"SDP_1024x36_BP",
"SDP_4096x10",
"SP_1024x32_ECC",
"SP_1024x36_BP",
"SP_2048x20",
"SP2_1024x18_BP",
"SP2_2048x09",
"SP2_4096x05": wire _TECHMAP_FAIL_ = 0;
`endif
default: wire _TECHMAP_FAIL_ = 1;
endcase
else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
module $__ANALOGDEVICES_BLOCKRAM_HALF_ (...);
// libmap params
parameter INIT = 0;
parameter OPTION_MODE = "NONE";
parameter OPTION_SIZE = "NONE";
parameter OPTION_ERR = "NONE";
parameter PORT_A_WR_EN_WIDTH = 1;
parameter PORT_A_CLK_POL = 1;
parameter PORT_B_WR_EN_WIDTH = PORT_A_WR_EN_WIDTH;
parameter PORT_B_CLK_POL = 1;
// needs -force-params
parameter WIDTH = 40;
parameter ABITS = 13;
// libmap ports
input PORT_A_CLK;
input PORT_A_CLK_EN;
input [ABITS-1:0] PORT_A_ADDR;
input [WIDTH-1:0] PORT_A_WR_DATA;
output [WIDTH-1:0] PORT_A_RD_DATA;
input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
input PORT_B_CLK;
input PORT_B_CLK_EN;
input [ABITS-1:0] PORT_B_ADDR;
input [WIDTH-1:0] PORT_B_WR_DATA;
output [WIDTH-1:0] PORT_B_RD_DATA;
input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
$__ANALOGDEVICES_BLOCKRAM_FULL_
# (
.INIT(INIT),
.OPTION_MODE(OPTION_MODE),
.OPTION_SIZE(OPTION_SIZE),
.OPTION_ERR(OPTION_ERR),
.PORT_A_WR_EN_WIDTH(PORT_A_WR_EN_WIDTH),
.PORT_A_CLK_POL(PORT_A_CLK_POL),
.PORT_B_WR_EN_WIDTH(PORT_B_WR_EN_WIDTH),
.PORT_B_CLK_POL(PORT_B_CLK_POL),
.WIDTH(WIDTH),
.ABITS(ABITS)
)
_TECHMAP_REPLACE_
(
.PORT_A_CLK(PORT_A_CLK),
.PORT_A_CLK_EN(PORT_A_CLK_EN),
.PORT_A_ADDR(PORT_A_ADDR),
.PORT_A_WR_DATA(PORT_A_WR_DATA),
.PORT_A_RD_DATA(PORT_A_RD_DATA),
.PORT_A_WR_EN(PORT_A_WR_EN),
.PORT_B_CLK(PORT_B_CLK),
.PORT_B_CLK_EN(PORT_B_CLK_EN),
.PORT_B_ADDR(PORT_B_ADDR),
.PORT_B_WR_DATA(PORT_B_WR_DATA),
.PORT_B_RD_DATA(PORT_B_RD_DATA),
.PORT_B_WR_EN(PORT_B_WR_EN)
);
endmodule
module $__ANALOGDEVICES_BLOCKRAM_QUARTER_ (...);
// libmap params
parameter INIT = 0;
parameter OPTION_MODE = "NONE";
parameter OPTION_SIZE = "NONE";
parameter OPTION_ERR = "NONE";
parameter PORT_A_WR_EN_WIDTH = 1;
parameter PORT_A_CLK_POL = 1;
parameter PORT_B_WR_EN_WIDTH = PORT_A_WR_EN_WIDTH;
parameter PORT_B_CLK_POL = 1;
// needs -force-params
parameter WIDTH = 40;
parameter ABITS = 13;
// libmap ports
input PORT_A_CLK;
input PORT_A_CLK_EN;
input [ABITS-1:0] PORT_A_ADDR;
input [WIDTH-1:0] PORT_A_WR_DATA;
output [WIDTH-1:0] PORT_A_RD_DATA;
input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
$__ANALOGDEVICES_BLOCKRAM_FULL_
# (
.INIT(INIT),
.OPTION_MODE(OPTION_MODE),
.OPTION_SIZE(OPTION_SIZE),
.OPTION_ERR(OPTION_ERR),
.PORT_A_WR_EN_WIDTH(PORT_A_WR_EN_WIDTH),
.PORT_A_CLK_POL(PORT_A_CLK_POL),
.PORT_B_WR_EN_WIDTH(PORT_B_WR_EN_WIDTH),
.PORT_B_CLK_POL(PORT_B_CLK_POL),
.WIDTH(WIDTH),
.ABITS(ABITS)
)
_TECHMAP_REPLACE_
(
.PORT_A_CLK(PORT_A_CLK),
.PORT_A_CLK_EN(PORT_A_CLK_EN),
.PORT_A_ADDR(PORT_A_ADDR),
.PORT_A_WR_DATA(PORT_A_WR_DATA),
.PORT_A_RD_DATA(PORT_A_RD_DATA),
.PORT_A_WR_EN(PORT_A_WR_EN),
);
endmodule

364
techlibs/analogdevices/cells_map.v Normal file
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@ -0,0 +1,364 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$__SHREG_ (input C, input D, input E, output Q);
parameter DEPTH = 0;
parameter [DEPTH-1:0] INIT = 0;
parameter CLKPOL = 1;
parameter ENPOL = 2;
\$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));
endmodule
module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
parameter DEPTH = 0;
parameter [DEPTH-1:0] INIT = 0;
parameter CLKPOL = 1;
parameter ENPOL = 2;
// shregmap's INIT parameter shifts out LSB first;
// however Analog Devices expects MSB first
function [DEPTH-1:0] brev;
input [DEPTH-1:0] din;
integer i;
begin
for (i = 0; i < DEPTH; i=i+1)
brev[i] = din[DEPTH-1-i];
end
endfunction
localparam [DEPTH-1:0] INIT_R = brev(INIT);
parameter _TECHMAP_CONSTMSK_L_ = 0;
wire CE;
generate
if (ENPOL == 0)
assign CE = ~E;
else if (ENPOL == 1)
assign CE = E;
else
assign CE = 1'b1;
if (DEPTH == 1) begin
if (CLKPOL)
FFRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
else
FFRE_N #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
end else
if (DEPTH <= 16) begin
SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
end else
if (DEPTH > 17 && DEPTH <= 32) begin
SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
end else
if (DEPTH > 33 && DEPTH <= 64) begin
wire T0, T1, T2;
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
if (&_TECHMAP_CONSTMSK_L_)
assign Q = T2;
else
LUTMUX7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
end else
if (DEPTH > 65 && DEPTH <= 96) begin
wire T0, T1, T2, T3, T4, T5, T6;
SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
if (&_TECHMAP_CONSTMSK_L_)
assign Q = T4;
else
\$__ANALOGDEVICES_LUTMUX78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S0(L[5]), .S1(L[6]), .O(Q));
end else
if (DEPTH > 97 && DEPTH < 128) begin
wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
if (&_TECHMAP_CONSTMSK_L_)
assign Q = T6;
else
\$__ANALOGDEVICES_LUTMUX78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
end
else if (DEPTH == 128) begin
wire T0, T1, T2, T3, T4, T5, T6;
SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
if (&_TECHMAP_CONSTMSK_L_)
assign Q = T6;
else
\$__ANALOGDEVICES_LUTMUX78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
end
// For fixed length, if just 1 over a convenient value, decompose
else if (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_) begin
wire T;
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl (.C(C), .D(D), .L({32{1'b1}}), .E(E), .Q(T));
\$__XILINX_SHREG_ #(.DEPTH(1), .INIT(INIT[0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(T), .L(L), .E(E), .Q(Q));
end
// For variable length, if just 1 over a convenient value, then bump up one more
else if (DEPTH < 129 && ~&_TECHMAP_CONSTMSK_L_)
\$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
else begin
localparam depth0 = 128;
localparam num_srl128 = DEPTH / depth0;
localparam depthN = DEPTH % depth0;
wire [num_srl128 + (depthN > 0 ? 1 : 0) - 1:0] T;
wire [num_srl128 + (depthN > 0 ? 1 : 0) :0] S;
assign S[0] = D;
genvar i;
for (i = 0; i < num_srl128; i++)
\$__XILINX_SHREG_ #(.DEPTH(depth0), .INIT(INIT[DEPTH-1-i*depth0-:depth0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl (.C(C), .D(S[i]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[i]), .SO(S[i+1]));
if (depthN > 0)
\$__XILINX_SHREG_ #(.DEPTH(depthN), .INIT(INIT[depthN-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(S[num_srl128]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[num_srl128]));
if (&_TECHMAP_CONSTMSK_L_)
assign Q = T[num_srl128 + (depthN > 0 ? 1 : 0) - 1];
else
assign Q = T[L[DEPTH-1:$clog2(depth0)]];
end
endgenerate
endmodule
`ifdef MIN_MUX_INPUTS
module \$__ANALOGDEVICES_SHIFTX (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
function integer A_WIDTH_trimmed;
input integer start;
begin
A_WIDTH_trimmed = start;
while (A_WIDTH_trimmed > 0 && _TECHMAP_CONSTMSK_A_[A_WIDTH_trimmed-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH_trimmed-1] === 1'bx)
A_WIDTH_trimmed = A_WIDTH_trimmed - 1;
end
endfunction
generate
genvar i, j;
// Bit-blast
if (Y_WIDTH > 1) begin
for (i = 0; i < Y_WIDTH; i++)
\$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
end
// If the LSB of B is constant zero (and Y_WIDTH is 1) then
// we can optimise by removing every other entry from A
// and popping the constant zero from B
else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
wire [(A_WIDTH+1)/2-1:0] A_i;
for (i = 0; i < (A_WIDTH+1)/2; i++)
assign A_i[i] = A[i*2];
\$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
end
// Trim off any leading 1'bx -es in A
else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin
localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1);
if (A_WIDTH_new == 0)
assign Y = 1'bx;
else
\$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y));
end
else if (A_WIDTH < `MIN_MUX_INPUTS) begin
wire _TECHMAP_FAIL_ = 1;
end
else if (A_WIDTH == 2) begin
LUTMUX7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));
end
else if (A_WIDTH <= 4) begin
wire [4-1:0] Ax;
if (A_WIDTH == 4)
assign Ax = A;
else
// Rather than extend with 1'bx which gets flattened to 1'b0
// causing the "don't care" status to get lost, extend with
// the same driver of F7B.I0 so that we can optimise F7B away
// later
assign Ax = {A[1], A};
\$__ANALOGDEVICES_LUTMUX78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y));
end
// Note that the following decompositions are 'backwards' in that
// the LSBs are placed on the hard resources, and the soft resources
// are used for MSBs.
// This has the effect of more effectively utilising the hard mux;
// take for example a 5:1 multiplexer, currently this would map as:
//
// A[0] \___ __ A[0] \__ __
// A[4] / \| \ whereas the more A[1] / \| \
// A[1] _____| | obvious mapping A[2] \___| |
// A[2] _____| |-- of MSBs to hard A[3] / | |__
// A[3]______| | resources would A[4] ____| |
// |__/ lead to: 1'bx ____| |
// || |__/
// || ||
// B[1:0] B[1:2]
//
// Expectation would be that the 'forward' mapping (right) is more
// area efficient (consider a 9:1 multiplexer using 2x4:1 multiplexers
// on its I0 and I1 inputs, and A[8] and 1'bx on its I2 and I3 inputs)
// but that the 'backwards' mapping (left) is more delay efficient
// since smaller LUTs are faster than wider ones.
else if (A_WIDTH <= 8) begin
wire [8-1:0] Ax = {{{8-A_WIDTH}{1'bx}}, A};
wire T0 = B[2] ? Ax[4] : Ax[0];
wire T1 = B[2] ? Ax[5] : Ax[1];
wire T2 = B[2] ? Ax[6] : Ax[2];
wire T3 = B[2] ? Ax[7] : Ax[3];
\$__ANALOGDEVICES_LUTMUX78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));
end
else if (A_WIDTH <= 16) begin
wire [16-1:0] Ax = {{{16-A_WIDTH}{1'bx}}, A};
wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]
: B[3] ? Ax[ 8] : Ax[0];
wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]
: B[3] ? Ax[ 9] : Ax[1];
wire T2 = B[2] ? B[3] ? Ax[14] : Ax[6]
: B[3] ? Ax[10] : Ax[2];
wire T3 = B[2] ? B[3] ? Ax[15] : Ax[7]
: B[3] ? Ax[11] : Ax[3];
\$__ANALOGDEVICES_LUTMUX78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));
end
else begin
localparam num_mux16 = (A_WIDTH+15) / 16;
localparam clog2_num_mux16 = $clog2(num_mux16);
wire [num_mux16-1:0] T;
wire [num_mux16*16-1:0] Ax = {{(num_mux16*16-A_WIDTH){1'bx}}, A};
for (i = 0; i < num_mux16; i++)
\$__ANALOGDEVICES_SHIFTX #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(16),
.B_WIDTH(4),
.Y_WIDTH(Y_WIDTH)
) fpga_mux (
.A(Ax[i*16+:16]),
.B(B[3:0]),
.Y(T[i])
);
\$__ANALOGDEVICES_SHIFTX #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(num_mux16),
.B_WIDTH(clog2_num_mux16),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(T),
.B(B[B_WIDTH-1-:clog2_num_mux16]),
.Y(Y));
end
endgenerate
endmodule
(* techmap_celltype = "$__ANALOGDEVICES_SHIFTX" *)
module _90__ANALOGDEVICES_SHIFTX (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
endmodule
module \$_MUX_ (A, B, S, Y);
input A, B, S;
output Y;
generate
if (`MIN_MUX_INPUTS == 2)
\$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(2), .B_WIDTH(1), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({B,A}), .B(S), .Y(Y));
else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
module \$_MUX4_ (A, B, C, D, S, T, Y);
input A, B, C, D, S, T;
output Y;
\$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({D,C,B,A}), .B({T,S}), .Y(Y));
endmodule
module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
\$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
endmodule
module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
output Y;
\$__ANALOGDEVICES_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
endmodule
`endif
module \$__ANALOGDEVICES_LUTMUX78 (O, I0, I1, I2, I3, S0, S1);
output O;
input I0, I1, I2, I3, S0, S1;
wire T0, T1;
parameter _TECHMAP_BITS_CONNMAP_ = 0;
parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
parameter _TECHMAP_CONSTMSK_S0_ = 0;
parameter _TECHMAP_CONSTVAL_S0_ = 0;
parameter _TECHMAP_CONSTMSK_S1_ = 0;
parameter _TECHMAP_CONSTVAL_S1_ = 0;
if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
assign T0 = I1;
else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
assign T0 = I0;
else
LUTMUX7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
assign T1 = I3;
else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
assign T1 = I2;
else
LUTMUX7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
assign O = T1;
else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
assign O = T0;
else
LUTMUX8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
endmodule

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module \$__MUL22X22 (input [21:0] A, input [21:0] B, output [43:0] Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
wire [47:0] P_48;
RBBDSP #(
// Disable all registers
.AI_SEL_IN(1'b0),
.BC_CI(2'b00),
.BI_SEL(1'b0),
.BI_SEL_IN(1'b0),
.CE_A(1'b0),
.CE_ADD(1'b0),
.CE_B(1'b0),
.CE_C(1'b0),
.CE_CRY(1'b0),
.CE_D(2'b0),
.CE_M(1'b0),
.CE_OPCODE(1'b0),
.CE_PADD(1'b0),
.CE_RST(1'b1),
.CE_SEL(1'b0),
.CE_SFT(1'b0),
.CI_SEL(4'd3),
.DI_SEL(1'b0),
.DI_SEL_IN(1'b0),
.OPCODE_SEL(1'b0),
.OP_ADD(10'b0),
.OP_CPLX(1'b0),
.OP_MULT(2'b11),
.OP_PADD(10'b0000000000),
.OP_SFT(6'b000000),
.OP_X(4'b1010),
.OP_Y(4'b0101),
.OP_Z(4'b0000),
.PO_LOC_SEL(1'b1),
.PO_NWK_SEL(1'b1),
.REG_A(1'b0),
.REG_ADD(1'b0),
.REG_B(1'b0),
.REG_C(1'b0),
.REG_CRY(1'b0),
.REG_D(2'b0),
.REG_M(1'b0),
.REG_OPCODE(1'b0),
.REG_PADD(1'b0),
.REG_SFT(1'b0),
.RST_SEL(1'b0),
.FF_SYNC_RST(1'b0),
) _TECHMAP_REPLACE_ (
.P(P_48),
.A(A),
.B(B),
.D(48'b0)
);
assign Y = P_48;
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`ifndef _NO_FFS
// Async reset, enable.
module \$_DFFE_NP0P_ (input D, C, E, R, output Q);
FFCE_N #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
FFCE #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFFE_NP1P_ (input D, C, E, R, output Q);
FFPE_N #(.INIT(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFFE_PP1P_ (input D, C, E, R, output Q);
FFPE #(.INIT(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// Sync reset, enable.
module \$_SDFFE_NP0P_ (input D, C, E, R, output Q);
FFRE_N #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_SDFFE_PP0P_ (input D, C, E, R, output Q);
FFRE #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_SDFFE_NP1P_ (input D, C, E, R, output Q);
FFSE_N #(.INIT(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
FFSE #(.INIT(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
`endif

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// ============================================================================
// LUT mapping
`ifndef _NO_LUTS
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]));
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]));
end else
if (WIDTH == 3) begin
LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]));
end else
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]));
end else
if (WIDTH == 5) begin
LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]));
end else
if (WIDTH == 6) begin
LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
end else
if (WIDTH == 7) begin
wire f0, f1;
\$lut #(.LUT(LUT[ 63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
LUTMUX7 mux7(.I0(f0), .I1(f1), .S(A[6]), .O(Y));
end else
if (WIDTH == 8) begin
wire f0, f1;
\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
LUTMUX8 mux8 (.I0(f0), .I1(f1), .S(A[7]), .O(Y));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
`endif

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ram distributed $__ANALOGDEVICES_LUTRAM_ {
option "SIZE" 32 abits 5;
option "SIZE" 64 abits 6;
width 1;
init no_undef;
prune_rom;
port arsw "RW" {
clock posedge;
}
option "MODE" "SP" {
option "SIZE" 32 cost 2;
option "SIZE" 64 cost 2;
}
option "MODE" "DP" {
option "SIZE" 32 cost 4;
option "SIZE" 64 cost 8;
port ar "R" {
}
}
}

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module $__ANALOGDEVICES_LUTRAM_ (...);
parameter INIT = 0;
parameter OPTION_SIZE = 32;
parameter OPTION_MODE = "SP";
parameter ABITS = 5;
parameter WIDTH = 1;
output PORT_RW_RD_DATA;
input PORT_RW_WR_DATA;
input [ABITS-1:0] PORT_RW_ADDR;
input PORT_RW_WR_EN;
input PORT_RW_CLK;
output PORT_R_RD_DATA;
input [ABITS-1:0] PORT_R_ADDR;
generate
if (OPTION_MODE=="SP")
case(OPTION_SIZE)
32:
RAMS32X1
#(
.INIT(INIT)
)
_TECHMAP_REPLACE_
(
.O(PORT_RW_RD_DATA),
.A0(PORT_RW_ADDR[0]),
.A1(PORT_RW_ADDR[1]),
.A2(PORT_RW_ADDR[2]),
.A3(PORT_RW_ADDR[3]),
.A4(PORT_RW_ADDR[4]),
.D(PORT_RW_WR_DATA),
.WCLK(PORT_RW_CLK),
.WE(PORT_RW_WR_EN)
);
64:
RAMS64X1
#(
.INIT(INIT)
)
_TECHMAP_REPLACE_
(
.O(PORT_RW_RD_DATA),
.A0(PORT_RW_ADDR[0]),
.A1(PORT_RW_ADDR[1]),
.A2(PORT_RW_ADDR[2]),
.A3(PORT_RW_ADDR[3]),
.A4(PORT_RW_ADDR[4]),
.A5(PORT_RW_ADDR[5]),
.D(PORT_RW_WR_DATA),
.WCLK(PORT_RW_CLK),
.WE(PORT_RW_WR_EN)
);
default:
$error("invalid SIZE/MODE combination");
endcase
else if (OPTION_MODE=="DP")
case (OPTION_SIZE)
32:
RAMD32X1
#(
.INIT(INIT)
)
_TECHMAP_REPLACE_
(
.DPO(PORT_R_RD_DATA),
.SPO(PORT_RW_RD_DATA),
.A0(PORT_RW_ADDR[0]),
.A1(PORT_RW_ADDR[1]),
.A2(PORT_RW_ADDR[2]),
.A3(PORT_RW_ADDR[3]),
.A4(PORT_RW_ADDR[4]),
.D(PORT_RW_WR_DATA),
.DPRA0(PORT_R_ADDR[0]),
.DPRA1(PORT_R_ADDR[1]),
.DPRA2(PORT_R_ADDR[2]),
.DPRA3(PORT_R_ADDR[3]),
.DPRA4(PORT_R_ADDR[4]),
.WCLK(PORT_RW_CLK),
.WE(PORT_RW_WR_EN)
);
64:
RAMD64X1
#(
.INIT(INIT)
)
_TECHMAP_REPLACE_
(
.DPO(PORT_R_RD_DATA),
.SPO(PORT_RW_RD_DATA),
.A0(PORT_RW_ADDR[0]),
.A1(PORT_RW_ADDR[1]),
.A2(PORT_RW_ADDR[2]),
.A3(PORT_RW_ADDR[3]),
.A4(PORT_RW_ADDR[4]),
.A5(PORT_RW_ADDR[5]),
.D(PORT_RW_WR_DATA),
.DPRA0(PORT_R_ADDR[0]),
.DPRA1(PORT_R_ADDR[1]),
.DPRA2(PORT_R_ADDR[2]),
.DPRA3(PORT_R_ADDR[3]),
.DPRA4(PORT_R_ADDR[4]),
.DPRA5(PORT_R_ADDR[5]),
.WCLK(PORT_RW_CLK),
.WE(PORT_RW_WR_EN)
);
default:
$error("invalid SIZE/MODE combination");
endcase
else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
module $__ANALOGDEVICES_LUTRAM_DP_ (...);
parameter INIT = 0;
parameter OPTION_SIZE = 32;
parameter ABITS = 5;
parameter WIDTH = 1;
output PORT_RW_RD_DATA;
input PORT_RW_WR_DATA;
input [ABITS-1:0] PORT_RW_ADDR;
input PORT_RW_WR_EN;
input PORT_RW_CLK;
output PORT_R_RD_DATA;
input [ABITS-1:0] PORT_R_ADDR;
generate
endgenerate
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// The purpose of these mapping rules is to allow preserve all (sufficiently
// wide) $shiftx cells during 'techmap' so that they can be mapped to hard
// resources, rather than being bit-blasted to gates during 'techmap'
// execution
module \$shiftx (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
generate
if (B_SIGNED) begin
if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && (_TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0 || _TECHMAP_CONSTVAL_B_[B_WIDTH-1] === 1'bx))
// Optimisation to remove B_SIGNED if sign bit of B is constant-0
\$shiftx #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(0),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH-1'd1),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)
);
else
wire _TECHMAP_FAIL_ = 1;
end
else begin
if (((A_WIDTH + Y_WIDTH - 1) / Y_WIDTH) < `MIN_MUX_INPUTS)
wire _TECHMAP_FAIL_ = 1;
else
\$__ANALOGDEVICES_SHIFTX #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(A), .B(B), .Y(Y)
);
end
endgenerate
endmodule

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module FF (input C, D, output Q);
parameter INIT = 1'b0;
if (INIT === 1'b1) begin
FFPE _TECHMAP_REPLACE_ (.C(C), .D(D), .PRE(1'b0), .CE(1'b1), .Q(Q));
end else begin
FFCE _TECHMAP_REPLACE_ (.C(C), .D(D), .CLR(1'b0), .CE(1'b1), .Q(Q));
end
endmodule
module FF_N (input C, D, output Q);
parameter INIT = 1'b0;
if (INIT === 1'b1) begin
FFPE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .PRE(1'b0), .CE(1'b1), .Q(Q));
end else begin
FFCE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .CLR(1'b0), .CE(1'b1), .Q(Q));
end
endmodule
module FFC (input C, D, CLR, output Q);
FFCE _TECHMAP_REPLACE_ (.C(C), .D(D), .CLR(CLR), .CE(1'b1), .Q(Q));
endmodule
module FFC_N (input C, D, CLR, output Q);
FFCE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .CLR(CLR), .CE(1'b1), .Q(Q));
endmodule
module FFP (input C, D, PRE, output Q);
FFPE _TECHMAP_REPLACE_ (.C(C), .D(D), .PRE(PRE), .CE(1'b1), .Q(Q));
endmodule
module FFP_N (input C, D, CLR, output Q);
FFPE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .PRE(PRE), .CE(1'b1), .Q(Q));
endmodule
module FFR (input C, D, R, output Q);
FFRE _TECHMAP_REPLACE_ (.C(C), .D(D), .R(R), .CE(1'b1), .Q(Q));
endmodule
module FFR_N (input C, D, R, output Q);
FFRE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .R(R), .CE(1'b1), .Q(Q));
endmodule
module FFS (input C, D, S, output Q);
FFSE _TECHMAP_REPLACE_ (.C(C), .D(D), .S(S), .CE(1'b1), .Q(Q));
endmodule
module FFS_N (input C, D, S, output Q);
FFSE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .S(S), .CE(1'b1), .Q(Q));
endmodule

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* (C) 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SynthAnalogDevicesPass : public ScriptPass
{
SynthAnalogDevicesPass() : ScriptPass("synth_analogdevices", "synthesis for Analog Devices FPGAs") { }
void on_register() override
{
RTLIL::constpad["synth_analogdevices.abc9.W"] = "300"; // Number with which ABC will map a 6-input gate
// to one LUT6 (instead of a LUT5 + LUT2)
}
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" synth_analogdevices [options]\n");
log("\n");
log("This command runs synthesis for Analog Devices FPGAs. This command does not operate on\n");
log("partly selected designs.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module\n");
log("\n");
log(" -tech <tech>\n");
log(" run synthesis for the specified ADI technology process\n");
log(" currently only affects the type of BRAM used.\n");
log(" supported values:\n");
log(" - t40lp (RBRAM)\n");
log(" - t16ffc (RBRAM2, default)\n");
log("\n");
log(" -edif <file>\n");
log(" write the design to the specified edif file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -nobram\n");
log(" do not use block RAM cells in output netlist\n");
log("\n");
log(" -nolutram\n");
log(" do not use distributed RAM cells in output netlist\n");
log("\n");
log(" -nosrl\n");
log(" do not use distributed SRL cells in output netlist\n");
log("\n");
log(" -nocarry\n");
log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
log("\n");
log(" -nowidelut\n");
log(" do not use MUXF[7-8] resources to implement LUTs larger than native for\n");
log(" the target\n");
log("\n");
log(" -nodsp\n");
log(" do not use DSP48*s to implement multipliers and associated logic\n");
log("\n");
log(" -noiopad\n");
log(" disable I/O buffer insertion (useful for hierarchical or \n");
log(" out-of-context flows)\n");
log("\n");
log(" -noclkbuf\n");
log(" disable automatic clock buffer insertion\n");
log("\n");
log(" -widemux <int>\n");
log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at\n");
log(" or above this number of inputs (minimum value 2, recommended value >= 5)\n");
log(" default: 0 (no inference)\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis\n");
log("\n");
log(" -dff\n");
log(" run 'abc'/'abc9' with -dff option\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with '-D 1' option to enable flip-flop retiming.\n");
log(" implies -dff.\n");
log("\n");
log(" -noabc9\n");
log(" disable use of new ABC9 flow\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
log("\n");
}
std::string top_opt, edif_file, json_file, tech, tech_param;
bool flatten, retime, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp;
bool abc9, dff;
bool flatten_before_abc;
int widemux;
int widelut_size;
void clear_flags() override
{
top_opt = "-auto-top";
edif_file.clear();
tech = "t16ffc";
tech_param = " -D IS_T16FFC";
flatten = true;
retime = false;
noiopad = false;
noclkbuf = false;
nocarry = false;
nobram = false;
nolutram = false;
nosrl = false;
nocarry = false;
nowidelut = false;
nodsp = false;
abc9 = true;
dff = false;
flatten_before_abc = false;
widemux = 0;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string run_from, run_to;
clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-top" && argidx+1 < args.size()) {
top_opt = "-top " + args[++argidx];
continue;
}
if (args[argidx] == "-tech" && argidx+1 < args.size()) {
tech = args[++argidx];
if (tech == "t16ffc")
tech_param = " -D IS_T16FFC";
else if (tech == "t40lp")
tech_param = " -D IS_T40LP";
continue;
}
if (args[argidx] == "-edif" && argidx+1 < args.size()) {
edif_file = args[++argidx];
continue;
}
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos)
break;
run_from = args[++argidx].substr(0, pos);
run_to = args[argidx].substr(pos+1);
continue;
}
if (args[argidx] == "-noflatten") {
flatten = false;
continue;
}
if (args[argidx] == "-flatten_before_abc") {
flatten_before_abc = true;
continue;
}
if (args[argidx] == "-retime") {
dff = true;
retime = true;
continue;
}
if (args[argidx] == "-nocarry") {
nocarry = true;
continue;
}
if (args[argidx] == "-nowidelut") {
nowidelut = true;
continue;
}
if (args[argidx] == "-iopad") {
continue;
}
if (args[argidx] == "-noiopad") {
noiopad = true;
continue;
}
if (args[argidx] == "-noclkbuf") {
noclkbuf = true;
continue;
}
if (args[argidx] == "-nocarry") {
nocarry = true;
continue;
}
if (args[argidx] == "-nobram") {
nobram = true;
continue;
}
if (args[argidx] == "-nolutram") {
nolutram = true;
continue;
}
if (args[argidx] == "-nosrl") {
nosrl = true;
continue;
}
if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
widemux = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-noabc9") {
abc9 = false;
continue;
}
if (args[argidx] == "-nodsp") {
nodsp = true;
continue;
}
if (args[argidx] == "-dff") {
dff = true;
continue;
}
if (args[argidx] == "-json" && argidx+1 < args.size()) {
json_file = args[++argidx];
continue;
}
break;
}
extra_args(args, argidx, design);
if (!(tech == "t16ffc" || tech == "t40lp"))
log_cmd_error("Invalid ADI -tech setting: '%s'.\n", tech);
if (widemux != 0 && widemux < 2)
log_cmd_error("-widemux value must be 0 or >= 2.\n");
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
if (abc9 && retime)
log_cmd_error("-retime option not currently compatible with -abc9!\n");
log_header(design, "Executing SYNTH_ANALOGDEVICES pass.\n");
log_push();
run_script(design, run_from, run_to);
log_pop();
}
void script() override
{
if (check_label("begin")) {
run(stringf("read_verilog -lib -specify %s +/analogdevices/cells_sim.v", tech_param));
run(stringf("hierarchy -check %s", top_opt.c_str()));
}
if (check_label("prepare")) {
run("proc");
if (flatten || help_mode) {
run("check");
run("flatten", "(with '-flatten')");
}
if (active_design)
active_design->scratchpad_unset("tribuf.added_something");
run("tribuf -logic");
if (noiopad && active_design && active_design->scratchpad_get_bool("tribuf.added_something"))
log_error("Tristate buffers are unsupported without the '-iopad' option.\n");
run("deminout");
run("opt_expr");
run("opt_clean");
run("check");
run("opt -nodffe -nosdff");
run("fsm");
run("opt");
if (help_mode)
run("wreduce [-keepdc]", "(option for '-widemux')");
else
run("wreduce" + std::string(widemux > 0 ? " -keepdc" : ""));
run("peepopt");
run("opt_clean");
if (widemux > 0 || help_mode)
run("muxpack", " ('-widemux' only)");
// xilinx_srl looks for $shiftx cells for identifying variable-length
// shift registers, so attempt to convert $pmux-es to this
// Also: wide multiplexer inference benefits from this too
if (!(nosrl && widemux == 0) || help_mode) {
run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
run("clean", " (skip if '-nosrl' and '-widemux=0')");
}
}
if (check_label("map_dsp", "(skip if '-nodsp')")) {
if (!nodsp || help_mode) {
run("memory_dff"); // xilinx_dsp will merge registers, reserve memory port registers first
// NB: Analog Devices multipliers are signed only
if (help_mode)
run("techmap -map +/mul2dsp.v -map +/analogdevices/{family}_dsp_map.v {options}");
run("techmap -map +/mul2dsp.v -map +/analogdevices/dsp_map.v -D DSP_A_MAXWIDTH=22 -D DSP_B_MAXWIDTH=22 "
"-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally
// limited to 18x18 in order to take
// advantage of the (PCOUT << 17) -> PCIN
// dedicated cascade chain capability
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL22X22");
run("select a:mul2dsp");
run("setattr -unset mul2dsp");
run("opt_expr -fine");
run("wreduce");
run("select -clear");
if (help_mode)
run("xilinx_dsp -family <family>");
else
run("xilinx_dsp -family xc7");
run("chtype -set $mul t:$__soft_mul");
}
}
if (check_label("coarse")) {
run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=6");
run("alumacc");
run("share");
run("opt");
run("memory -nomap");
run("opt_clean");
}
if (check_label("map_memory")) {
std::string params = "";
std::string lutrams_map = "+/analogdevices/lutrams_map.v";
std::string brams_map = "+/analogdevices/brams_map.v";
if (help_mode) {
params = " [...]";
} else {
params += " -logic-cost-rom 0.015625";
params += " -force-params";
params += " -lib +/analogdevices/lutrams.txt";
params += " -lib +/analogdevices/brams.txt";
params += tech_param;
brams_map += tech_param;
if (nolutram)
params += " -no-auto-distributed";
if (nobram)
params += " -no-auto-block";
}
run("memory_libmap" + params);
run("techmap -map " + lutrams_map);
run("techmap -map " + brams_map);
}
if (check_label("map_ffram")) {
if (widemux > 0) {
run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
// performs less efficiently
} else {
run("opt -fast -full");
}
run("memory_map");
}
if (check_label("fine")) {
if (help_mode) {
run("simplemap t:$mux", "('-widemux' only)");
run("muxcover <internal options>", "('-widemux' only)");
} else if (widemux > 0) {
run("simplemap t:$mux");
constexpr int cost_mux2 = 100;
std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
switch (widemux) {
case 2: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2+1, cost_mux2+2, cost_mux2+3); break;
case 3:
case 4: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-2, cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
case 5:
case 6:
case 7:
case 8: muxcover_args += stringf(" -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
case 9:
case 10:
case 11:
case 12:
case 13:
case 14:
case 15:
default: muxcover_args += stringf(" -mux16=%d", cost_mux2*(widemux-1)-1); break;
}
run("muxcover " + muxcover_args);
}
run("opt -full");
if (!nosrl || help_mode)
run("xilinx_srl -variable -minlen 3", "(skip if '-nosrl')");
std::string techmap_args = " -map +/techmap.v -D LUT_SIZE=6";
if (help_mode)
techmap_args += " [-map +/analogdevices/mux_map.v]";
else if (widemux > 0)
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/analogdevices/mux_map.v", widemux);
if (!nocarry) {
techmap_args += " -map +/analogdevices/arith_map.v";
}
run("techmap " + techmap_args);
run("opt -fast");
}
if (check_label("map_cells")) {
// Needs to be done before logic optimization, so that inverters (inserted
// here because of negative-polarity output enable) are handled.
if (help_mode || !noiopad)
run("iopadmap -bits -outpad OUTBUF I:O -inpad INBUF O:I A:top", "(skip if '-noiopad')");
std::string techmap_args = "-map +/techmap.v -map +/analogdevices/cells_map.v";
if (widemux > 0)
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
run("techmap " + techmap_args);
run("clean");
}
if (check_label("map_ffs")) {
run("dfflegalize -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r");
if (abc9 || help_mode) {
if (dff || help_mode)
run("zinit -all w:* t:$_SDFFE_*", "('-dff' only)");
run("techmap -map +/analogdevices/ff_map.v", "('-abc9' only)");
}
}
if (check_label("map_luts")) {
run("opt_expr -mux_undef -noclkinv");
if (flatten_before_abc) {
run("check");
run("flatten");
}
if (help_mode)
run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
else if (abc9) {
run("read_verilog -icells -lib -specify +/analogdevices/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_analogdevices.abc9.W";
if (active_design && active_design->scratchpad.count(k))
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
else {
abc9_opts += stringf(" -W %s", RTLIL::constpad.at("synth_analogdevices.abc9.W").c_str());
}
if (nowidelut)
abc9_opts += stringf(" -maxlut 6");
if (dff)
abc9_opts += " -dff";
run("abc9" + abc9_opts);
}
else {
std::string abc_opts;
if (nowidelut)
abc_opts += " -luts 2:2,3,6:5";
else
abc_opts += " -luts 2:2,3,6:5,10,20";
if (dff)
abc_opts += " -dff";
if (retime)
abc_opts += " -D 1";
run("abc -dress" + abc_opts);
}
run("clean");
if (help_mode || !abc9)
run("techmap -map +/analogdevices/ff_map.v", "(only if not '-abc9')");
// This shregmap call infers fixed length shift registers after abc
// has performed any necessary retiming
if (!nosrl || help_mode)
run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
std::string techmap_args = "-map +/analogdevices/lut_map.v -map +/analogdevices/cells_map.v";
techmap_args += " -D LUT_WIDTH=6";
run("techmap " + techmap_args);
run("xilinx_dffopt");
run("opt_lut_ins -tech analogdevices");
}
if (check_label("finalize")) {
run("clean");
}
if (check_label("check")) {
run("hierarchy -check");
run("stat -tech analogdevices");
run("check -noinit");
run("blackbox =A:whitebox");
}
if (check_label("edif")) {
if (!edif_file.empty() || help_mode) {
run("delete t:$assert t:$scopeinfo");
run(stringf("write_edif %s", edif_file.c_str()));
}
}
}
} SynthAnalogDevicesPass;
PRIVATE_NAMESPACE_END

45
techlibs/anlogic/CMakeLists.txt Normal file
View file

@ -0,0 +1,45 @@
yosys_pass(anlogic_eqn
anlogic_eqn.cc
)
yosys_pass(anlogic_fixcarry
anlogic_fixcarry.cc
)
yosys_pass(synth_anlogic
synth_anlogic.cc
REQUIRES
abc
anlogic_eqn
anlogic_fixcarry
blackbox
check
clean
deminout
dfflegalize
flatten
hierarchy
memory_libmap
memory_map
opt
opt_expr
proc
read_verilog
simplemap
stat
synth
techmap
tribuf
write_edif
write_json
DATA_DIR
anlogic
DATA_FILES
cells_map.v
arith_map.v
cells_sim.v
eagle_bb.v
lutrams.txt
lutrams_map.v
brams.txt
brams_map.v
)

13
techlibs/anlogic/Makefile.inc
View file

@ -1,13 +0,0 @@
OBJS += techlibs/anlogic/synth_anlogic.o
OBJS += techlibs/anlogic/anlogic_eqn.o
OBJS += techlibs/anlogic/anlogic_fixcarry.o
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams.txt))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams_map.v))

4
techlibs/anlogic/anlogic_fixcarry.cc
View file

@ -69,7 +69,7 @@ static void fix_carry_chain(Module *module)
continue;
adders_to_fix_cells.push_back(cell);
log("Found %s cell named %s with invalid 'c' signal.\n", log_id(cell->type), log_id(cell));
log("Found %s cell named %s with invalid 'c' signal.\n", cell->type.unescape(), cell);
}
}
@ -78,7 +78,7 @@ static void fix_carry_chain(Module *module)
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescape(), cell);
Cell *c = module->addCell(NEW_ID, ID(AL_MAP_ADDER));
SigBit new_bit = module->addWire(NEW_ID);
SigBit dummy_bit = module->addWire(NEW_ID);

1
techlibs/anlogic/synth_anlogic.cc
View file

@ -156,6 +156,7 @@ struct SynthAnlogicPass : public ScriptPass
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc");
run("check");
run("flatten");
run("tribuf -logic");
run("deminout");

2
techlibs/common/.gitignore vendored
View file

@ -1,2 +0,0 @@
simlib_help.inc
simcells_help.inc

87
techlibs/common/CMakeLists.txt Normal file
View file

@ -0,0 +1,87 @@
if (YOSYS_ENABLE_ABC)
set(abc_requires abc abc9)
endif()
yosys_pass(synth
synth.cc
DEFINITIONS
$<$<BOOL:${YOSYS_ENABLE_ABC}>:YOSYS_ENABLE_ABC>
REQUIRES
${abc_requires}
alumacc
arith_tree
booth
check
clean
flatten
flowmap
fsm
hierarchy
memory
memory_map
opt
opt_clean
opt_expr
peepopt
proc
share
stat
techmap
wreduce
DATA_FILES
simlib.v
simcells.v
techmap.v
smtmap.v
pmux2mux.v
adff2dff.v
dff2ff.v
gate2lut.v
cmp2lut.v
mul2dsp.v
abc9_model.v
abc9_map.v
abc9_unmap.v
cmp2lcu.v
cmp2softlogic.v
choices/kogge-stone.v
choices/han-carlson.v
choices/sklansky.v
)
yosys_pass(prep
prep.cc
REQUIRES
check
flatten
future
hierarchy
memory_collect
memory_dff
memory_memx
opt
opt_clean
opt_expr
proc
sort
stat
wreduce
)
yosys_pass(opensta
opensta.cc
)
yosys_pass(sdc_expand
sdc_expand.cc
REQUIRES
chtype
design
hierarchy
icell_liberty
memory
opensta
proc
read_verilog
write_verilog
)

41
techlibs/common/Makefile.inc
View file

@ -1,41 +0,0 @@
ifneq ($(SMALL),1)
OBJS += techlibs/common/synth.o
OBJS += techlibs/common/prep.o
OBJS += techlibs/common/opensta.o
OBJS += techlibs/common/sdc_expand.o
endif
GENFILES += techlibs/common/simlib_help.inc
GENFILES += techlibs/common/simcells_help.inc
techlibs/common/simlib_help.inc: techlibs/common/cellhelp.py techlibs/common/simlib.v
$(Q) mkdir -p techlibs/common
$(P) $(PYTHON_EXECUTABLE) $^ > $@.new
$(Q) mv $@.new $@
techlibs/common/simcells_help.inc: techlibs/common/cellhelp.py techlibs/common/simcells.v
$(Q) mkdir -p techlibs/common
$(P) $(PYTHON_EXECUTABLE) $^ > $@.new
$(Q) mv $@.new $@
kernel/register.o: techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc
$(eval $(call add_share_file,share,techlibs/common/simlib.v))
$(eval $(call add_share_file,share,techlibs/common/simcells.v))
$(eval $(call add_share_file,share,techlibs/common/techmap.v))
$(eval $(call add_share_file,share,techlibs/common/smtmap.v))
$(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
$(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
$(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
$(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
$(eval $(call add_share_file,share,techlibs/common/abc9_model.v))
$(eval $(call add_share_file,share,techlibs/common/abc9_map.v))
$(eval $(call add_share_file,share,techlibs/common/abc9_unmap.v))
$(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v))
$(eval $(call add_share_file,share,techlibs/common/cmp2softlogic.v))
$(eval $(call add_share_file,share/choices,techlibs/common/choices/kogge-stone.v))
$(eval $(call add_share_file,share/choices,techlibs/common/choices/han-carlson.v))
$(eval $(call add_share_file,share/choices,techlibs/common/choices/sklansky.v))

100
techlibs/common/cellhelp.py
View file

@ -1,100 +0,0 @@
#!/usr/bin/env python3
from __future__ import annotations
import fileinput
import json
from pathlib import Path
class SimHelper:
name: str = ""
title: str = ""
ports: str = ""
source: str = ""
desc: list[str]
code: list[str]
group: str = ""
ver: str = "1"
tags: list[str]
def __init__(self) -> None:
self.desc = []
self.tags = []
def __str__(self) -> str:
printed_fields = [
"name", "title", "ports", "source", "desc", "code", "group", "ver",
"tags",
]
# generate C++ struct
val = f"cell_help[{json.dumps(self.name)}] = "
val += "{\n"
for field in printed_fields:
field_val = getattr(self, field)
if isinstance(field_val, list):
field_val = "\n".join(field_val)
field_val = field_val.strip()
val += f' {json.dumps(field_val)},\n'
val += "};\n"
return val
def simcells_reparse(cell: SimHelper):
# cut manual signature
cell.desc = cell.desc[3:]
# code-block truth table
new_desc = []
indent = ""
for line in cell.desc:
if line.startswith("Truth table:"):
indent = " "
new_desc.pop()
new_desc.extend(["::", ""])
new_desc.append(indent + line)
cell.desc = new_desc
# set version
cell.ver = "2a"
simHelper = SimHelper()
for line in fileinput.input():
line = line.rstrip()
# special comments
if line.startswith("//-"):
simHelper.desc.append(line[4:] if len(line) > 4 else "")
elif line.startswith("//* "):
_, key, val = line.split(maxsplit=2)
setattr(simHelper, key, val)
# code parsing
if line.startswith("module "):
clean_line = line[7:].replace("\\", "").replace(";", "")
simHelper.name, simHelper.ports = clean_line.split(maxsplit=1)
simHelper.code = []
short_filename = Path(fileinput.filename()).name
simHelper.source = f'{short_filename}:{fileinput.filelineno()}'
elif not line.startswith("endmodule"):
line = " " + line
try:
simHelper.code.append(line.replace("\t", " "))
except AttributeError:
# no module definition, ignore line
pass
if line.startswith("endmodule"):
short_filename = Path(fileinput.filename()).name
if simHelper.ver == "1" and short_filename == "simcells.v":
# default simcells parsing
simcells_reparse(simHelper)
# check help
if simHelper.desc and simHelper.ver == "1" and short_filename == "simlib.v" and simHelper.desc[1].startswith(' '):
simHelper.desc.pop(1)
# check group
assert simHelper.group, f"techlibs/common/{simHelper.source}: {simHelper.name} cell missing group"
# dump
print(simHelper)
# new
simHelper = SimHelper()

4
techlibs/common/opensta.cc
View file

@ -5,7 +5,7 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
#if !defined(YOSYS_DISABLE_SPAWN)
#if defined(YOSYS_ENABLE_SPAWN)
struct OpenstaPass : public Pass
{
OpenstaPass() : Pass("opensta", "run OpenSTA") { }
@ -98,7 +98,7 @@ struct OpenstaPass : public Pass
f_script << "read_verilog " << verilog_filename << "\n";
f_script << "read_lib " << liberty_filename << "\n";
f_script << "link_design " << RTLIL::unescape_id(top_mod->name) << "\n";
f_script << "link_design " << top_mod->name.unescape() << "\n";
f_script << "read_sdc " << sdc_filename << "\n";
f_script << "write_sdc " << sdc_expanded_filename << "\n";
f_script.close();

24
techlibs/common/simcells.v
View file

@ -1613,6 +1613,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 0 0 - | x
//- - - 0 - | 0
//- - 0 - - | 1
//- \ - - d | d
@ -1641,6 +1642,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 0 1 - | x
//- - - 1 - | 0
//- - 0 - - | 1
//- \ - - d | d
@ -1669,6 +1671,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 1 0 - | x
//- - - 0 - | 0
//- - 1 - - | 1
//- \ - - d | d
@ -1697,6 +1700,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 1 1 - | x
//- - - 1 - | 0
//- - 1 - - | 1
//- \ - - d | d
@ -1725,6 +1729,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 0 0 - | x
//- - - 0 - | 0
//- - 0 - - | 1
//- / - - d | d
@ -1753,6 +1758,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 0 1 - | x
//- - - 1 - | 0
//- - 0 - - | 1
//- / - - d | d
@ -1781,6 +1787,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 1 0 - | x
//- - - 0 - | 0
//- - 1 - - | 1
//- / - - d | d
@ -1809,6 +1816,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 1 1 - | x
//- - - 1 - | 0
//- - 1 - - | 1
//- / - - d | d
@ -1837,6 +1845,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 0 - - | x
//- - - 0 - - | 0
//- - 0 - - - | 1
//- \ - - 0 d | d
@ -1865,6 +1874,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 0 - - | x
//- - - 0 - - | 0
//- - 0 - - - | 1
//- \ - - 1 d | d
@ -1893,6 +1903,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 1 - - | x
//- - - 1 - - | 0
//- - 0 - - - | 1
//- \ - - 0 d | d
@ -1921,6 +1932,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 1 - - | x
//- - - 1 - - | 0
//- - 0 - - - | 1
//- \ - - 1 d | d
@ -1949,6 +1961,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 0 - - | x
//- - - 0 - - | 0
//- - 1 - - - | 1
//- \ - - 0 d | d
@ -1977,6 +1990,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 0 - - | x
//- - - 0 - - | 0
//- - 1 - - - | 1
//- \ - - 1 d | d
@ -2005,6 +2019,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 1 - - | x
//- - - 1 - - | 0
//- - 1 - - - | 1
//- \ - - 0 d | d
@ -2033,6 +2048,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 1 - - | x
//- - - 1 - - | 0
//- - 1 - - - | 1
//- \ - - 1 d | d
@ -2061,6 +2077,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 0 - - | x
//- - - 0 - - | 0
//- - 0 - - - | 1
//- / - - 0 d | d
@ -2089,6 +2106,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 0 - - | x
//- - - 0 - - | 0
//- - 0 - - - | 1
//- / - - 1 d | d
@ -2117,6 +2135,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 1 - - | x
//- - - 1 - - | 0
//- - 0 - - - | 1
//- / - - 0 d | d
@ -2145,6 +2164,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 1 - - | x
//- - - 1 - - | 0
//- - 0 - - - | 1
//- / - - 1 d | d
@ -2173,6 +2193,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 0 - - | x
//- - - 0 - - | 0
//- - 1 - - - | 1
//- / - - 0 d | d
@ -2201,6 +2222,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 0 - - | x
//- - - 0 - - | 0
//- - 1 - - - | 1
//- / - - 1 d | d
@ -2229,6 +2251,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 1 - - | x
//- - - 1 - - | 0
//- - 1 - - - | 1
//- / - - 0 d | d
@ -2257,6 +2280,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 1 - - | x
//- - - 1 - - | 0
//- - 1 - - - | 1
//- / - - 1 d | d

4
techlibs/common/simlib.v
View file

@ -1976,7 +1976,7 @@ endmodule
// --------------------------------------------------------
//* group spec
module \$specrule (EN_SRC, EN_DST, SRC, DST);
module \$specrule (SRC_EN, DST_EN, SRC, DST);
parameter TYPE = "";
parameter T_LIMIT = 0;
@ -1991,7 +1991,7 @@ parameter SRC_POL = 0;
parameter DST_PEN = 0;
parameter DST_POL = 0;
input EN_SRC, EN_DST;
input SRC_EN, DST_EN;
input [SRC_WIDTH-1:0] SRC;
input [DST_WIDTH-1:0] DST;

28
techlibs/common/synth.cc
View file

@ -67,6 +67,10 @@ struct SynthPass : public ScriptPass {
log(" -booth\n");
log(" run the booth pass to map $mul to Booth encoded multipliers\n");
log("\n");
log(" -arith_tree\n");
log(" run the arith_tree pass to convert $add/$sub chains and $macc cells to\n");
log(" carry-save adder trees.\n");
log("\n");
log(" -noalumacc\n");
log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n");
log(" their direct form ($add, $sub, etc.).\n");
@ -108,7 +112,7 @@ struct SynthPass : public ScriptPass {
}
string top_module, fsm_opts, memory_opts, abc;
bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, hieropt, relative_share;
bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, arith_tree, hieropt, relative_share;
int lut;
std::vector<std::string> techmap_maps;
@ -127,6 +131,7 @@ struct SynthPass : public ScriptPass {
noshare = false;
flowmap = false;
booth = false;
arith_tree = false;
hieropt = false;
relative_share = false;
abc = "abc";
@ -187,7 +192,10 @@ struct SynthPass : public ScriptPass {
booth = true;
continue;
}
if (args[argidx] == "-arith_tree") {
arith_tree = true;
continue;
}
if (args[argidx] == "-nordff") {
memory_opts += " -nordff";
continue;
@ -269,8 +277,10 @@ struct SynthPass : public ScriptPass {
if (check_label("coarse")) {
run("proc");
if (flatten || help_mode)
if (flatten || help_mode) {
run("check");
run("flatten", " (if -flatten)");
}
run("opt_expr");
run("opt_clean");
run("check");
@ -289,6 +299,8 @@ struct SynthPass : public ScriptPass {
run("booth", " (if -booth)");
if (!noalumacc)
run("alumacc", " (unless -noalumacc)");
if (arith_tree || help_mode)
run("arith_tree", " (if -arith_tree)");
if (!noshare)
run("share", " (unless -noshare)");
run("opt" + hieropt_flag);
@ -301,7 +313,7 @@ struct SynthPass : public ScriptPass {
run("memory_map");
run("opt -full");
if (help_mode) {
run(techmap_cmd, " (unless -extra-map)");
run(techmap_cmd, " (unless -extra-map)");
run(techmap_cmd + " -map +/techmap.v -map <inject>", " (if -extra-map)");
} else {
std::string techmap_opts;
@ -326,13 +338,13 @@ struct SynthPass : public ScriptPass {
if ((!noabc && !flowmap) || help_mode) {
#ifdef YOSYS_ENABLE_ABC
if (help_mode) {
run(abc + " -fast", " (unless -noabc, unless -lut)");
run(abc + " -fast -lut k", "(unless -noabc, if -lut)");
run(abc, " (unless -noabc, unless -lut)");
run(abc + " -lut k", "(unless -noabc, if -lut)");
} else {
if (lut)
run(stringf("%s -fast -lut %d", abc, lut));
run(stringf("%s -lut %d", abc, lut));
else
run(abc + " -fast");
run(abc);
}
run("opt -fast", " (unless -noabc)");
#endif

44
techlibs/common/techmap.v
View file

@ -59,7 +59,7 @@ module _90_simplemap_compare_ops;
endmodule
(* techmap_simplemap *)
(* techmap_celltype = "$buf $pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx" *)
(* techmap_celltype = "$buf $pos $slice $concat $mux $pmux $tribuf $bmux $bwmux $bweqx" *)
module _90_simplemap_various;
endmodule
@ -563,48 +563,6 @@ module _90_pow (A, B, Y);
wire _TECHMAP_FAIL_ = 1;
endmodule
// --------------------------------------------------------
// Parallel Multiplexers
// --------------------------------------------------------
(* techmap_celltype = "$pmux" *)
module _90_pmux (A, B, S, Y);
parameter WIDTH = 1;
parameter S_WIDTH = 1;
(* force_downto *)
input [WIDTH-1:0] A;
(* force_downto *)
input [WIDTH*S_WIDTH-1:0] B;
(* force_downto *)
input [S_WIDTH-1:0] S;
(* force_downto *)
output [WIDTH-1:0] Y;
(* force_downto *)
wire [WIDTH-1:0] Y_B;
genvar i, j;
generate
(* force_downto *)
wire [WIDTH*S_WIDTH-1:0] B_AND_S;
for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
end:B_AND
for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
(* force_downto *)
wire [S_WIDTH-1:0] B_AND_BITS;
for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
end:B_AND_BITS_COLLECT
assign Y_B[i] = |B_AND_BITS;
end:B_OR
endgenerate
assign Y = |S ? Y_B : A;
endmodule
// --------------------------------------------------------
// Demultiplexers
// --------------------------------------------------------

42
techlibs/coolrunner2/CMakeLists.txt Normal file
View file

@ -0,0 +1,42 @@
yosys_pass(coolrunner2_sop
coolrunner2_sop.cc
)
yosys_pass(coolrunner2_fixup
coolrunner2_fixup.cc
)
yosys_pass(synth_coolrunner2
synth_coolrunner2.cc
REQUIRES
abc
attrmvcp
blackbox
check
clean
coolrunner2_fixup
coolrunner2_sop
dffinit
dfflibmap
extract
extract_counter
flatten
hierarchy
iopadmap
opt
proc
read_verilog
splitnets
stat
synth
techmap
tribuf
write_json
DATA_DIR
coolrunner2
DATA_FILES
cells_latch.v
cells_sim.v
cells_counter_map.v
tff_extract.v
xc2_dff.lib
)

10
techlibs/coolrunner2/Makefile.inc
View file

@ -1,10 +0,0 @@
OBJS += techlibs/coolrunner2/synth_coolrunner2.o
OBJS += techlibs/coolrunner2/coolrunner2_sop.o
OBJS += techlibs/coolrunner2/coolrunner2_fixup.o
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v))
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_counter_map.v))
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/tff_extract.v))
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/xc2_dff.lib))

1
techlibs/coolrunner2/synth_coolrunner2.cc
View file

@ -132,6 +132,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc");
run("check");
run("flatten");
run("tribuf -logic");
}

19
techlibs/easic/CMakeLists.txt Normal file
View file

@ -0,0 +1,19 @@
yosys_pass(synth_easic
synth_easic.cc
REQUIRES
abc
blackbox
check
dfflibmap
flatten
hierarchy
memory_map
opt
opt_clean
proc
read_liberty
stat
synth
techmap
write_verilog
)

3
techlibs/easic/Makefile.inc
View file

@ -1,3 +0,0 @@
OBJS += techlibs/easic/synth_easic.o

1
techlibs/easic/synth_easic.cc
View file

@ -142,6 +142,7 @@ struct SynthEasicPass : public ScriptPass
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc");
run("check");
run("flatten");
}

40
techlibs/efinix/CMakeLists.txt Normal file
View file

@ -0,0 +1,40 @@
yosys_pass(efinix_fixcarry
efinix_fixcarry.cc
)
yosys_pass(synth_efinix
synth_efinix.cc
REQUIRES
abc
blackbox
check
clean
clkbufmap
deminout
dfflegalize
efinix_fixcarry
flatten
hierarchy
memory_libmap
memory_map
opt
opt_expr
proc
read_verilog
simplemap
stat
synth
techmap
tribuf
write_edif
write_json
DATA_DIR
efinix
DATA_FILES
cells_map.v
arith_map.v
cells_sim.v
brams_map.v
gbuf_map.v
brams.txt
)

10
techlibs/efinix/Makefile.inc
View file

@ -1,10 +0,0 @@
OBJS += techlibs/efinix/synth_efinix.o
OBJS += techlibs/efinix/efinix_fixcarry.o
$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/gbuf_map.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams.txt))

4
techlibs/efinix/efinix_fixcarry.cc
View file

@ -65,7 +65,7 @@ static void fix_carry_chain(Module *module)
continue;
adders_to_fix_cells.push_back(cell);
log("Found %s cell named %s with invalid CI signal.\n", log_id(cell->type), log_id(cell));
log("Found %s cell named %s with invalid CI signal.\n", cell->type.unescape(), cell);
}
}
@ -74,7 +74,7 @@ static void fix_carry_chain(Module *module)
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI));
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescape(), cell);
Cell *c = module->addCell(NEW_ID, ID(EFX_ADD));
SigBit new_bit = module->addWire(NEW_ID);
c->setParam(ID(I0_POLARITY), State::S1);

1
techlibs/efinix/synth_efinix.cc
View file

@ -148,6 +148,7 @@ struct SynthEfinixPass : public ScriptPass
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc");
run("check");
run("flatten");
run("tribuf -logic");
run("deminout");

41
techlibs/fabulous/CMakeLists.txt Normal file
View file

@ -0,0 +1,41 @@
yosys_pass(synth_fabulous
synth_fabulous.cc
REQUIRES
abc
alumacc
check
clean
deminout
dfflegalize
flatten
fsm
hierarchy
iopadmap
memory
memory_libmap
memory_map
opt
opt_clean
opt_expr
peepopt
proc
read_verilog
share
stat
techmap
tribuf
wreduce
write_blif
write_json
DATA_DIR
fabulous
DATA_FILES
cells_map.v
prims.v
latches_map.v
ff_map.v
ram_regfile.txt
regfile_map.v
io_map.v
arith_map.v
)

11
techlibs/fabulous/Makefile.inc
View file

@ -1,11 +0,0 @@
OBJS += techlibs/fabulous/synth_fabulous.o
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/cells_map.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/prims.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/latches_map.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ff_map.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ram_regfile.txt))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/regfile_map.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/io_map.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/arith_map.v))

24
techlibs/fabulous/prims.v
View file

@ -149,6 +149,30 @@ module OutPass4_frame_config (input CLK, I0, I1, I2, I3);
endmodule
(* blackbox, keep *)
module InPass4_frame_config_mux #(
parameter [3:0] O_reg = 0
) (
input CLK,
output O0,
output O1,
output O2,
output O3
);
endmodule
(* blackbox, keep *)
module OutPass4_frame_config_mux #(
parameter [3:0] I_reg = 0
) (
input I0,
input I1,
input I2,
input I3,
input CLK
);
endmodule
(* keep *)
module IO_1_bidirectional_frame_config_pass (input CLK, T, I, output Q, O, (* iopad_external_pin *) inout PAD);
assign PAD = T ? 1'bz : I;

1
techlibs/fabulous/synth_fabulous.cc
View file

@ -286,6 +286,7 @@ struct SynthPass : public ScriptPass
if (check_label("flatten", "(unless -noflatten)"))
{
if (flatten) {
run("check");
run("flatten");
run("tribuf -logic");
run("deminout");

2
techlibs/gatemate/.gitignore vendored
View file

@ -1,4 +1,2 @@
lut_tree_cells.genlib
lut_tree_map.v
lut_tree_lib.mk

65
techlibs/gatemate/CMakeLists.txt Normal file
View file

@ -0,0 +1,65 @@
yosys_pass(gatemate_foldinv
gatemate_foldinv.cc
)
add_custom_command(
DEPENDS make_lut_tree_lib.py
# yosys_pass(DATA_FILES) expects the files to be in the source directory
OUTPUT ${CMAKE_CURRENT_SOURCE_DIR}/lut_tree_cells.genlib ${CMAKE_CURRENT_SOURCE_DIR}/lut_tree_map.v
COMMAND ${Python3_EXECUTABLE} make_lut_tree_lib.py
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
VERBATIM
)
yosys_pass(synth_gatemate
synth_gatemate.cc
REQUIRES
abc
alumacc
blackbox
check
clean
clkbufmap
deminout
dfflegalize
flatten
fsm
gatemate_foldinv
hierarchy
iopadmap
memory
memory_libmap
memory_map
muxcover
muxpack
opt
opt_clean
opt_expr
peepopt
proc
read_verilog
share
simplemap
stat
techmap
tribuf
wreduce
write_json
write_verilog
DATA_DIR
gatemate
DATA_FILES
reg_map.v
mux_map.v
lut_map.v
mul_map.v
arith_map.v
cells_sim.v
cells_bb.v
brams_map.v
brams.txt
brams_init_20.vh
brams_init_40.vh
inv_map.v
lut_tree_cells.genlib
lut_tree_map.v
)

34
techlibs/gatemate/Makefile.inc
View file

@ -1,34 +0,0 @@
OBJS += techlibs/gatemate/synth_gatemate.o
OBJS += techlibs/gatemate/gatemate_foldinv.o
GENFILES += techlibs/gatemate/lut_tree_cells.genlib
GENFILES += techlibs/gatemate/lut_tree_map.v
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/reg_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/mux_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/lut_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/mul_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/arith_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/cells_sim.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/cells_bb.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams_map.v))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams.txt))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams_init_20.vh))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/brams_init_40.vh))
$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/inv_map.v))
EXTRA_OBJS += techlibs/gatemate/lut_tree_lib.mk
.SECONDARY: techlibs/gatemate/lut_tree_lib.mk
techlibs/gatemate/lut_tree_lib.mk: techlibs/gatemate/make_lut_tree_lib.py
$(Q) mkdir -p techlibs/gatemate
$(P) $(PYTHON_EXECUTABLE) $<
$(Q) touch $@
techlibs/gatemate/lut_tree_cells.genlib: techlibs/gatemate/lut_tree_lib.mk
techlibs/gatemate/lut_tree_map.v: techlibs/gatemate/lut_tree_lib.mk
$(eval $(call add_gen_share_file,share/gatemate,techlibs/gatemate/lut_tree_cells.genlib))
$(eval $(call add_gen_share_file,share/gatemate,techlibs/gatemate/lut_tree_map.v))

4
techlibs/gatemate/make_lut_tree_lib.py
View file

@ -185,7 +185,7 @@ for name, expr in base_cells:
if name not in ("$__CC4_XX", "$__CC3_X"):
cells.append([name + "_X", 12, XOR(E, expr)])
with open("techlibs/gatemate/lut_tree_cells.genlib", "w") as glf:
with open("lut_tree_cells.genlib", "w") as glf:
def mkGate(name, cost, expr, max_load=9999, block_delay = 10, fanout_delay = 5):
name = name.replace(" ", "")
expr = expr.map()
@ -280,7 +280,7 @@ lut_prims = {
)
}
with open("techlibs/gatemate/lut_tree_map.v", "w") as vf:
with open("lut_tree_map.v", "w") as vf:
# Non-automatic rules
print("""
module \\$__ZERO (output Y); assign Y = 1'b0; endmodule

31
techlibs/gatemate/synth_gatemate.cc
View file

@ -56,6 +56,9 @@ struct SynthGateMatePass : public ScriptPass
log(" -noflatten\n");
log(" do not flatten design before synthesis.\n");
log("\n");
log(" -scopename\n");
log(" create 'scopename' attributes when flattening the netlist.\n");
log("\n");
log(" -nobram\n");
log(" do not use CC_BRAM_20K or CC_BRAM_40K cells in output netlist.\n");
log("\n");
@ -69,7 +72,8 @@ struct SynthGateMatePass : public ScriptPass
log(" do not use CC_MX{8,4} multiplexer cells in output netlist.\n");
log("\n");
log(" -luttree\n");
log(" use new LUT tree mapping approach (EXPERIMENTAL).\n");
log(" use LUT tree mapping for output to nextpnr. Do not use this if targeting\n");
log(" legacy p_r.\n");
log("\n");
log(" -dff\n");
log(" run 'abc' with -dff option\n");
@ -77,6 +81,9 @@ struct SynthGateMatePass : public ScriptPass
log(" -retime\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -abc_new\n");
log(" use 'abc_new' instead of 'abc' for mapping. (EXPERIMENTAL)\n");
log("\n");
log(" -noiopad\n");
log(" disable I/O buffer insertion (useful for hierarchical or \n");
log(" out-of-context flows).\n");
@ -90,7 +97,7 @@ struct SynthGateMatePass : public ScriptPass
}
string top_opt, vlog_file, json_file;
bool noflatten, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf;
bool noflatten, scopename, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf, abc_new;
void clear_flags() override
{
@ -98,6 +105,7 @@ struct SynthGateMatePass : public ScriptPass
vlog_file = "";
json_file = "";
noflatten = false;
scopename = false;
nobram = false;
noaddf = false;
nomult = false;
@ -108,6 +116,7 @@ struct SynthGateMatePass : public ScriptPass
retime = false;
noiopad = false;
noclkbuf = false;
abc_new = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -142,6 +151,10 @@ struct SynthGateMatePass : public ScriptPass
noflatten = true;
continue;
}
if (args[argidx] == "-scopename") {
scopename = true;
continue;
}
if (args[argidx] == "-nobram") {
nobram = true;
continue;
@ -182,6 +195,10 @@ struct SynthGateMatePass : public ScriptPass
noclkbuf = true;
continue;
}
if (args[argidx] == "-abc_new") {
abc_new = true;
continue;
}
break;
}
extra_args(args, argidx, design);
@ -210,7 +227,9 @@ struct SynthGateMatePass : public ScriptPass
{
run("proc");
if (!noflatten) {
run("flatten");
run("check");
std::string flatten_args = scopename ? " -scopename" : "";
run("flatten" + flatten_args);
}
run("tribuf -logic");
run("deminout");
@ -312,7 +331,11 @@ struct SynthGateMatePass : public ScriptPass
if (dff) {
abc_args += " -dff";
}
run("abc " + abc_args, "(with -luttree)");
if (abc_new) {
run("abc_new " + abc_args, "(with -luttree and -abc_new)");
} else {
run("abc " + abc_args, "(with -luttree, without -abc_new)");
}
run("techmap -map +/gatemate/lut_tree_map.v", "(with -luttree)");
run("gatemate_foldinv", "(with -luttree)");
run("techmap -map +/gatemate/inv_map.v", "(with -luttree)");

55
techlibs/gowin/CMakeLists.txt Normal file
View file

@ -0,0 +1,55 @@
yosys_pass(synth_gowin
synth_gowin.cc
REQUIRES
abc
abc9
alumacc
autoname
blackbox
check
clean
deminout
dfflegalize
flatten
fsm
hierarchy
hilomap
iopadmap
memory
memory_libmap
memory_map
opt
opt_clean
opt_expr
opt_lut_ins
peepopt
proc
read_verilog
setundef
share
simplemap
sort
splitnets
stat
techmap
tribuf
wreduce
write_json
write_verilog
DATA_DIR
gowin
DATA_FILES
cells_map.v
cells_sim.v
cells_latch.v
cells_xtra_gw1n.v
cells_xtra_gw2a.v
cells_xtra_gw5a.v
arith_map.v
brams_map.v
brams_map_gw5a.v
brams.txt
lutrams_map.v
lutrams.txt
dsp_map.v
)

15
techlibs/gowin/Makefile.inc
View file

@ -1,15 +0,0 @@
OBJS += techlibs/gowin/synth_gowin.o
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra_gw1n.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra_gw2a.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra_gw5a.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map_gw5a.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/dsp_map.v))

5
techlibs/gowin/brams.txt
View file

@ -51,11 +51,6 @@ ram block $__GOWIN_DP_ {
portoption "WRITE_MODE" 1 {
rdwr new;
}
ifndef gw5a {
portoption "WRITE_MODE" 2 {
rdwr old;
}
}
wrbe_separate;
}
}

2
techlibs/gowin/brams_map.v
View file

@ -205,7 +205,7 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST;
wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_B_WR_BE);
wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE);
generate

2
techlibs/gowin/brams_map_gw5a.v
View file

@ -205,7 +205,7 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST;
wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_B_WR_BE);
wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE);
generate

37
techlibs/gowin/cells_latch.v Normal file
View file

@ -0,0 +1,37 @@
`default_nettype none
// DL D Latch with Positive Gate
module \$_DLATCH_P_ (input E, D, output Q);
DL _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DLN D Latch with Negative Gate
module \$_DLATCH_N_ (input E, D, output Q);
DLN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DLC D Latch with Positive Gate and Asynchronous Clear
module \$_DLATCH_PP0_ (input E, R, D, output Q);
DLC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E), .CLEAR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DLNC D Latch with Negative Gate and Asynchronous Clear
module \$_DLATCH_NP0_ (input E, R, D, output Q);
DLNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E), .CLEAR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DLP D Latch with Positive Gate and Asynchronous Preset
module \$_DLATCH_PP1_ (input E, R, D, output Q);
DLP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E), .PRESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DLNP D Latch with Negative Gate and Asynchronous Preset
module \$_DLATCH_NP1_ (input E, R, D, output Q);
DLNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E), .PRESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule

95
techlibs/gowin/cells_sim.v
View file

@ -540,6 +540,101 @@ module DFFNCE (output reg Q, input D, CLK, CE, CLEAR);
end
endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)
// Latch sim cells
// Gate signal uses CLK port name to match the physical DFF BEL pin
module DL (output reg Q, input D, CLK);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (CLK) Q <= D;
endmodule
module DLN (output reg Q, input D, CLK);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (!CLK) Q <= D;
endmodule
module DLE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (CLK && CE) Q <= D;
endmodule
module DLNE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (!CLK && CE) Q <= D;
endmodule
module DLC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (CLEAR) Q <= 1'b0;
else if (CLK) Q <= D;
endmodule
module DLCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (CLEAR) Q <= 1'b0;
else if (CLK && CE) Q <= D;
endmodule
module DLNC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (CLEAR) Q <= 1'b0;
else if (!CLK) Q <= D;
endmodule
module DLNCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (CLEAR) Q <= 1'b0;
else if (!CLK && CE) Q <= D;
endmodule
module DLP (output reg Q, input D, CLK, PRESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (PRESET) Q <= 1'b1;
else if (CLK) Q <= D;
endmodule
module DLPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (PRESET) Q <= 1'b1;
else if (CLK && CE) Q <= D;
endmodule
module DLNP (output reg Q, input D, CLK, PRESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (PRESET) Q <= 1'b1;
else if (!CLK) Q <= D;
endmodule
module DLNPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
if (PRESET) Q <= 1'b1;
else if (!CLK && CE) Q <= D;
endmodule
// TODO add more DFF sim cells
module VCC(output V);

15
techlibs/gowin/synth_gowin.cc
View file

@ -265,8 +265,10 @@ struct SynthGowinPass : public ScriptPass
if (check_label("coarse"))
{
run("proc");
if (flatten || help_mode)
if (flatten || help_mode) {
run("check");
run("flatten", "(unless -noflatten)");
}
run("tribuf -logic");
run("deminout");
run("opt_expr");
@ -309,7 +311,7 @@ struct SynthGowinPass : public ScriptPass
if (nolutram)
args += " -no-auto-distributed";
}
run(stringf("memory_libmap -lib +/gowin/lutrams.txt -lib +/gowin/brams.txt -D %s", family) + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
run(stringf("memory_libmap -lib +/gowin/lutrams.txt -lib +/gowin/brams.txt%s", family == "gw5a" ? " -D gw5a" : "") + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
run(stringf("techmap -map +/gowin/lutrams_map.v -map +/gowin/brams_map%s.v", family == "gw5a" ? "_gw5a" : ""));
}
@ -340,17 +342,18 @@ struct SynthGowinPass : public ScriptPass
run("opt_clean");
if (family == "gw5a") {
if (strict_gw5a_dffs) {
run("dfflegalize -cell $_SDFFE_PP?P_ r -cell $_DFFE_PP?P_ r");
run("dfflegalize -cell $_SDFFE_PP?P_ r -cell $_DFFE_PP?P_ r -cell $_DLATCH_?_ x -cell $_DLATCH_?P?_ x");
} else {
run("dfflegalize -cell $_DFF_?_ 0 -cell $_SDFFE_PP?P_ r -cell $_DFFE_PP?P_ r");
run("dfflegalize -cell $_DFF_?_ 0 -cell $_SDFFE_PP?P_ r -cell $_DFFE_PP?P_ r -cell $_DLATCH_?_ x -cell $_DLATCH_?P?_ x");
}
} else {
if (nodffe)
run("dfflegalize -cell $_DFF_?_ 0 -cell $_SDFF_?P?_ r -cell $_DFF_?P?_ r");
run("dfflegalize -cell $_DFF_?_ 0 -cell $_SDFF_?P?_ r -cell $_DFF_?P?_ r -cell $_DLATCH_?_ x -cell $_DLATCH_?P?_ x");
else
run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r");
run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r -cell $_DLATCH_?_ x -cell $_DLATCH_?P?_ x");
}
run("techmap -map +/gowin/cells_map.v");
run("techmap -map +/gowin/cells_latch.v");
run("opt_expr -mux_undef");
run("simplemap");
}

42
techlibs/greenpak4/CMakeLists.txt Normal file
View file

@ -0,0 +1,42 @@
yosys_pass(greenpak4_dffinv
greenpak4_dffinv.cc
)
yosys_pass(synth_greenpak4
synth_greenpak4.cc
REQUIRES
abc
attrmvcp
blackbox
check
clean
dffinit
dfflibmap
extract_counter
flatten
greenpak4_dffinv
hierarchy
iopadmap
memory_map
nlutmap
opt
proc
read_verilog
shregmap
stat
synth
techmap
tribuf
write_json
DATA_DIR
greenpak4
DATA_FILES
cells_blackbox.v
cells_latch.v
cells_map.v
cells_sim.v
cells_sim_ams.v
cells_sim_digital.v
cells_sim_wip.v
gp_dff.lib
)

12
techlibs/greenpak4/Makefile.inc
View file

@ -1,12 +0,0 @@
OBJS += techlibs/greenpak4/synth_greenpak4.o
OBJS += techlibs/greenpak4/greenpak4_dffinv.o
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_blackbox.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_ams.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_digital.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_wip.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/gp_dff.lib))

2
techlibs/greenpak4/greenpak4_dffinv.cc
View file

@ -86,7 +86,7 @@ void invert_gp_dff(Cell *cell, bool invert_input)
cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
log("Merged %s inverter into cell %s.%s: %s -> %s\n", invert_input ? "input" : "output",
log_id(cell->module), log_id(cell), cell_type.c_str()+1, log_id(cell->type));
cell->module, cell, cell_type.c_str()+1, cell->type.unescape());
}
struct Greenpak4DffInvPass : public Pass {

1
techlibs/greenpak4/synth_greenpak4.cc
View file

@ -144,6 +144,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc");
run("check");
run("flatten");
run("tribuf -logic");
}

84
techlibs/ice40/CMakeLists.txt Normal file
View file

@ -0,0 +1,84 @@
yosys_pass(ice40_braminit
ice40_braminit.cc
)
yosys_pass(ice40_opt
ice40_opt.cc
REQUIRES
opt_expr
opt_merge
opt_dff
opt_clean
)
pmgen_command(ice40_dsp
ice40_dsp.pmg
)
yosys_pass(ice40_dsp
ice40_dsp.cc
${PMGEN_ice40_dsp_OUTPUT}
)
pmgen_command(ice40_wrapcarry
ice40_wrapcarry.pmg
)
yosys_pass(ice40_wrapcarry
ice40_wrapcarry.cc
${PMGEN_ice40_wrapcarry_OUTPUT}
)
yosys_pass(synth_ice40
synth_ice40.cc
REQUIRES
abc
abc9
alumacc
autoname
blackbox
check
chtype
clean
deminout
dfflegalize
flatten
flowmap
fsm
hierarchy
ice40_braminit
ice40_dsp
ice40_opt
ice40_wrapcarry
memory
memory_dff
memory_libmap
memory_map
opt
opt_clean
opt_expr
opt_lut
peepopt
proc
read_verilog
select
setattr
share
simplemap
stat
techmap
tribuf
wreduce
write_blif
write_edif
write_json
DATA_DIR
ice40
DATA_FILES
arith_map.v
cells_map.v
ff_map.v
cells_sim.v
latches_map.v
brams.txt
brams_map.v
spram.txt
spram_map.v
dsp_map.v
abc9_model.v
)

26
techlibs/ice40/Makefile.inc
View file

@ -1,26 +0,0 @@
OBJS += techlibs/ice40/synth_ice40.o
OBJS += techlibs/ice40/ice40_braminit.o
OBJS += techlibs/ice40/ice40_opt.o
$(eval $(call add_share_file,share/ice40,techlibs/ice40/arith_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/ff_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/spram.txt))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/spram_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_model.v))
OBJS += techlibs/ice40/ice40_dsp.o
GENFILES += techlibs/ice40/ice40_dsp_pm.h
techlibs/ice40/ice40_dsp.o: techlibs/ice40/ice40_dsp_pm.h
$(eval $(call add_extra_objs,techlibs/ice40/ice40_dsp_pm.h))
OBJS += techlibs/ice40/ice40_wrapcarry.o
GENFILES += techlibs/ice40/ice40_wrapcarry_pm.h
techlibs/ice40/ice40_wrapcarry.o: techlibs/ice40/ice40_wrapcarry_pm.h
$(eval $(call add_extra_objs,techlibs/ice40/ice40_wrapcarry_pm.h))

2
techlibs/ice40/ice40_braminit.cc
View file

@ -46,7 +46,7 @@ static void run_ice40_braminit(Module *module)
continue;
/* Open file */
log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file);
log("Processing %s : %s\n", cell, init_file);
std::ifstream f;
f.open(init_file.c_str());

38
techlibs/ice40/ice40_dsp.cc
View file

@ -29,17 +29,17 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
{
auto &st = pm.st_ice40_dsp;
log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
log("Checking %s.%s for iCE40 DSP inference.\n", pm.module, st.mul);
log_debug("ffA: %s\n", log_id(st.ffA, "--"));
log_debug("ffB: %s\n", log_id(st.ffB, "--"));
log_debug("ffCD: %s\n", log_id(st.ffCD, "--"));
log_debug("mul: %s\n", log_id(st.mul, "--"));
log_debug("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
log_debug("ffH: %s\n", log_id(st.ffH, "--"));
log_debug("add: %s\n", log_id(st.add, "--"));
log_debug("mux: %s\n", log_id(st.mux, "--"));
log_debug("ffO: %s\n", log_id(st.ffO, "--"));
log_debug("ffA: %s\n", st.ffA ? st.ffA->name.unescape() : "--");
log_debug("ffB: %s\n", st.ffB ? st.ffB->name.unescape() : "--");
log_debug("ffCD: %s\n", st.ffCD ? st.ffCD->name.unescape() : "--");
log_debug("mul: %s\n", st.mul ? st.mul->name.unescape() : "--");
log_debug("ffFJKG: %s\n", st.ffFJKG ? st.ffFJKG->name.unescape() : "--");
log_debug("ffH: %s\n", st.ffH ? st.ffH->name.unescape() : "--");
log_debug("add: %s\n", st.add ? st.add->name.unescape() : "--");
log_debug("mux: %s\n", st.mux ? st.mux->name.unescape() : "--");
log_debug("ffO: %s\n", st.ffO ? st.ffO->name.unescape() : "--");
log_debug("\n");
if (GetSize(st.sigA) > 16) {
@ -64,7 +64,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
Cell *cell = st.mul;
if (cell->type == ID($mul)) {
log(" replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
log(" replacing %s with SB_MAC16 cell.\n", st.mul->type.unescape());
cell = pm.module->addCell(NEW_ID, ID(SB_MAC16));
pm.module->swap_names(cell, st.mul);
@ -135,22 +135,22 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), st.clock_pol ? "posedge" : "negedge");
if (st.ffA)
log(" ffA:%s", log_id(st.ffA));
log(" ffA:%s", st.ffA);
if (st.ffB)
log(" ffB:%s", log_id(st.ffB));
log(" ffB:%s", st.ffB);
if (st.ffCD)
log(" ffCD:%s", log_id(st.ffCD));
log(" ffCD:%s", st.ffCD);
if (st.ffFJKG)
log(" ffFJKG:%s", log_id(st.ffFJKG));
log(" ffFJKG:%s", st.ffFJKG);
if (st.ffH)
log(" ffH:%s", log_id(st.ffH));
log(" ffH:%s", st.ffH);
if (st.ffO)
log(" ffO:%s", log_id(st.ffO));
log(" ffO:%s", st.ffO);
log("\n");
}
@ -196,9 +196,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
if (st.add) {
accum = (st.ffO && st.add->getPort(st.addAB == ID::A ? ID::B : ID::A) == st.sigO);
if (accum)
log(" accumulator %s (%s)\n", log_id(st.add), log_id(st.add->type));
log(" accumulator %s (%s)\n", st.add, st.add->type.unescape());
else
log(" adder %s (%s)\n", log_id(st.add), log_id(st.add->type));
log(" adder %s (%s)\n", st.add, st.add->type.unescape());
cell->setPort(ID(ADDSUBTOP), st.add->type == ID($add) ? State::S0 : State::S1);
cell->setPort(ID(ADDSUBBOT), st.add->type == ID($add) ? State::S0 : State::S1);
} else {

6
techlibs/ice40/ice40_opt.cc
View file

@ -83,7 +83,7 @@ static void run_ice40_opts(Module *module)
module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
module, cell, log_signal(replacement_output));
module->remove(cell);
}
continue;
@ -137,7 +137,7 @@ static void run_ice40_opts(Module *module)
module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
module, cell, log_signal(replacement_output));
cell->type = ID($lut);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) });
@ -175,7 +175,7 @@ static void run_ice40_opts(Module *module)
remap_lut:
module->design->scratchpad_set_bool("opt.did_something", true);
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", log_id(module), log_id(cell));
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", module, cell);
cell->type = ID($lut);
cell->setParam(ID::WIDTH, 4);

4
techlibs/ice40/ice40_wrapcarry.cc
View file

@ -31,8 +31,8 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
#if 0
log("\n");
log("carry: %s\n", log_id(st.carry, "--"));
log("lut: %s\n", log_id(st.lut, "--"));
log("carry: %s\n", st.carry ? st.carry->name.unescape() : "--");
log("lut: %s\n", st.lut ? st.lut->name.unescape() : "--");
#endif
log(" replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n");

1
techlibs/ice40/synth_ice40.cc
View file

@ -309,6 +309,7 @@ struct SynthIce40Pass : public ScriptPass
if (check_label("flatten", "(unless -noflatten)"))
{
if (flatten) {
run("check");
run("flatten");
run("tribuf -logic");
run("deminout");

52
techlibs/intel/CMakeLists.txt Normal file
View file

@ -0,0 +1,52 @@
yosys_pass(synth_intel
synth_intel.cc
REQUIRES
abc
abc9
autoname
blackbox
check
clean
deminout
dfflegalize
flatten
fsm
hierarchy
iopadmap
memory
memory_bram
memory_map
opt
opt_clean
opt_expr
peepopt
proc
read_verilog
setundef
stat
techmap
tribuf
wreduce
write_blif
write_verilog
DATA_DIR
intel
DATA_FILES
common/m9k_bb.v
common/altpll_bb.v
common/brams_m9k.txt
common/brams_map_m9k.v
common/ff_map.v
max10/cells_sim.v
max10/cells_map.v
cyclone10lp/cells_sim.v
cyclone10lp/cells_map.v
cycloneiv/cells_sim.v
cycloneiv/cells_map.v
cycloneive/cells_sim.v
cycloneive/cells_map.v
)

14
techlibs/intel/Makefile.inc
View file

@ -1,14 +0,0 @@
OBJS += techlibs/intel/synth_intel.o
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/ff_map.v))
# Add the cell models and mappings for the VQM backend
families := max10 cyclone10lp cycloneiv cycloneive
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))

6
techlibs/intel/synth_intel.cc
View file

@ -198,9 +198,11 @@ struct SynthIntelPass : public ScriptPass {
if (check_label("coarse")) {
run("proc");
if (flatten || help_mode)
if (flatten || help_mode) {
run("check");
run("flatten", "(skip if -noflatten)");
run("tribuf -logic");
}
run("tribuf -logic");
run("deminout");
run("opt_expr");
run("opt_clean");

57
techlibs/intel_alm/CMakeLists.txt Normal file
View file

@ -0,0 +1,57 @@
yosys_pass(synth_intel_alm
synth_intel_alm.cc
REQUIRES
abc9
alumacc
autoname
blackbox
check
clean
clkbufmap
deminout
dfflegalize
flatten
fsm
hierarchy
iopadmap
memory
memory_bram
memory_map
opt
opt_clean
opt_expr
peepopt
proc
read_verilog
share
stat
techmap
tribuf
wreduce
DATA_DIR
intel_alm
DATA_FILES
# Techmap
common/abc9_map.v
common/abc9_unmap.v
common/abc9_model.v
common/alm_map.v
common/alm_sim.v
common/arith_alm_map.v
common/dff_map.v
common/dff_sim.v
common/dsp_sim.v
common/dsp_map.v
common/mem_sim.v
common/misc_sim.v
cyclonev/cells_sim.v
# RAM
common/bram_m10k.txt
common/bram_m10k_map.v
common/lutram_mlab.txt
# Miscellaneous
common/megafunction_bb.v
)

26
techlibs/intel_alm/Makefile.inc
View file

@ -1,26 +0,0 @@
OBJS += techlibs/intel_alm/synth_intel_alm.o
# Techmap
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/abc9_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/abc9_unmap.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/abc9_model.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/alm_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/alm_sim.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/arith_alm_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_sim.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_sim.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/misc_sim.v))
$(eval $(call add_share_file,share/intel_alm/cyclonev,techlibs/intel_alm/cyclonev/cells_sim.v))
# RAM
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
# Miscellaneous
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/megafunction_bb.v))

4
techlibs/intel_alm/synth_intel_alm.cc
View file

@ -184,8 +184,10 @@ struct SynthIntelALMPass : public ScriptPass {
if (check_label("coarse")) {
run("proc");
if (flatten || help_mode)
if (flatten || help_mode) {
run("check");
run("flatten", "(skip if -noflatten)");
}
run("tribuf -logic");
run("deminout");
run("opt_expr");

101
techlibs/lattice/CMakeLists.txt Normal file
View file

@ -0,0 +1,101 @@
pmgen_command(lattice_dsp_nexus
lattice_dsp_nexus.pmg
)
yosys_pass(lattice_dsp_nexus
lattice_dsp_nexus.cc
${PMGEN_lattice_dsp_nexus_OUTPUT}
)
yosys_pass(lattice_gsr
lattice_gsr.cc
)
yosys_pass(synth_lattice
synth_lattice.cc
REQUIRES
abc
abc9
alumacc
attrmvcp
autoname
blackbox
booth
check
clean
deminout
dfflegalize
flatten
fsm
hierarchy
iopadmap
lattice_dsp_nexus
lattice_gsr
memory
memory_libmap
memory_map
opt
opt_clean
opt_expr
opt_lut_ins
opt_merge
peepopt
proc
read_verilog
share
simplemap
stat
techmap
tribuf
wreduce
write_edif
write_json
zinit
DATA_EXPLICIT
lattice/cells_ff.vh cells_ff.vh
lattice/cells_io.vh cells_io.vh
lattice/cells_map_trellis.v cells_map_trellis.v
lattice/cells_map_nexus.v cells_map_nexus.v
lattice/common_sim.vh common_sim.vh
lattice/parse_init.vh parse_init.vh
lattice/ccu2d_sim.vh ccu2d_sim.vh
lattice/ccu2c_sim.vh ccu2c_sim.vh
lattice/cells_sim_ecp5.v cells_sim_ecp5.v
lattice/cells_sim_xo2.v cells_sim_xo2.v
lattice/cells_sim_xo3.v cells_sim_xo3.v
lattice/cells_sim_xo3d.v cells_sim_xo3d.v
lattice/cells_sim_nexus.v cells_sim_nexus.v
lattice/cells_bb_ecp5.v cells_bb_ecp5.v
lattice/cells_bb_xo2.v cells_bb_xo2.v
lattice/cells_bb_xo3.v cells_bb_xo3.v
lattice/cells_bb_xo3d.v cells_bb_xo3d.v
lattice/cells_bb_nexus.v cells_bb_nexus.v
lattice/lutrams_map_trellis.v lutrams_map_trellis.v
lattice/lutrams_trellis.txt lutrams_trellis.txt
lattice/lutrams_map_nexus.v lutrams_map_nexus.v
lattice/lutrams_nexus.txt lutrams_nexus.txt
lattice/lrams_map_nexus.v lrams_map_nexus.v
lattice/lrams_nexus.txt lrams_nexus.txt
lattice/brams_map_16kd.v brams_map_16kd.v
lattice/brams_16kd.txt brams_16kd.txt
lattice/brams_map_8kc.v brams_map_8kc.v
lattice/brams_8kc.txt brams_8kc.txt
lattice/brams_map_nexus.v brams_map_nexus.v
lattice/brams_nexus.txt brams_nexus.txt
lattice/arith_map_ccu2c.v arith_map_ccu2c.v
lattice/arith_map_ccu2d.v arith_map_ccu2d.v
lattice/arith_map_nexus.v arith_map_nexus.v
lattice/latches_map.v latches_map.v
lattice/dsp_map_18x18.v dsp_map_18x18.v
lattice/dsp_map_nexus.v dsp_map_nexus.v
ecp5/cells_ff.vh cells_ff.vh
ecp5/cells_io.vh cells_io.vh
ecp5/common_sim.vh common_sim.vh
ecp5/ccu2c_sim.vh ccu2c_sim.vh
ecp5/cells_sim.v cells_sim_ecp5.v
ecp5/cells_bb.v cells_bb_ecp5.v
nexus/parse_init.vh parse_init.vh
nexus/cells_sim.v cells_sim_nexus.v
nexus/cells_xtra.v cells_bb_nexus.v
)

52
techlibs/lattice/Makefile.inc
View file

@ -1,52 +0,0 @@
OBJS += techlibs/lattice/synth_lattice.o
OBJS += techlibs/lattice/lattice_gsr.o
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_ff.vh))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_io.vh))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_map_trellis.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_map_nexus.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/common_sim.vh))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/parse_init.vh))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2d_sim.vh))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2c_sim.vh))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_ecp5.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo2.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3d.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_nexus.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_ecp5.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo2.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo3.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo3d.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_nexus.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_map_trellis.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_trellis.txt))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_map_nexus.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_nexus.txt))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/lrams_map_nexus.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/lrams_nexus.txt))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_16kd.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_16kd.txt))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_8kc.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_8kc.txt))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_nexus.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_nexus.txt))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2c.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2d.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_nexus.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/latches_map.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/dsp_map_18x18.v))
$(eval $(call add_share_file,share/lattice,techlibs/lattice/dsp_map_nexus.v))
$(eval $(call add_share_file,share/ecp5,techlibs/lattice/cells_ff.vh))
$(eval $(call add_share_file,share/ecp5,techlibs/lattice/cells_io.vh))
$(eval $(call add_share_file,share/ecp5,techlibs/lattice/common_sim.vh))
$(eval $(call add_share_file,share/ecp5,techlibs/lattice/ccu2c_sim.vh))
$(eval $(call add_share_file_and_rename,share/ecp5,techlibs/lattice/cells_sim_ecp5.v,cells_sim.v))
$(eval $(call add_share_file_and_rename,share/ecp5,techlibs/lattice/cells_bb_ecp5.v,cells_bb.v))
$(eval $(call add_share_file,share/nexus,techlibs/lattice/parse_init.vh))
$(eval $(call add_share_file_and_rename,share/nexus,techlibs/lattice/cells_sim_nexus.v,cells_sim.v))
$(eval $(call add_share_file_and_rename,share/nexus,techlibs/lattice/cells_bb_nexus.v,cells_xtra.v))

72
techlibs/lattice/dsp_map_nexus.v
View file

@ -77,3 +77,75 @@ module \$__NX_MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
.Z(Y)
);
endmodule
module \$__NX_MAC18X18 (input [17:0] A, input [17:0] B, input [47:0] C, output [53:0] Y);
parameter A_WIDTH = 18;
parameter B_WIDTH = 18;
parameter C_WIDTH = 48;
parameter Y_WIDTH = 48;
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter SUBTRACT = 0;
MULTADDSUB18X18 #(
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGINPUTC("BYPASS"),
.REGOUTPUT("BYPASS")
) _TECHMAP_REPLACE_ (
.A(A),
.B(B),
.C({6'b0, C}),
.SIGNED(A_SIGNED ? 1'b1 : 1'b0),
.ADDSUB(SUBTRACT ? 1'b1 : 1'b0),
.Z(Y)
);
endmodule
module \$__NX_PREADD18X18 (input [17:0] A, input [17:0] B, input [17:0] C, input CLK, output [35:0] Y);
parameter PIPELINED = 0;
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter C_SIGNED = 0;
MULTPREADD18X18 #(
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGINPUTC("BYPASS"),
.REGOUTPUT(PIPELINED ? "REGISTER" : "BYPASS")
) _TECHMAP_REPLACE_ (
.A(A),
.B(B),
.C(C),
.CLK(CLK),
.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
.SIGNEDC(C_SIGNED ? 1'b1 : 1'b0),
.Z(Y)
);
endmodule
module \$__NX_MAC9X9WIDE_4LANE (input [8:0] A0, B0, A1, B1, A2, B2, A3, B3, output [53:0] Y);
parameter SIGNED = 0;
MULTADDSUB9X9WIDE #(
.REGINPUTAB0("BYPASS"),
.REGINPUTAB1("BYPASS"),
.REGINPUTAB2("BYPASS"),
.REGINPUTAB3("BYPASS"),
.REGINPUTC("BYPASS"),
.REGOUTPUT("BYPASS")
) _TECHMAP_REPLACE_ (
.A0(A0), .B0(B0),
.A1(A1), .B1(B1),
.A2(A2), .B2(B2),
.A3(A3), .B3(B3),
.C(54'b0),
.SIGNED(SIGNED ? 1'b1 : 1'b0),
.ADDSUB(4'b0000),
.Z(Y)
);
endmodule

36
techlibs/lattice/lattice_dsp_nexus.cc Normal file
View file

@ -0,0 +1,36 @@
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
#include "techlibs/lattice/lattice_dsp_nexus_pm.h"
struct LatticeDspNexusPass : public Pass {
LatticeDspNexusPass() : Pass("lattice_dsp_nexus", "Lattice Nexus DSP inference") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" lattice_dsp_nexus [options] [selection]\n");
log("\n");
log("Infer Lattice Nexus sysDSP macrocells (MULTADDSUB18X18, MULTPREADD18X18,\n");
log("MULTADDSUB9X9WIDE) from MAC and dot-product patterns.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing LATTICE_DSP_NEXUS pass.\n");
extra_args(args, 1, design);
for (auto module : design->selected_modules()) {
lattice_dsp_nexus_pm pm(module, module->cells());
pm.run_nexus_mac9_4lane();
pm.run_nexus_mac18();
pm.run_nexus_preadd18();
}
}
} LatticeDspNexusPass;
PRIVATE_NAMESPACE_END

208
techlibs/lattice/lattice_dsp_nexus.pmg Normal file
View file

@ -0,0 +1,208 @@
pattern nexus_mac18
match mul
select mul->type.in($mul)
select GetSize(port(mul, \A)) <= 18
select GetSize(port(mul, \B)) <= 18
select GetSize(port(mul, \Y)) <= 48
endmatch
match add
select add->type.in($add, $sub)
select GetSize(port(add, \Y)) <= 48
choice <IdString> AB {\A, \B}
index <SigBit> port(add, AB)[0] === port(mul, \Y)[0]
endmatch
code
if (mul->getParam(\A_SIGNED).as_bool() != mul->getParam(\B_SIGNED).as_bool()) {
reject;
}
{
SigSpec mul_out = port(mul, \Y);
IdString add_AB;
if (GetSize(port(add, \A)) >= GetSize(mul_out) && port(add, \A).extract(0, GetSize(mul_out)) == mul_out) {
add_AB = \A;
} else if (GetSize(port(add, \B)) >= GetSize(mul_out) && port(add, \B).extract(0, GetSize(mul_out)) == mul_out) {
add_AB = \B;
} else {
reject;
}
Cell *mac = module->addCell(NEW_ID, "$__NX_MAC18X18");
IdString add_C = (add_AB == \A) ? \B : \A;
mac->setPort(\A, port(mul, \A));
mac->setPort(\B, port(mul, \B));
mac->setPort(\C, port(add, add_C));
mac->setPort(\Y, port(add, \Y));
mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED));
mac->setParam(\SUBTRACT, add->type == $sub ? State::S1 : State::S0);
autoremove(mul);
autoremove(add);
}
accept;
endcode
pattern nexus_preadd18
match preadd
select preadd->type.in($add, $sub)
select GetSize(port(preadd, \Y)) <= 19
endmatch
match mul
select mul->type.in($mul)
select GetSize(port(mul, \Y)) <= 48
choice <IdString> mul_AB {\A, \B}
index <SigBit> port(mul, mul_AB)[0] === port(preadd, \Y)[0]
endmatch
match pipe_ff
select pipe_ff->type.in($dff, $dffe, $sdff, $sdffe)
index <SigBit> port(pipe_ff, \D)[0] === port(mul, \Y)[0]
optional
endmatch
code
SigSpec preadd_out = port(preadd, \Y);
IdString actual_mul_AB;
if (GetSize(port(mul, \A)) >= GetSize(preadd_out) && port(mul, \A).extract(0, GetSize(preadd_out)) == preadd_out) {
actual_mul_AB = \A;
} else if (GetSize(port(mul, \B)) >= GetSize(preadd_out) && port(mul, \B).extract(0, GetSize(preadd_out)) == preadd_out) {
actual_mul_AB = \B;
} else {
reject;
}
{
Cell *mac = module->addCell(NEW_ID, "$__NX_PREADD18X18");
IdString mul_other = (actual_mul_AB == \A) ? \B : \A;
IdString sgn_AC = (mul_other == \A) ? \B_SIGNED : \A_SIGNED;
IdString sgn_B = (mul_other == \A) ? \A_SIGNED : \B_SIGNED;
SigSpec sig_A = port(preadd, \A);
SigSpec sig_C = port(preadd, \B);
SigSpec sig_B = port(mul, mul_other);
sig_A.extend_u0(18, false);
sig_C.extend_u0(18, false);
sig_B.extend_u0(18, false);
mac->setPort(\A, sig_A.extract(0, 18));
mac->setPort(\C, sig_C.extract(0, 18));
mac->setPort(\B, sig_B.extract(0, 18));
if (pipe_ff) {
mac->setPort(\Y, port(pipe_ff, \Q));
mac->setPort(\CLK, port(pipe_ff, \CLK));
mac->setParam(\PIPELINED, State::S1);
} else {
mac->setPort(\Y, port(mul, \Y));
mac->setPort(\CLK, State::S0);
mac->setParam(\PIPELINED, State::S0);
}
mac->setParam(\A_SIGNED, mul->getParam(sgn_AC));
mac->setParam(\B_SIGNED, mul->getParam(sgn_B));
mac->setParam(\C_SIGNED, mul->getParam(sgn_AC));
if (pipe_ff) autoremove(pipe_ff);
autoremove(mul);
autoremove(preadd);
}
accept;
endcode
pattern nexus_mac9_4lane
match add_top
select add_top->type == $add
endmatch
match add_mid
select add_mid->type == $add
index <SigBit> port(add_mid, \Y)[0] === port(add_top, \A)[0]
endmatch
match add_bot
select add_bot->type == $add
index <SigBit> port(add_bot, \Y)[0] === port(add_mid, \A)[0]
endmatch
match mul3
select mul3->type == $mul
select GetSize(port(mul3, \A)) <= 9 && GetSize(port(mul3, \B)) <= 9
index <SigBit> port(mul3, \Y)[0] === port(add_top, \B)[0]
endmatch
match mul2
select mul2->type == $mul
select GetSize(port(mul2, \A)) <= 9 && GetSize(port(mul2, \B)) <= 9
index <SigBit> port(mul2, \Y)[0] === port(add_mid, \B)[0]
endmatch
match mul1
select mul1->type == $mul
select GetSize(port(mul1, \A)) <= 9 && GetSize(port(mul1, \B)) <= 9
index <SigBit> port(mul1, \Y)[0] === port(add_bot, \B)[0]
endmatch
match mul0
select mul0->type == $mul
select GetSize(port(mul0, \A)) <= 9 && GetSize(port(mul0, \B)) <= 9
index <SigBit> port(mul0, \Y)[0] === port(add_bot, \A)[0]
endmatch
code
bool is_signed = mul0->getParam(\A_SIGNED).as_bool();
if (
mul0->getParam(\B_SIGNED).as_bool() != is_signed ||
mul1->getParam(\A_SIGNED).as_bool() != is_signed ||
mul1->getParam(\B_SIGNED).as_bool() != is_signed ||
mul2->getParam(\A_SIGNED).as_bool() != is_signed ||
mul2->getParam(\B_SIGNED).as_bool() != is_signed ||
mul3->getParam(\A_SIGNED).as_bool() != is_signed ||
mul3->getParam(\B_SIGNED).as_bool() != is_signed
) {
reject;
}
{
Cell *mac = module->addCell(NEW_ID, "$__NX_MAC9X9WIDE_4LANE");
auto ext9 = [&](SigSpec s) {
s.extend_u0(9, is_signed);
return s;
};
mac->setPort(\A0, ext9(port(mul0, \A)));
mac->setPort(\B0, ext9(port(mul0, \B)));
mac->setPort(\A1, ext9(port(mul1, \A)));
mac->setPort(\B1, ext9(port(mul1, \B)));
mac->setPort(\A2, ext9(port(mul2, \A)));
mac->setPort(\B2, ext9(port(mul2, \B)));
mac->setPort(\A3, ext9(port(mul3, \A)));
mac->setPort(\B3, ext9(port(mul3, \B)));
mac->setPort(\Y, port(add_top, \Y));
mac->setParam(\SIGNED, is_signed ? State::S1 : State::S0);
autoremove(add_top);
autoremove(add_mid);
autoremove(add_bot);
autoremove(mul0);
autoremove(mul1);
autoremove(mul2);
autoremove(mul3);
}
accept;
endcode

8
techlibs/lattice/lattice_gsr.cc
View file

@ -57,7 +57,7 @@ struct LatticeGsrPass : public Pass {
for (auto module : design->selected_modules())
{
log("Handling GSR in %s.\n", log_id(module));
log("Handling GSR in %s.\n", module);
SigMap sigmap(module);
@ -69,11 +69,11 @@ struct LatticeGsrPass : public Pass {
if (cell->type != ID(GSR) && cell->type != ID(SGSR))
continue;
if (found_gsr)
log_error("Found more than one GSR or SGSR cell in module %s.\n", log_id(module));
log_error("Found more than one GSR or SGSR cell in module %s.\n", module);
found_gsr = true;
SigSpec sig_gsr = cell->getPort(ID(GSR));
if (GetSize(sig_gsr) < 1)
log_error("GSR cell %s has disconnected GSR input.\n", log_id(cell));
log_error("GSR cell %s has disconnected GSR input.\n", cell);
gsr = sigmap(sig_gsr[0]);
}
@ -97,7 +97,7 @@ struct LatticeGsrPass : public Pass {
// For finding active low FF inputs
pool<SigBit> inverted_gsr;
log_debug("GSR net in module %s is %s.\n", log_id(module), log_signal(gsr));
log_debug("GSR net in module %s is %s.\n", module, log_signal(gsr));
for (auto cell : module->selected_cells())
{
if (cell->type != ID($_NOT_))

7
techlibs/lattice/synth_lattice.cc
View file

@ -402,8 +402,10 @@ struct SynthLatticePass : public ScriptPass
if (check_label("coarse"))
{
run("proc");
if (flatten || help_mode)
if (flatten || help_mode) {
run("check");
run("flatten");
}
run("tribuf -logic");
run("deminout");
run("opt_expr");
@ -423,9 +425,12 @@ struct SynthLatticePass : public ScriptPass
run("opt_clean");
if (help_mode) {
run("lattice_dsp_nexus", "(only if -family lifcl/lfd2nx and unless -nodsp)");
run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)");
run("techmap -map +/lattice/dsp_map" + dsp_map + ".v", "(unless -nodsp)");
} else if (have_dsp && !nodsp) {
if (is_nexus)
run("lattice_dsp_nexus");
for (const auto &rule : dsp_rules) {
run(stringf("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d -D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_NAME=%s",
rule.a_maxwidth, rule.b_maxwidth, rule.a_minwidth, rule.b_minwidth, rule.prim));

76
techlibs/microchip/CMakeLists.txt Normal file
View file

@ -0,0 +1,76 @@
pmgen_command(microchip_dsp
microchip_dsp.pmg
)
pmgen_command(microchip_dsp_cascade
microchip_dsp_cascade.pmg
)
pmgen_command(microchip_dsp_CREG
microchip_dsp_CREG.pmg
)
yosys_pass(microchip_dffopt
microchip_dffopt.cc
)
yosys_pass(microchip_dsp
microchip_dsp.cc
${PMGEN_microchip_dsp_OUTPUT}
${PMGEN_microchip_dsp_cascade_OUTPUT}
${PMGEN_microchip_dsp_CREG_OUTPUT}
)
yosys_pass(synth_microchip
synth_microchip.cc
REQUIRES
abc
alumacc
attrmap
blackbox
check
chtype
clean
clkbufmap
deminout
dfflegalize
extract_reduce
flatten
fsm
hierarchy
iopadmap
memory
memory_dff
memory_libmap
memory_map
microchip_dffopt
microchip_dsp
muxcover
opt
opt_clean
opt_expr
peepopt
proc
read_verilog
select
setattr
share
simplemap
stat
techmap
tribuf
wreduce
write_blif
write_edif
write_verilog
zinit
DATA_DIR
microchip
DATA_FILES
arith_map.v
cells_map.v
cells_sim.v
polarfire_dsp_map.v
brams_defs.vh
LSRAM_map.v
LSRAM.txt
uSRAM_map.v
uSRAM.txt
)

40
techlibs/microchip/Makefile.inc
View file

@ -1,40 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
OBJS += techlibs/microchip/synth_microchip.o
OBJS += techlibs/microchip/microchip_dffopt.o
$(eval $(call add_share_file,share/microchip,techlibs/microchip/arith_map.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_map.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_sim.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/polarfire_dsp_map.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/brams_defs.vh))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM_map.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM.txt))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM_map.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM.txt))
OBJS += techlibs/microchip/microchip_dsp.o
GENFILES += techlibs/microchip/microchip_dsp_pm.h
GENFILES += techlibs/microchip/microchip_dsp_CREG_pm.h
GENFILES += techlibs/microchip/microchip_dsp_cascade_pm.h
techlibs/microchip/microchip_dsp.o: techlibs/microchip/microchip_dsp_pm.h techlibs/microchip/microchip_dsp_CREG_pm.h techlibs/microchip/microchip_dsp_cascade_pm.h
$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_pm.h))
$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_CREG_pm.h))
$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_cascade_pm.h))

4
techlibs/microchip/microchip_dffopt.cc
View file

@ -121,7 +121,7 @@ struct MicrochipDffOptPass : public Pass {
extra_args(args, argidx, design);
for (auto module : design->selected_modules()) {
log("Optimizing FFs in %s.\n", log_id(module));
log("Optimizing FFs in %s.\n", module);
SigMap sigmap(module);
dict<SigBit, pair<LutData, Cell *>> bit_to_lut;
@ -294,7 +294,7 @@ struct MicrochipDffOptPass : public Pass {
ports += " + S";
if (worthy_post_ce)
ports += " + CE";
log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, log_id(cell), log_id(sig_Q.wire),
log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, cell, sig_Q.wire,
GetSize(lut_d.second), GetSize(final_lut.second));
// Okay, we're doing it. Unmap ports.

20
techlibs/microchip/microchip_dsp.cc
View file

@ -31,13 +31,13 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
{
auto &st = pm.st_microchip_dsp_pack;
log("Analysing %s.%s for Microchip MACC_PA packing.\n", log_id(pm.module), log_id(st.dsp));
log("Analysing %s.%s for Microchip MACC_PA packing.\n", pm.module, st.dsp);
Cell *cell = st.dsp;
// pack pre-adder
if (st.preAdderStatic) {
SigSpec &pasub = cell->connections_.at(ID(PASUB));
log(" static PASUB preadder %s (%s)\n", log_id(st.preAdderStatic), log_id(st.preAdderStatic->type));
log(" static PASUB preadder %s (%s)\n", st.preAdderStatic, st.preAdderStatic->type.unescape());
bool D_SIGNED = st.preAdderStatic->getParam(ID::B_SIGNED).as_bool();
bool B_SIGNED = st.preAdderStatic->getParam(ID::A_SIGNED).as_bool();
st.sigB.extend_u0(18, B_SIGNED);
@ -60,7 +60,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
}
// pack post-adder
if (st.postAdderStatic) {
log(" postadder %s (%s)\n", log_id(st.postAdderStatic), log_id(st.postAdderStatic->type));
log(" postadder %s (%s)\n", st.postAdderStatic, st.postAdderStatic->type.unescape());
SigSpec &sub = cell->connections_.at(ID(SUB));
// Post-adder in MACC_PA also supports subtraction
// Determines the sign of the output from the multiplier.
@ -171,13 +171,13 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
log(" clock: %s (%s)\n", log_signal(st.clock), "posedge");
if (st.ffA)
log(" \t ffA:%s\n", log_id(st.ffA));
log(" \t ffA:%s\n", st.ffA);
if (st.ffB)
log(" \t ffB:%s\n", log_id(st.ffB));
log(" \t ffB:%s\n", st.ffB);
if (st.ffD)
log(" \t ffD:%s\n", log_id(st.ffD));
log(" \t ffD:%s\n", st.ffD);
if (st.ffP)
log(" \t ffP:%s\n", log_id(st.ffP));
log(" \t ffP:%s\n", st.ffP);
}
log("\n");
@ -194,8 +194,8 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
{
auto &st = pm.st_microchip_dsp_packC;
log_debug("Analysing %s.%s for Microchip DSP packing (REG_C).\n", log_id(pm.module), log_id(st.dsp));
log_debug("ffC: %s\n", log_id(st.ffC, "--"));
log_debug("Analysing %s.%s for Microchip DSP packing (REG_C).\n", pm.module, st.dsp);
log_debug("ffC: %s\n", st.ffC ? st.ffC->name.unescape() : "--");
Cell *cell = st.dsp;
@ -264,7 +264,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), "posedge");
if (st.ffC)
log(" ffC:%s", log_id(st.ffC));
log(" ffC:%s", st.ffC);
log("\n");
}

4
techlibs/microchip/microchip_dsp_cascade.pmg
View file

@ -135,10 +135,10 @@ finally
}
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", dsp, dsp_pcin);
} else {
log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE);
log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", dsp, dsp_pcin, MAX_DSP_CASCADE);
}
dsp = dsp_pcin;

4
techlibs/microchip/synth_microchip.cc
View file

@ -267,8 +267,10 @@ struct SynthMicrochipPass : public ScriptPass {
if (check_label("prepare")) {
run("proc");
if (flatten || help_mode)
if (flatten || help_mode) {
run("check");
run("flatten", "(with '-flatten')");
}
if (active_design)
active_design->scratchpad_unset("tribuf.added_something");
run("tribuf -logic");

68
techlibs/nanoxplore/CMakeLists.txt Normal file
View file

@ -0,0 +1,68 @@
yosys_pass(nx_carry
nx_carry.cc
)
yosys_pass(synth_nanoxplore
synth_nanoxplore.cc
REQUIRES
abc
alumacc
autoname
blackbox
check
clean
deminout
dfflegalize
flatten
fsm
hierarchy
iopadmap
memory
memory_libmap
memory_map
nx_carry
opt
opt_clean
opt_expr
opt_merge
peepopt
proc
read_verilog
setundef
share
stat
techmap
tribuf
wreduce
write_json
DATA_DIR
nanoxplore
DATA_FILES
# Techmap
arith_map.v
brams_init.vh
brams_map.v
brams.txt
cells_bb.v
cells_bb_l.v
cells_bb_m.v
cells_bb_u.v
cells_map.v
cells_sim.v
cells_sim_l.v
cells_sim_m.v
cells_sim_u.v
cells_wrap.v
cells_wrap_l.v
cells_wrap_m.v
cells_wrap_u.v
io_map.v
latches_map.v
rf_init.vh
rf_rams_l.txt
rf_rams_m.txt
rf_rams_u.txt
rf_rams_map_l.v
rf_rams_map_m.v
rf_rams_map_u.v
)

31
techlibs/nanoxplore/Makefile.inc
View file

@ -1,31 +0,0 @@
OBJS += techlibs/nanoxplore/synth_nanoxplore.o
OBJS += techlibs/nanoxplore/nx_carry.o
# Techmap
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_init.vh))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_map.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams.txt))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_l.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_u.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_l.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_m.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_u.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/latches_map.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_init.vh))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_l.txt))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_m.txt))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_l.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_m.v))
$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_u.v))

4
techlibs/nanoxplore/synth_nanoxplore.cc
View file

@ -250,8 +250,10 @@ struct SynthNanoXplorePass : public ScriptPass
if (check_label("coarse"))
{
run("proc");
if (flatten || help_mode)
if (flatten || help_mode) {
run("check");
run("flatten", "(skip if -noflatten)");
}
run("tribuf -logic");
run("deminout");
run("opt_expr");

1
techlibs/quicklogic/.gitignore vendored
View file

@ -1 +0,0 @@
/*_pm.h

104
techlibs/quicklogic/CMakeLists.txt Normal file
View file

@ -0,0 +1,104 @@
yosys_pass(ql_bram_merge
ql_bram_merge.cc
)
yosys_pass(ql_bram_types
ql_bram_types.cc
)
pmgen_command(ql_dsp_macc
ql_dsp_macc.pmg
)
yosys_pass(ql_dsp_macc
ql_dsp_macc.cc
${PMGEN_ql_dsp_macc_OUTPUT}
)
yosys_pass(ql_dsp_simd
ql_dsp_simd.cc
)
yosys_pass(ql_dsp_io_regs
ql_dsp_io_regs.cc
)
yosys_pass(ql_ioff
ql_ioff.cc
)
add_custom_command(
DEPENDS qlf_k6n10f/generate_bram_types_sim.py
# yosys_pass(DATA_FILES) expects the files to be in the source directory
OUTPUT ${CMAKE_CURRENT_SOURCE_DIR}/qlf_k6n10f/bram_types_sim.v
COMMAND ${Python3_EXECUTABLE} qlf_k6n10f/generate_bram_types_sim.py qlf_k6n10f/bram_types_sim.v
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
VERBATIM
)
yosys_pass(synth_quicklogic
synth_quicklogic.cc
REQUIRES
abc9
alumacc
autoname
blackbox
check
chtype
clean
clkbufmap
deminout
dfflegalize
flatten
fsm
hierarchy
iopadmap
memory
memory_libmap
memory_map
muxcover
opt
opt_clean
opt_expr
opt_lut
peepopt
pmuxtree
proc
ql_bram_merge
ql_bram_types
ql_dsp_io_regs
ql_dsp_macc
ql_dsp_simd
ql_ioff
read_verilog
setundef
share
shregmap
stat
techmap
tribuf
wreduce
write_blif
write_verilog
DATA_DIR
quicklogic
DATA_FILES
common/cells_sim.v
pp3/ffs_map.v
pp3/lut_map.v
pp3/latches_map.v
pp3/cells_map.v
pp3/cells_sim.v
pp3/abc9_model.v
pp3/abc9_map.v
pp3/abc9_unmap.v
qlf_k6n10f/arith_map.v
qlf_k6n10f/libmap_brams.txt
qlf_k6n10f/libmap_brams_map.v
qlf_k6n10f/brams_map.v
qlf_k6n10f/brams_sim.v
qlf_k6n10f/bram_types_sim.v
qlf_k6n10f/cells_sim.v
qlf_k6n10f/ffs_map.v
qlf_k6n10f/dsp_sim.v
qlf_k6n10f/dsp_map.v
qlf_k6n10f/dsp_final_map.v
qlf_k6n10f/TDP18K_FIFO.v
qlf_k6n10f/ufifo_ctl.v
qlf_k6n10f/sram1024x18_mem.v
)

44
techlibs/quicklogic/Makefile.inc
View file

@ -1,44 +0,0 @@
techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v: techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py
$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $^ $@
OBJS += techlibs/quicklogic/synth_quicklogic.o
OBJS += techlibs/quicklogic/ql_bram_merge.o
OBJS += techlibs/quicklogic/ql_bram_types.o
OBJS += techlibs/quicklogic/ql_dsp_simd.o
OBJS += techlibs/quicklogic/ql_dsp_io_regs.o
OBJS += techlibs/quicklogic/ql_ioff.o
# --------------------------------------
OBJS += techlibs/quicklogic/ql_dsp_macc.o
GENFILES += techlibs/quicklogic/ql_dsp_macc_pm.h techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v
techlibs/quicklogic/ql_dsp_macc.o: techlibs/quicklogic/ql_dsp_macc_pm.h
$(eval $(call add_extra_objs,techlibs/quicklogic/ql_dsp_macc_pm.h))
# --------------------------------------
$(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/ffs_map.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/lut_map.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/latches_map.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_map.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_sim.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_model.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_map.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_unmap.v))
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/arith_map.v))
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt))
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v))
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_map.v))
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v))
$(eval $(call add_gen_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v))
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v))
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v))
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_sim.v))
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_map.v))
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v))
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v))
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v))
$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v))

6
techlibs/quicklogic/ql_bram_merge.cc
View file

@ -128,7 +128,7 @@ struct QlBramMergeWorker {
// Create the new cell
RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type);
log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name));
log_debug("Merging split BRAM cells %s and %s -> %s\n", bram1->name.unescape(), bram2->name.unescape(), merged->name.unescape());
for (auto &it : param_map(false))
{
@ -146,14 +146,14 @@ struct QlBramMergeWorker {
if (bram1->hasPort(it.first))
merged->setPort(it.second, bram1->getPort(it.first));
else
log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name));
log_error("Can't find port %s on cell %s!\n", it.first.unescape(), bram1->name.unescape());
}
for (auto &it : port_map(true))
{
if (bram2->hasPort(it.first))
merged->setPort(it.second, bram2->getPort(it.first));
else
log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name));
log_error("Can't find port %s on cell %s!\n", it.first.unescape(), bram2->name.unescape());
}
merged->attributes = bram1->attributes;
for (auto attr: bram2->attributes)

2
techlibs/quicklogic/ql_bram_types.cc
View file

@ -155,7 +155,7 @@ struct QlBramTypesPass : public Pass {
}
cell->type = RTLIL::escape_id(type);
log_debug("Changed type of memory cell %s to %s\n", log_id(cell->name), log_id(cell->type));
log_debug("Changed type of memory cell %s to %s\n", cell->name.unescape(), cell->type.unescape());
}
}

6
techlibs/quicklogic/ql_dsp_io_regs.cc
View file

@ -83,19 +83,19 @@ struct QlDspIORegs : public Pass {
for (auto cfg_port : {ID(register_inputs), ID(output_select)})
if (!cell->hasPort(cfg_port) || !sigmap(cell->getPort(cfg_port)).is_fully_const())
log_error("Missing or non-constant '%s' port on DSP cell %s\n",
log_id(cfg_port), log_id(cell));
cfg_port, cell);
int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int();
int out_sel_i = sigmap(cell->getPort(ID(output_select))).as_int();
// Get the feedback port
if (!cell->hasPort(ID(feedback)))
log_error("Missing 'feedback' port on %s", log_id(cell));
log_error("Missing 'feedback' port on %s", cell);
SigSpec feedback = sigmap(cell->getPort(ID(feedback)));
// Check the top two bits on 'feedback' to be constant zero.
// That's what we are expecting from inference.
if (feedback.extract(1, 2) != SigSpec(0, 2))
log_error("Unexpected feedback configuration on %s\n", log_id(cell));
log_error("Unexpected feedback configuration on %s\n", cell);
// Build new type name
std::string new_type = "\\QL_DSP2_MULT";

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