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Merge remote-tracking branch 'upstream/main' into silimate

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This commit is contained in:
Mohamed Gaber 2026-06-09 16:22:51 +03:00
commit e58125b605
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834 changed files with 25281 additions and 8780 deletions
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1
passes/opt/.gitignore vendored
View file

@ -1 +0,0 @@
/peepopt*_pm.h

97
passes/opt/CMakeLists.txt Normal file
View file

@ -0,0 +1,97 @@
add_subdirectory(opt_clean)
yosys_pass(opt_merge
opt_merge.cc
)
yosys_pass(opt_mem_widen
opt_mem_widen.cc
)
yosys_pass(opt_muxtree
opt_muxtree.cc
)
yosys_pass(opt_reduce
opt_reduce.cc
)
yosys_pass(opt_dff
opt_dff.cc
REQUIRES
simplemap
)
yosys_pass(opt_share
opt_share.cc
)
yosys_pass(opt_expr
opt_expr.cc
)
yosys_pass(opt_hier
opt_hier.cc
)
yosys_pass(opt
opt.cc
REQUIRES
opt_clean
opt_dff
opt_expr
opt_hier
opt_merge
opt_muxtree
opt_reduce
opt_share
)
yosys_pass(opt_mem
opt_mem.cc
)
yosys_pass(opt_mem_feedback
opt_mem_feedback.cc
)
yosys_pass(opt_mem_priority
opt_mem_priority.cc
)
yosys_pass(share
share.cc
)
yosys_pass(wreduce
wreduce.cc
)
yosys_pass(opt_demorgan
opt_demorgan.cc
)
yosys_pass(rmports
rmports.cc
)
yosys_pass(opt_lut
opt_lut.cc
)
yosys_pass(opt_lut_ins
opt_lut_ins.cc
)
yosys_pass(opt_ffinv
opt_ffinv.cc
)
yosys_pass(pmux2shiftx
pmux2shiftx.cc
)
yosys_pass(muxpack
muxpack.cc
)
yosys_pass(opt_balance_tree
opt_balance_tree.cc
)
pmgen_command(peepopt
peepopt_shiftmul_right.pmg
peepopt_shiftmul_left.pmg
peepopt_shiftadd.pmg
peepopt_shiftpow2.pmg
peepopt_muldiv.pmg
peepopt_muldiv_c.pmg
peepopt_formal_clockgateff.pmg
PREFIX
peepopt
)
yosys_pass(peepopt
peepopt.cc
${PMGEN_peepopt_OUTPUT}
)

50
passes/opt/Makefile.inc
View file

@ -1,50 +0,0 @@
OBJS += passes/opt/opt.o
OBJS += passes/opt/opt_merge.o
OBJS += passes/opt/opt_mem.o
OBJS += passes/opt/opt_mem_feedback.o
OBJS += passes/opt/opt_mem_priority.o
OBJS += passes/opt/opt_mem_widen.o
OBJS += passes/opt/opt_muxtree.o
OBJS += passes/opt/opt_reduce.o
OBJS += passes/opt/opt_dff.o
OBJS += passes/opt/opt_share.o
OBJS += passes/opt/opt_clean.o
OBJS += passes/opt/opt_expr.o
OBJS += passes/opt/opt_hier.o
OBJS += passes/opt/share.o
OBJS += passes/opt/wreduce.o
OBJS += passes/opt/opt_demorgan.o
OBJS += passes/opt/rmports.o
OBJS += passes/opt/opt_lut.o
OBJS += passes/opt/opt_lut_ins.o
OBJS += passes/opt/opt_ffinv.o
OBJS += passes/opt/pmux2shiftx.o
OBJS += passes/opt/muxpack.o
OBJS += passes/opt/opt_addcin.o
OBJS += passes/opt/opt_andor_pmux.o
OBJS += passes/opt/opt_argmax.o
OBJS += passes/opt/opt_balance_tree.o
OBJS += passes/opt/opt_parallel_prefix.o
OBJS += passes/opt/opt_prienc.o
OBJS += passes/opt/peepopt.o
GENFILES += passes/opt/peepopt_pm.h
passes/opt/peepopt.o: passes/opt/peepopt_pm.h
$(eval $(call add_extra_objs,passes/opt/peepopt_pm.h))
PEEPOPT_PATTERN = passes/opt/peepopt_shiftmul_right.pmg
PEEPOPT_PATTERN += passes/opt/peepopt_shiftmul_left.pmg
PEEPOPT_PATTERN += passes/opt/peepopt_shiftadd.pmg
PEEPOPT_PATTERN += passes/opt/peepopt_muldiv.pmg
PEEPOPT_PATTERN += passes/opt/peepopt_muldiv_c.pmg
PEEPOPT_PATTERN += passes/opt/peepopt_modshr_onehot.pmg
PEEPOPT_PATTERN += passes/opt/peepopt_addsub_c.pmg
PEEPOPT_PATTERN += passes/opt/peepopt_muxorder.pmg
PEEPOPT_PATTERN += passes/opt/peepopt_formal_clockgateff.pmg
PEEPOPT_PATTERN += passes/opt/peepopt_sub_neg.pmg
passes/opt/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^)

20
passes/opt/muxpack.cc
View file

@ -38,6 +38,9 @@ struct ExclusiveDatabase
pool<Cell*> reduce_or;
for (auto cell : module->cells()) {
if (cell->type == ID($eq)) {
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
if (GetSize(y_sig) == 0)
continue;
nonconst_sig = sigmap(cell->getPort(ID::A));
const_sig = sigmap(cell->getPort(ID::B));
if (!const_sig.is_fully_const()) {
@ -45,12 +48,15 @@ struct ExclusiveDatabase
continue;
std::swap(nonconst_sig, const_sig);
}
y_port = sigmap(cell->getPort(ID::Y));
y_port = y_sig[0];
}
else if (cell->type == ID($logic_not)) {
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
if (GetSize(y_sig) == 0)
continue;
nonconst_sig = sigmap(cell->getPort(ID::A));
const_sig = Const(State::S0, GetSize(nonconst_sig));
y_port = sigmap(cell->getPort(ID::Y));
y_port = y_sig[0];
}
else if (cell->type == ID($reduce_or)) {
reduce_or.insert(cell);
@ -84,7 +90,10 @@ struct ExclusiveDatabase
}
if (nonconst_sig.empty())
continue;
y_port = sigmap(cell->getPort(ID::Y));
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
if (GetSize(y_sig) == 0)
continue;
y_port = y_sig[0];
sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,std::move(values));
}
}
@ -184,7 +193,7 @@ struct MuxpackWorker
{
for (auto cell : candidate_cells)
{
log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
log_debug("Considering %s (%s)\n", cell, cell->type.unescape());
SigSpec a_sig = sigmap(cell->getPort(ID::A));
if (cell->type == ID($mux)) {
@ -254,7 +263,6 @@ struct MuxpackWorker
int cases = GetSize(chain) - cursor;
Cell *first_cell = chain[cursor];
dict<int, SigBit> taps_dict;
if (cases < 2) {
cursor++;
@ -264,7 +272,7 @@ struct MuxpackWorker
Cell *last_cell = chain[cursor+cases-1];
log("Converting %s.%s ... %s.%s to a pmux with %d cases.\n",
log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), cases);
module, first_cell, module, last_cell, cases);
mux_count += cases;
pmux_count += 1;

36
passes/opt/opt_balance_tree.cc
View file

@ -105,15 +105,15 @@ struct OptBalanceTreeWorker {
// Base case: if we have only one source, return it
if (sources.size() == 1)
return sources[0];
// Base case: if we have two sources, create a single cell
if (sources.size() == 2) {
// Create a new cell of the same type
Cell* new_cell = module->addCell(NEW_ID2_SUFFIX("tree"), cell_type);
// Copy attributes from reference cell
new_cell->attributes = cell->attributes;
// Create output wire
int out_width = cell->getParam(ID::Y_WIDTH).as_int();
if (cell_type == ID($add))
@ -121,7 +121,7 @@ struct OptBalanceTreeWorker {
else if (cell_type == ID($mul))
out_width = sources[0].size() + sources[1].size();
Wire* out_wire = module->addWire(NEW_ID2_SUFFIX("tree_out"), out_width);
// Connect ports and fix up parameters
new_cell->setPort(ID::A, sources[0]);
new_cell->setPort(ID::B, sources[1]);
@ -129,26 +129,26 @@ struct OptBalanceTreeWorker {
new_cell->fixup_parameters();
new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
// Update count and return output wire
cell_count[cell_type]++;
return out_wire;
}
// Recursive case: split sources into two groups and create subtrees
int mid = (sources.size() + 1) / 2;
vector<SigSpec> left_sources(sources.begin(), sources.begin() + mid);
vector<SigSpec> right_sources(sources.begin() + mid, sources.end());
SigSpec left_tree = create_balanced_tree(left_sources, cell_type, cell);
SigSpec right_tree = create_balanced_tree(right_sources, cell_type, cell);
// Create a cell to combine the two subtrees
Cell* new_cell = module->addCell(NEW_ID2_SUFFIX("tree"), cell_type);
// Copy attributes from reference cell
new_cell->attributes = cell->attributes;
// Create output wire
int out_width = cell->getParam(ID::Y_WIDTH).as_int();
if (cell_type == ID($add))
@ -156,7 +156,7 @@ struct OptBalanceTreeWorker {
else if (cell_type == ID($mul))
out_width = left_tree.size() + right_tree.size();
Wire* out_wire = module->addWire(NEW_ID2_SUFFIX("tree_out"), out_width);
// Connect ports and fix up parameters
new_cell->setPort(ID::A, left_tree);
new_cell->setPort(ID::B, right_tree);
@ -164,7 +164,7 @@ struct OptBalanceTreeWorker {
new_cell->fixup_parameters();
new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
// Update count and return output wire
cell_count[cell_type]++;
return out_wire;
@ -512,8 +512,8 @@ struct OptBalanceTreeWorker {
if (inner_cells)
{
// Create a tree
log_debug(" Creating tree for %s with %d sources and %d inner cells...\n", log_id(head_cell), GetSize(sources), inner_cells);
log_debug(" Creating tree for %s with %d sources and %d inner cells...\n", head_cell, GetSize(sources), inner_cells);
// Build a vector of all source signals
vector<SigSpec> source_signals;
vector<bool> signed_flags;
@ -528,10 +528,10 @@ struct OptBalanceTreeWorker {
if (!std::all_of(signed_flags.begin(), signed_flags.end(), [&](bool flag) { return flag == signed_flags[0]; })) {
continue;
}
// Create the balanced tree
SigSpec tree_output = create_balanced_tree(source_signals, cell_type, head_cell);
// Connect the tree output to the head cell's output
SigSpec head_output = sigmap(head_cell->getPort(ID::Y));
int connect_width = std::min(head_output.size(), tree_output.size());
@ -546,7 +546,7 @@ struct OptBalanceTreeWorker {
}
}
}
// Remove all consumed cells, which now have been replaced by trees
for (auto cell : consumed_cells)
module->remove(cell);
@ -604,7 +604,7 @@ struct OptBalanceTreePass : public Pass {
// Log stats
for (auto cell_type : cell_types)
log("Converted %d %s cells into trees.\n", cell_count[cell_type], log_id(cell_type));
log("Converted %d %s cells into trees.\n", cell_count[cell_type], cell_type.unescape());
if (std::find(cell_types.begin(), cell_types.end(), ID($add)) != cell_types.end())
log("Converted %d sliced $add chains into trees.\n", sliced_add_count);

800
passes/opt/opt_clean.cc
View file

@ -1,800 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/sigtools.h"
#include "kernel/log.h"
#include "kernel/celltypes.h"
#include "kernel/ffinit.h"
#include <stdlib.h>
#include <stdio.h>
#include <set>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
using RTLIL::id2cstr;
struct keep_cache_t
{
Design *design;
dict<Module*, bool> cache;
bool purge_mode = false;
void reset(Design *design = nullptr, bool purge_mode = false)
{
this->design = design;
this->purge_mode = purge_mode;
cache.clear();
}
bool query(Module *module)
{
log_assert(design != nullptr);
if (module == nullptr)
return false;
if (cache.count(module))
return cache.at(module);
cache[module] = true;
if (!module->get_bool_attribute(ID::keep)) {
bool found_keep = false;
for (auto cell : module->cells())
if (query(cell, true /* ignore_specify */)) {
found_keep = true;
break;
}
for (auto wire : module->wires())
if (wire->get_bool_attribute(ID::keep)) {
found_keep = true;
break;
}
cache[module] = found_keep;
}
return cache[module];
}
bool query(Cell *cell, bool ignore_specify = false)
{
if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
return true;
if (cell->type.in(ID($overwrite_tag)))
return true;
if (!ignore_specify && cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
return true;
if (cell->type == ID($print) || cell->type == ID($check))
return true;
if (cell->has_keep_attr())
return true;
if (!purge_mode && cell->type == ID($scopeinfo))
return true;
if (cell->module && cell->module->design)
return query(cell->module->design->module(cell->type));
return false;
}
};
keep_cache_t keep_cache;
CellTypes ct_reg, ct_all;
int count_rm_cells, count_rm_wires;
void rmunused_module_cells(Module *module, bool verbose)
{
SigMap sigmap(module);
dict<IdString, pool<Cell*>> mem2cells;
pool<IdString> mem_unused;
pool<Cell*> queue, unused;
pool<SigBit> used_raw_bits;
dict<SigBit, pool<Cell*>> wire2driver;
dict<SigBit, vector<string>> driver_driver_logs;
FfInitVals ffinit(&sigmap, module);
SigMap raw_sigmap;
for (auto &it : module->connections_) {
for (int i = 0; i < GetSize(it.second); i++) {
if (it.second[i].wire != nullptr)
raw_sigmap.add(it.first[i], it.second[i]);
}
}
for (auto &it : module->memories) {
mem_unused.insert(it.first);
}
for (Cell *cell : module->cells()) {
if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2))) {
IdString mem_id = cell->getParam(ID::MEMID).decode_string();
mem2cells[mem_id].insert(cell);
}
}
for (auto &it : module->cells_) {
Cell *cell = it.second;
for (auto &it2 : cell->connections()) {
if (ct_all.cell_known(cell->type) && !ct_all.cell_output(cell->type, it2.first))
continue;
for (auto raw_bit : it2.second) {
if (raw_bit.wire == nullptr)
continue;
auto bit = sigmap(raw_bit);
if (bit.wire == nullptr && ct_all.cell_known(cell->type))
driver_driver_logs[raw_sigmap(raw_bit)].push_back(stringf("Driver-driver conflict "
"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
log_signal(raw_bit), log_id(cell), log_id(it2.first), log_signal(bit), log_id(module)));
if (bit.wire != nullptr)
wire2driver[bit].insert(cell);
}
}
if (keep_cache.query(cell))
queue.insert(cell);
else
unused.insert(cell);
}
for (auto &it : module->wires_) {
Wire *wire = it.second;
if (wire->port_output || wire->get_bool_attribute(ID::keep)) {
for (auto bit : sigmap(wire))
for (auto c : wire2driver[bit])
queue.insert(c), unused.erase(c);
for (auto raw_bit : SigSpec(wire))
used_raw_bits.insert(raw_sigmap(raw_bit));
}
}
while (!queue.empty())
{
pool<SigBit> bits;
pool<IdString> mems;
for (auto cell : queue) {
for (auto &it : cell->connections())
if (!ct_all.cell_known(cell->type) || ct_all.cell_input(cell->type, it.first))
for (auto bit : sigmap(it.second))
bits.insert(bit);
if (cell->type.in(ID($memrd), ID($memrd_v2))) {
IdString mem_id = cell->getParam(ID::MEMID).decode_string();
if (mem_unused.count(mem_id)) {
mem_unused.erase(mem_id);
mems.insert(mem_id);
}
}
}
queue.clear();
for (auto bit : bits)
for (auto c : wire2driver[bit])
if (unused.count(c))
queue.insert(c), unused.erase(c);
for (auto mem : mems)
for (auto c : mem2cells[mem])
if (unused.count(c))
queue.insert(c), unused.erase(c);
}
unused.sort(RTLIL::sort_by_name_id<RTLIL::Cell>());
for (auto cell : unused) {
if (verbose)
log_debug(" removing unused `%s' cell `%s'.\n", cell->type, cell->name);
module->design->scratchpad_set_bool("opt.did_something", true);
if (cell->is_builtin_ff())
ffinit.remove_init(cell->getPort(ID::Q));
module->remove(cell);
count_rm_cells++;
}
for (auto it : mem_unused)
{
if (verbose)
log_debug(" removing unused memory `%s'.\n", it);
delete module->memories.at(it);
module->memories.erase(it);
}
for (auto &it : module->cells_) {
Cell *cell = it.second;
for (auto &it2 : cell->connections()) {
if (ct_all.cell_known(cell->type) && !ct_all.cell_input(cell->type, it2.first))
continue;
for (auto raw_bit : raw_sigmap(it2.second))
used_raw_bits.insert(raw_bit);
}
}
for (auto it : driver_driver_logs) {
if (used_raw_bits.count(it.first))
for (auto msg : it.second)
log_warning("%s\n", msg);
}
}
int count_nontrivial_wire_attrs(RTLIL::Wire *w)
{
int count = w->attributes.size();
count -= w->attributes.count(ID::src);
count -= w->attributes.count(ID::hdlname);
count -= w->attributes.count(ID(scopename));
count -= w->attributes.count(ID::unused_bits);
return count;
}
// Should we pick `s2` over `s1` to represent a signal?
bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPool &conns, pool<RTLIL::Wire*> &direct_wires)
{
RTLIL::Wire *w1 = s1.wire;
RTLIL::Wire *w2 = s2.wire;
if (w1 == NULL || w2 == NULL)
return w2 == NULL;
if (w1->port_input != w2->port_input)
return w2->port_input;
if ((w1->port_input && w1->port_output) != (w2->port_input && w2->port_output))
return !(w2->port_input && w2->port_output);
if (w1->name.isPublic() && w2->name.isPublic()) {
if (regs.check(s1) != regs.check(s2))
return regs.check(s2);
if (direct_wires.count(w1) != direct_wires.count(w2))
return direct_wires.count(w2) != 0;
if (conns.check_any(s1) != conns.check_any(s2))
return conns.check_any(s2);
}
if (w1->port_output != w2->port_output)
return w2->port_output;
if (w1->name[0] != w2->name[0])
return w2->name.isPublic();
int attrs1 = count_nontrivial_wire_attrs(w1);
int attrs2 = count_nontrivial_wire_attrs(w2);
if (attrs1 != attrs2)
return attrs2 > attrs1;
return w2->name.lt_by_name(w1->name);
}
bool check_public_name(RTLIL::IdString id)
{
if (id.begins_with("$"))
return false;
const std::string &id_str = id.str();
if (id.begins_with("\\_") && (id.ends_with("_") || id_str.find("_[") != std::string::npos))
return false;
if (id_str.find(".$") != std::string::npos)
return false;
return true;
}
bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool unusedbitsattr_mode, bool verbose)
{
// `register_signals` and `connected_signals` will help us decide later on
// on picking representatives out of groups of connected signals
SigPool register_signals;
SigPool connected_signals;
if (!purge_mode)
for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
if (ct_reg.cell_known(cell->type)) {
bool clk2fflogic = cell->get_bool_attribute(ID(clk2fflogic));
for (auto &it2 : cell->connections())
if (clk2fflogic ? it2.first == ID::D : ct_reg.cell_output(cell->type, it2.first))
register_signals.add(it2.second);
}
for (auto &it2 : cell->connections())
connected_signals.add(it2.second);
}
SigMap assign_map(module);
// construct a pool of wires which are directly driven by a known celltype,
// this will influence our choice of representatives
pool<RTLIL::Wire*> direct_wires;
{
pool<RTLIL::SigSpec> direct_sigs;
for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
if (ct_all.cell_known(cell->type))
for (auto &it2 : cell->connections())
if (ct_all.cell_output(cell->type, it2.first))
direct_sigs.insert(assign_map(it2.second));
}
for (auto &it : module->wires_) {
if (direct_sigs.count(assign_map(it.second)) || it.second->port_input)
direct_wires.insert(it.second);
}
}
// weight all options for representatives with `compare_signals`,
// the one that wins will be what `assign_map` maps to
for (auto &it : module->wires_) {
RTLIL::Wire *wire = it.second;
for (int i = 0; i < wire->width; i++) {
RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1);
if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires))
assign_map.add(s1);
}
}
// we are removing all connections
module->connections_.clear();
// used signals sigmapped
SigPool used_signals;
// used signals pre-sigmapped
SigPool raw_used_signals;
// used signals sigmapped, ignoring drivers (we keep track of this to set `unused_bits`)
SigPool used_signals_nodrivers;
// gather the usage information for cells
for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
for (auto &it2 : cell->connections_) {
assign_map.apply(it2.second); // modify the cell connection in place
raw_used_signals.add(it2.second);
used_signals.add(it2.second);
if (!ct_all.cell_output(cell->type, it2.first))
used_signals_nodrivers.add(it2.second);
}
}
// gather the usage information for ports, wires with `keep`,
// also gather init bits
dict<RTLIL::SigBit, RTLIL::State> init_bits;
for (auto &it : module->wires_) {
RTLIL::Wire *wire = it.second;
if (wire->port_id > 0) {
RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
raw_used_signals.add(sig);
assign_map.apply(sig);
used_signals.add(sig);
if (!wire->port_input)
used_signals_nodrivers.add(sig);
}
if (wire->get_bool_attribute(ID::keep)) {
RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
assign_map.apply(sig);
used_signals.add(sig);
}
auto it2 = wire->attributes.find(ID::init);
if (it2 != wire->attributes.end()) {
RTLIL::Const &val = it2->second;
SigSpec sig = assign_map(wire);
for (int i = 0; i < GetSize(val) && i < GetSize(sig); i++)
if (val[i] != State::Sx)
init_bits[sig[i]] = val[i];
wire->attributes.erase(it2);
}
}
// set init attributes on all wires of a connected group
for (auto wire : module->wires()) {
bool found = false;
Const val(State::Sx, wire->width);
for (int i = 0; i < wire->width; i++) {
auto it = init_bits.find(RTLIL::SigBit(wire, i));
if (it != init_bits.end()) {
val.set(i, it->second);
found = true;
}
}
if (found)
wire->attributes[ID::init] = val;
}
// now decide for each wire if we should be deleting it
pool<RTLIL::Wire*> del_wires_queue;
for (auto wire : module->wires())
{
SigSpec s1 = SigSpec(wire), s2 = assign_map(s1);
log_assert(GetSize(s1) == GetSize(s2));
Const initval;
if (wire->attributes.count(ID::init))
initval = wire->attributes.at(ID::init);
if (GetSize(initval) != GetSize(wire))
initval.resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef())
wire->attributes.erase(ID::init);
if (GetSize(wire) == 0) {
// delete zero-width wires, unless they are module ports
if (wire->port_id == 0)
goto delete_this_wire;
} else
if (wire->port_id != 0 || wire->get_bool_attribute(ID::keep) || !initval.is_fully_undef()) {
// do not delete anything with "keep" or module ports or initialized wires
} else
if (!purge_mode && check_public_name(wire->name) && (raw_used_signals.check_any(s1) || used_signals.check_any(s2) || s1 != s2)) {
// do not get rid of public names unless in purge mode or if the wire is entirely unused, not even aliased
} else
if (!raw_used_signals.check_any(s1)) {
// delete wires that aren't used by anything directly
goto delete_this_wire;
}
if (0)
{
delete_this_wire:
del_wires_queue.insert(wire);
}
else
{
RTLIL::SigSig new_conn;
for (int i = 0; i < GetSize(s1); i++)
if (s1[i] != s2[i]) {
if (s2[i] == State::Sx && (initval[i] == State::S0 || initval[i] == State::S1)) {
s2[i] = initval[i];
initval.set(i, State::Sx);
}
new_conn.first.append(s1[i]);
new_conn.second.append(s2[i]);
}
if (new_conn.first.size() > 0) {
if (initval.is_fully_undef())
wire->attributes.erase(ID::init);
else
wire->attributes.at(ID::init) = initval;
module->connect(new_conn);
}
if (!used_signals_nodrivers.check_all(s2)) {
std::string unused_bits;
for (int i = 0; i < GetSize(s2); i++) {
if (s2[i].wire == NULL)
continue;
if (!used_signals_nodrivers.check(s2[i])) {
if (!unused_bits.empty())
unused_bits += " ";
unused_bits += stringf("%d", i);
}
}
if (unused_bits.empty() || wire->port_id != 0)
wire->attributes.erase(ID::unused_bits);
else if (unusedbitsattr_mode)
wire->attributes[ID::unused_bits] = RTLIL::Const(unused_bits);
} else {
wire->attributes.erase(ID::unused_bits);
}
}
}
int del_temp_wires_count = 0;
for (auto wire : del_wires_queue) {
if (ys_debug() || (check_public_name(wire->name) && verbose))
log_debug(" removing unused non-port wire %s.\n", wire->name);
else
del_temp_wires_count++;
}
module->remove(del_wires_queue);
count_rm_wires += GetSize(del_wires_queue);
if (verbose && del_temp_wires_count)
log_debug(" removed %d unused temporary wires.\n", del_temp_wires_count);
if (!del_wires_queue.empty())
module->design->scratchpad_set_bool("opt.did_something", true);
return !del_wires_queue.empty();
}
bool rmunused_module_init(RTLIL::Module *module, bool verbose)
{
bool did_something = false;
CellTypes fftypes;
fftypes.setup_internals_mem();
SigMap sigmap(module);
dict<SigBit, State> qbits;
for (auto cell : module->cells())
if (fftypes.cell_known(cell->type) && cell->hasPort(ID::Q))
{
SigSpec sig = cell->getPort(ID::Q);
for (int i = 0; i < GetSize(sig); i++)
{
SigBit bit = sig[i];
if (bit.wire == nullptr || bit.wire->attributes.count(ID::init) == 0)
continue;
Const init = bit.wire->attributes.at(ID::init);
if (i >= GetSize(init) || init[i] == State::Sx || init[i] == State::Sz)
continue;
sigmap.add(bit);
qbits[bit] = init[i];
}
}
for (auto wire : module->wires())
{
if (wire->attributes.count(ID::init) == 0)
continue;
Const init = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(wire) && i < GetSize(init); i++)
{
if (init[i] == State::Sx || init[i] == State::Sz)
continue;
SigBit wire_bit = SigBit(wire, i);
SigBit mapped_wire_bit = sigmap(wire_bit);
if (wire_bit == mapped_wire_bit)
goto next_wire;
if (mapped_wire_bit.wire) {
if (qbits.count(mapped_wire_bit) == 0)
goto next_wire;
if (qbits.at(mapped_wire_bit) != init[i])
goto next_wire;
}
else {
if (mapped_wire_bit == State::Sx || mapped_wire_bit == State::Sz)
goto next_wire;
if (mapped_wire_bit != init[i]) {
log_warning("Initial value conflict for %s resolving to %s but with init %s.\n", log_signal(wire_bit), log_signal(mapped_wire_bit), log_signal(init[i]));
goto next_wire;
}
}
}
if (verbose)
log_debug(" removing redundant init attribute on %s.\n", log_id(wire));
wire->attributes.erase(ID::init);
did_something = true;
next_wire:;
}
if (did_something)
module->design->scratchpad_set_bool("opt.did_something", true);
return did_something;
}
void rmunused_module(RTLIL::Module *module, bool purge_mode, bool unusedbitsattr_mode, bool verbose, bool rminit)
{
if (verbose)
log("Finding unused cells or wires in module %s..\n", module->name);
std::vector<RTLIL::Cell*> delcells;
for (auto cell : module->cells()) {
if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
a.extend_u0(GetSize(y), is_signed);
if (a.has_const(State::Sz)) {
SigSpec new_a;
SigSpec new_y;
for (int i = 0; i < GetSize(a); ++i) {
SigBit b = a[i];
if (b == State::Sz)
continue;
new_a.append(b);
new_y.append(y[i]);
}
a = std::move(new_a);
y = std::move(new_y);
}
if (!y.empty())
module->connect(y, a);
delcells.push_back(cell);
} else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) {
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec b = cell->getPort(ID::B);
if (a.has_const() && !b.has_const())
std::swap(a, b);
module->connect(a, b);
delcells.push_back(cell);
} else if (cell->type.in(ID($input_port)) && !cell->has_keep_attr()) {
delcells.push_back(cell);
}
}
for (auto cell : delcells) {
if (verbose) {
if (cell->type == ID($connect))
log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name,
log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
else if (cell->type == ID($input_port))
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::Y)));
else
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
}
module->remove(cell);
}
if (!delcells.empty())
module->design->scratchpad_set_bool("opt.did_something", true);
rmunused_module_cells(module, verbose);
while (rmunused_module_signals(module, purge_mode, unusedbitsattr_mode, verbose)) { }
if (rminit && rmunused_module_init(module, verbose))
while (rmunused_module_signals(module, purge_mode, unusedbitsattr_mode, verbose)) { }
}
struct OptCleanPass : public Pass {
OptCleanPass() : Pass("opt_clean", "remove unused cells and wires") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" opt_clean [options] [selection]\n");
log("\n");
log("This pass identifies wires and cells that are unused and removes them. Other\n");
log("passes often remove cells but leave the wires in the design or reconnect the\n");
log("wires but leave the old cells in the design. This pass can be used to clean up\n");
log("after the passes that do the actual work.\n");
log("\n");
log("This pass only operates on completely selected modules without processes.\n");
log("\n");
log(" -purge\n");
log(" also remove internal nets if they have a public name\n");
log("\n");
log(" -unusedbitsattr\n");
log(" add an unused_bits attribute onto wires for bits that are not used\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool purge_mode = false;
bool unusedbitsattr_mode = false;
log_header(design, "Executing OPT_CLEAN pass (remove unused cells and wires).\n");
log_push();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-purge") {
purge_mode = true;
continue;
}
if (args[argidx] == "-unusedbitsattr") {
unusedbitsattr_mode = true;
continue;
}
break;
}
extra_args(args, argidx, design);
keep_cache.reset(design, purge_mode);
ct_reg.setup_internals_mem();
ct_reg.setup_internals_anyinit();
ct_reg.setup_stdcells_mem();
ct_all.setup(design);
count_rm_cells = 0;
count_rm_wires = 0;
for (auto module : design->selected_whole_modules_warn()) {
if (module->has_processes_warn())
continue;
rmunused_module(module, purge_mode, unusedbitsattr_mode, true, true);
}
if (count_rm_cells > 0 || count_rm_wires > 0)
log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
design->optimize();
design->sort();
design->check();
keep_cache.reset();
ct_reg.clear();
ct_all.clear();
log_pop();
request_garbage_collection();
}
} OptCleanPass;
struct CleanPass : public Pass {
CleanPass() : Pass("clean", "remove unused cells and wires") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" clean [options] [selection]\n");
log("\n");
log("This is identical to 'opt_clean', but less verbose.\n");
log("\n");
log("When commands are separated using the ';;' token, this command will be executed\n");
log("between the commands.\n");
log("\n");
log("When commands are separated using the ';;;' token, this command will be executed\n");
log("in -purge mode between the commands.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool purge_mode = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-purge") {
purge_mode = true;
continue;
}
break;
}
extra_args(args, argidx, design);
keep_cache.reset(design);
ct_reg.setup_internals_mem();
ct_reg.setup_internals_anyinit();
ct_reg.setup_stdcells_mem();
ct_all.setup(design);
count_rm_cells = 0;
count_rm_wires = 0;
for (auto module : design->selected_unboxed_whole_modules()) {
if (module->has_processes())
continue;
rmunused_module(module, purge_mode, false, ys_debug(), true);
}
log_suppressed();
if (count_rm_cells > 0 || count_rm_wires > 0)
log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
design->optimize();
design->sort();
design->check();
keep_cache.reset();
ct_reg.clear();
ct_all.clear();
request_garbage_collection();
}
} CleanPass;
PRIVATE_NAMESPACE_END

11
passes/opt/opt_clean/CMakeLists.txt Normal file
View file

@ -0,0 +1,11 @@
yosys_pass(opt_clean
cells_all.cc
cells_temp.cc
wires.cc
inits.cc
opt_clean.cc
opt_clean.h
keep_cache.h
PROVIDES
clean
)

373
passes/opt/opt_clean/cells_all.cc Normal file
View file

@ -0,0 +1,373 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/ffinit.h"
#include "kernel/yosys_common.h"
#include "passes/opt/opt_clean/opt_clean.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
unsigned int hash_bit(const SigBit &bit) {
return static_cast<unsigned int>(hash_ops<SigBit>::hash(bit).yield());
}
SigMap wire_sigmap(const RTLIL::Module* mod) {
SigMap map;
for (auto &it : mod->connections_) {
for (int i = 0; i < GetSize(it.second); i++) {
if (it.second[i].wire != nullptr)
map.add(it.first[i], it.second[i]);
}
}
return map;
}
struct WireDrivers;
// Maps from a SigBit to a unique driver cell.
struct WireDriver {
using Accumulated = WireDrivers;
SigBit bit;
int driver_cell;
};
// Maps from a SigBit to one or more driver cells.
struct WireDrivers {
WireDrivers() : driver_cell(0) {}
WireDrivers(WireDriver driver) : bit(driver.bit), driver_cell(driver.driver_cell) {}
WireDrivers(SigBit bit) : bit(bit), driver_cell(0) {}
WireDrivers(WireDrivers &&other) = default;
class const_iterator {
public:
const_iterator(const WireDrivers &drivers, bool end)
: driver_cell(drivers.driver_cell), in_extra_cells(end) {
if (drivers.extra_driver_cells) {
if (end) {
extra_it = drivers.extra_driver_cells->end();
} else {
extra_it = drivers.extra_driver_cells->begin();
}
}
}
int operator*() const {
if (in_extra_cells)
return **extra_it;
return driver_cell;
}
const_iterator& operator++() {
if (in_extra_cells)
++*extra_it;
else
in_extra_cells = true;
return *this;
}
bool operator!=(const const_iterator &other) const {
return !(*this == other);
}
bool operator==(const const_iterator &other) const {
return in_extra_cells == other.in_extra_cells &&
extra_it == other.extra_it;
}
private:
std::optional<pool<int>::iterator> extra_it;
int driver_cell;
bool in_extra_cells;
};
const_iterator begin() const { return const_iterator(*this, false); }
const_iterator end() const { return const_iterator(*this, true); }
SigBit bit;
int driver_cell;
std::unique_ptr<pool<int>> extra_driver_cells;
};
struct WireDriversKeyEquality {
bool operator()(const WireDrivers &a, const WireDrivers &b) const {
return a.bit == b.bit;
}
};
struct WireDriversCollisionHandler {
void operator()(WireDrivers &incumbent, WireDrivers &new_value) const {
log_assert(new_value.extra_driver_cells == nullptr);
if (!incumbent.extra_driver_cells)
incumbent.extra_driver_cells.reset(new pool<int>());
incumbent.extra_driver_cells->insert(new_value.driver_cell);
}
};
using Wire2Drivers = ShardedHashtable<WireDriver, WireDriversKeyEquality, WireDriversCollisionHandler>;
struct ConflictLogs {
ShardedVector<std::pair<SigBit, std::string>> logs;
ConflictLogs(ParallelDispatchThreadPool::Subpool &subpool) : logs(subpool) {}
void print_warnings(pool<SigBit>& used_raw_bits, const SigMap& wire_map, const RTLIL::Module* mod, CleanRunContext &clean_ctx) {
if (!logs.empty()) {
// We could do this in parallel but hopefully this is rare.
for (auto [_, cell] : mod->cells_) {
for (auto &[port, sig] : cell->connections()) {
if (clean_ctx.ct_all.cell_known(cell->type) && !clean_ctx.ct_all.cell_input(cell->type, port))
continue;
for (auto raw_bit : wire_map(sig))
used_raw_bits.insert(raw_bit);
}
}
for (std::pair<SigBit, std::string> &it : logs) {
if (used_raw_bits.count(it.first))
log_warning("%s\n", it.second);
}
}
}
};
struct CellTraversal {
ConcurrentWorkQueue<int> queue;
Wire2Drivers wire2driver;
dict<std::string, pool<int>> mem2cells;
CellTraversal(int num_threads) : queue(num_threads), wire2driver(), mem2cells() {}
};
struct CellAnalysis {
ShardedVector<Wire*> keep_wires;
std::vector<std::atomic<bool>> unused;
CellAnalysis(AnalysisContext& actx)
: keep_wires(actx.subpool), unused(actx.mod->cells_size()) {}
pool<SigBit> analyze_kept_wires(CellTraversal& traversal, const SigMap& sigmap, const SigMap& wire_map, int num_threads) {
// Also enqueue cells that drive kept wires into cell_queue
// and mark those cells as used
// and mark all bits of those wires as used
pool<SigBit> used_raw_bits;
int i = 0;
for (Wire *wire : keep_wires) {
for (auto bit : sigmap(wire)) {
const WireDrivers *drivers = traversal.wire2driver.find({{bit}, hash_bit(bit)});
if (drivers != nullptr)
for (int cell_index : *drivers)
if (unused[cell_index].exchange(false, std::memory_order_relaxed)) {
ThreadIndex fake_thread_index = {i++ % num_threads};
traversal.queue.push(fake_thread_index, cell_index);
}
}
for (auto raw_bit : SigSpec(wire))
used_raw_bits.insert(wire_map(raw_bit));
}
return used_raw_bits;
}
void mark_used_and_enqueue(int cell_idx, ConcurrentWorkQueue<int>& queue, const ParallelDispatchThreadPool::RunCtx &ctx) {
if (unused[cell_idx].exchange(false, std::memory_order_relaxed))
queue.push(ctx, cell_idx);
}
};
ConflictLogs explore(CellAnalysis& analysis, CellTraversal& traversal, const SigMap& wire_map, AnalysisContext& actx, CleanRunContext &clean_ctx) {
ConflictLogs logs(actx.subpool);
Wire2Drivers::Builder wire2driver_builder(actx.subpool);
ShardedVector<std::pair<std::string, int>> mem2cells_vector(actx.subpool);
// Enqueue kept cells into traversal.queue
// Prepare input cone traversal into traversal.wire2driver
// Prepare "input cone" traversal from memory to write port or meminit as analysis.mem2cells
// Also check driver conflicts
// Also mark cells unused to true unless keep (we override this later)
actx.subpool.run([&analysis, &traversal, &logs, &wire_map, &mem2cells_vector, &wire2driver_builder, &actx, &clean_ctx](const ParallelDispatchThreadPool::RunCtx &ctx) {
for (int i : ctx.item_range(actx.mod->cells_size())) {
Cell *cell = actx.mod->cell_at(i);
if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2)))
mem2cells_vector.insert(ctx, {cell->getParam(ID::MEMID).decode_string(), i});
for (auto &it2 : cell->connections()) {
if (clean_ctx.ct_all.cell_known(cell->type) && !clean_ctx.ct_all.cell_output(cell->type, it2.first))
continue;
for (auto raw_bit : it2.second) {
if (raw_bit.wire == nullptr)
continue;
auto bit = actx.assign_map(raw_bit);
if (bit.wire == nullptr && clean_ctx.ct_all.cell_known(cell->type)) {
std::string msg = stringf("Driver-driver conflict "
"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
log_signal(raw_bit), cell->name.unescape(), it2.first.unescape(), log_signal(bit), actx.mod->name.unescape());
logs.logs.insert(ctx, {wire_map(raw_bit), msg});
}
if (bit.wire != nullptr)
wire2driver_builder.insert(ctx, {{bit, i}, hash_bit(bit)});
}
}
bool keep = clean_ctx.keep_cache.query(cell);
analysis.unused[i].store(!keep, std::memory_order_relaxed);
if (keep)
traversal.queue.push(ctx, i);
}
for (int i : ctx.item_range(actx.mod->wires_size())) {
Wire *wire = actx.mod->wire_at(i);
if (wire->port_output || wire->get_bool_attribute(ID::keep))
analysis.keep_wires.insert(ctx, wire);
}
});
// Finish by merging per-thread collected data
actx.subpool.run([&wire2driver_builder](const ParallelDispatchThreadPool::RunCtx &ctx) {
wire2driver_builder.process(ctx);
});
traversal.wire2driver = wire2driver_builder;
for (std::pair<std::string, int> &mem2cell : mem2cells_vector)
traversal.mem2cells[mem2cell.first].insert(mem2cell.second);
return logs;
}
struct MemAnalysis {
std::vector<std::atomic<bool>> unused;
dict<std::string, int> indices;
MemAnalysis(const RTLIL::Module* mod) : unused(mod->memories.size()), indices() {
for (int i = 0; i < GetSize(mod->memories); ++i) {
indices[mod->memories.element(i)->first.str()] = i;
unused[i].store(true, std::memory_order_relaxed);
}
}
};
void fixup_unused_cells_and_mems(CellAnalysis& analysis, MemAnalysis& mem_analysis, CellTraversal& traversal, AnalysisContext& actx, CleanRunContext &clean_ctx) {
// Processes the cell queue in batches, traversing input cones by enqueuing more cells
// Discover and mark used memories and cells
actx.subpool.run([&analysis, &mem_analysis, &traversal, &actx, &clean_ctx](const ParallelDispatchThreadPool::RunCtx &ctx) {
pool<SigBit> bits;
pool<std::string> mems;
while (true) {
std::vector<int> cell_indices = traversal.queue.pop_batch(ctx);
if (cell_indices.empty())
return;
for (auto cell_index : cell_indices) {
Cell *cell = actx.mod->cell_at(cell_index);
for (auto &it : cell->connections())
if (!clean_ctx.ct_all.cell_known(cell->type) || clean_ctx.ct_all.cell_input(cell->type, it.first))
for (auto bit : actx.assign_map(it.second))
bits.insert(bit);
if (cell->type.in(ID($memrd), ID($memrd_v2))) {
std::string mem_id = cell->getParam(ID::MEMID).decode_string();
if (mem_analysis.indices.count(mem_id)) {
int mem_index = mem_analysis.indices[mem_id];
// Memory fixup
if (mem_analysis.unused[mem_index].exchange(false, std::memory_order_relaxed))
mems.insert(mem_id);
}
}
}
for (auto bit : bits) {
// Cells fixup
const WireDrivers *drivers = traversal.wire2driver.find({{bit}, hash_bit(bit)});
if (drivers != nullptr)
for (int cell_idx : *drivers)
analysis.mark_used_and_enqueue(cell_idx, traversal.queue, ctx);
}
bits.clear();
for (auto mem : mems) {
if (traversal.mem2cells.count(mem) == 0)
continue;
// Cells fixup
for (int cell_idx : traversal.mem2cells.at(mem))
analysis.mark_used_and_enqueue(cell_idx, traversal.queue, ctx);
}
mems.clear();
}
});
}
pool<Cell*> all_unused_cells(const Module *mod, const CellAnalysis& analysis, Wire2Drivers& wire2driver, ParallelDispatchThreadPool::Subpool &subpool) {
pool<Cell*> unused_cells;
ShardedVector<int> sharded_unused_cells(subpool);
subpool.run([mod, &analysis, &wire2driver, &sharded_unused_cells](const ParallelDispatchThreadPool::RunCtx &ctx) {
// Parallel destruction of `wire2driver`
wire2driver.clear(ctx);
for (int i : ctx.item_range(mod->cells_size()))
if (analysis.unused[i].load(std::memory_order_relaxed))
sharded_unused_cells.insert(ctx, i);
});
for (int cell_index : sharded_unused_cells)
unused_cells.insert(mod->cell_at(cell_index));
unused_cells.sort(RTLIL::sort_by_name_id<RTLIL::Cell>());
return unused_cells;
}
void remove_cells(RTLIL::Module* mod, FfInitVals& ffinit, const pool<Cell*>& cells, bool verbose, RmStats& stats) {
for (auto cell : cells) {
if (verbose)
log_debug(" removing unused `%s' cell `%s'.\n", cell->type, cell->name);
mod->design->scratchpad_set_bool("opt.did_something", true);
if (cell->is_builtin_ff())
ffinit.remove_init(cell->getPort(ID::Q));
mod->remove(cell);
stats.count_rm_cells++;
}
}
void remove_mems(RTLIL::Module* mod, const MemAnalysis& mem_analysis, bool verbose) {
for (const auto &it : mem_analysis.indices) {
if (!mem_analysis.unused[it.second].load(std::memory_order_relaxed))
continue;
RTLIL::IdString id(it.first);
if (verbose)
log_debug(" removing unused memory `%s'.\n", id.unescape());
delete mod->memories.at(id);
mod->memories.erase(id);
}
}
PRIVATE_NAMESPACE_END
YOSYS_NAMESPACE_BEGIN
void rmunused_module_cells(Module *module, ParallelDispatchThreadPool::Subpool &subpool, CleanRunContext &clean_ctx)
{
AnalysisContext actx(module, subpool);
// Used for logging warnings only
SigMap wire_map = wire_sigmap(module);
CellAnalysis analysis(actx);
CellTraversal traversal(subpool.num_threads());
// Mark all unkept cells as unused initially
// and queue up cell traversal from those cells
auto logs = explore(analysis, traversal, wire_map, actx, clean_ctx);
// Mark cells that drive kept wires into cell_queue and those bits as used
// and queue up cell traversal from those cells
pool<SigBit> used_raw_bits = analysis.analyze_kept_wires(traversal, actx.assign_map, wire_map, subpool.num_threads());
// Mark all memories as unused initially
MemAnalysis mem_analysis(module);
// Marked all used cells and mems as used by traversing with cell queue
fixup_unused_cells_and_mems(analysis, mem_analysis, traversal, actx, clean_ctx);
// Analyses are now fully correct
// unused_cells.contains(foo) iff analysis.used[foo] == true
// wire2driver is passed in only to destroy it
pool<Cell*> unused_cells = all_unused_cells(module, analysis, traversal.wire2driver, subpool);
FfInitVals ffinit;
ffinit.set_parallel(&actx.assign_map, subpool.thread_pool(), module);
// Now we know what to kill
remove_cells(module, ffinit, unused_cells, clean_ctx.flags.verbose, clean_ctx.stats);
remove_mems(module, mem_analysis, clean_ctx.flags.verbose);
logs.print_warnings(used_raw_bits, wire_map, module, clean_ctx);
}
YOSYS_NAMESPACE_END

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "passes/opt/opt_clean/opt_clean.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
bool is_signed(RTLIL::Cell* cell) {
return cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
}
bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections, const ParallelDispatchThreadPool::RunCtx &ctx) {
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
a.extend_u0(GetSize(y), is_signed(cell));
if (a.has_const(State::Sz)) {
RTLIL::SigSpec new_a;
RTLIL::SigSpec new_y;
for (int i = 0; i < GetSize(a); ++i) {
RTLIL::SigBit b = a[i];
if (b == State::Sz)
return false;
new_a.append(b);
new_y.append(y[i]);
}
a = std::move(new_a);
y = std::move(new_y);
}
if (!y.empty())
new_connections.insert(ctx, {y, a});
return true;
}
bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose) {
bool did_something = false;
for (RTLIL::Cell *cell : cells) {
if (verbose) {
if (cell->type == ID($connect))
log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name,
log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
else if (cell->type == ID($input_port))
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::Y)));
else
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
}
mod->remove(cell);
did_something = true;
}
return did_something;
}
PRIVATE_NAMESPACE_END
YOSYS_NAMESPACE_BEGIN
void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose)
{
ShardedVector<RTLIL::Cell*> delcells(subpool);
ShardedVector<RTLIL::SigSig> new_connections(subpool);
const RTLIL::Module *const_module = module;
subpool.run([const_module, &delcells, &new_connections](const ParallelDispatchThreadPool::RunCtx &ctx) {
for (int i : ctx.item_range(const_module->cells_size())) {
RTLIL::Cell *cell = const_module->cell_at(i);
if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
if (trim_buf(cell, new_connections, ctx))
delcells.insert(ctx, cell);
} else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) {
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec b = cell->getPort(ID::B);
if (a.has_const() && !b.has_const())
std::swap(a, b);
new_connections.insert(ctx, {a, b});
delcells.insert(ctx, cell);
} else if (cell->type.in(ID($input_port)) && !cell->has_keep_attr()) {
delcells.insert(ctx, cell);
}
}
});
for (RTLIL::SigSig &connection : new_connections) {
module->connect(connection);
}
if (remove(delcells, module, verbose))
module->design->scratchpad_set_bool("opt.did_something", true);
}
YOSYS_NAMESPACE_END

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "passes/opt/opt_clean/opt_clean.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
ShardedVector<std::pair<SigBit, State>> build_inits(AnalysisContext& actx) {
ShardedVector<std::pair<SigBit, State>> results(actx.subpool);
actx.subpool.run([&results, &actx](const ParallelDispatchThreadPool::RunCtx &ctx) {
for (int i : ctx.item_range(actx.mod->cells_size())) {
RTLIL::Cell *cell = actx.mod->cell_at(i);
if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(ID::Q))
{
SigSpec sig = cell->getPort(ID::Q);
for (int i = 0; i < GetSize(sig); i++)
{
SigBit bit = sig[i];
if (bit.wire == nullptr || bit.wire->attributes.count(ID::init) == 0)
continue;
Const init = bit.wire->attributes.at(ID::init);
if (i >= GetSize(init) || init[i] == State::Sx || init[i] == State::Sz)
continue;
results.insert(ctx, {bit, init[i]});
}
}
}
});
return results;
}
dict<SigBit, State> qbits_from_inits(ShardedVector<std::pair<SigBit, State>>& inits, SigMap& assign_map) {
dict<SigBit, State> qbits;
for (std::pair<SigBit, State> &p : inits) {
assign_map.add(p.first);
qbits[p.first] = p.second;
}
return qbits;
}
ShardedVector<RTLIL::Wire*> deferred_init_transfer(const dict<SigBit, State>& qbits, AnalysisContext& actx) {
ShardedVector<RTLIL::Wire*> wire_results(actx.subpool);
actx.subpool.run([&actx, &qbits, &wire_results](const ParallelDispatchThreadPool::RunCtx &ctx) {
for (int j : ctx.item_range(actx.mod->wires_size())) {
RTLIL::Wire *wire = actx.mod->wire_at(j);
if (wire->attributes.count(ID::init) == 0)
continue;
Const init = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(wire) && i < GetSize(init); i++)
{
if (init[i] == State::Sx || init[i] == State::Sz)
continue;
SigBit wire_bit = SigBit(wire, i);
SigBit mapped_wire_bit = actx.assign_map(wire_bit);
if (wire_bit == mapped_wire_bit)
goto next_wire;
if (mapped_wire_bit.wire) {
if (qbits.count(mapped_wire_bit) == 0)
goto next_wire;
if (qbits.at(mapped_wire_bit) != init[i])
goto next_wire;
}
else {
if (mapped_wire_bit == State::Sx || mapped_wire_bit == State::Sz)
goto next_wire;
if (mapped_wire_bit != init[i]) {
log_warning("Initial value conflict for %s resolving to %s but with init %s.\n", log_signal(wire_bit), log_signal(mapped_wire_bit), log_signal(init[i]));
goto next_wire;
}
}
}
wire_results.insert(ctx, wire);
next_wire:;
}
});
return wire_results;
}
bool remove_redundant_inits(ShardedVector<RTLIL::Wire*> wires, bool verbose) {
bool did_something = false;
for (RTLIL::Wire *wire : wires) {
if (verbose)
log_debug(" removing redundant init attribute on %s.\n", wire);
wire->attributes.erase(ID::init);
did_something = true;
}
return did_something;
}
PRIVATE_NAMESPACE_END
YOSYS_NAMESPACE_BEGIN
bool rmunused_module_init(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose)
{
AnalysisContext actx(module, subpool);
ShardedVector<std::pair<SigBit, State>> inits = build_inits(actx);
dict<SigBit, State> qbits = qbits_from_inits(inits, actx.assign_map);
ShardedVector<RTLIL::Wire*> inits_to_transfer = deferred_init_transfer(qbits, actx);
bool did_something = remove_redundant_inits(inits_to_transfer, verbose);
if (did_something)
module->design->scratchpad_set_bool("opt.did_something", true);
return did_something;
}
YOSYS_NAMESPACE_END

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/rtlil.h"
#include "kernel/sigtools.h"
#include "kernel/threading.h"
#include "kernel/celltypes.h"
#include "kernel/yosys_common.h"
#ifndef OPT_CLEAN_KEEP_CACHE_H
#define OPT_CLEAN_KEEP_CACHE_H
YOSYS_NAMESPACE_BEGIN
struct KeepCache
{
dict<Module*, bool> keep_modules;
bool purge_mode;
KeepCache(bool purge_mode, ParallelDispatchThreadPool &thread_pool, const std::vector<RTLIL::Module *> &selected_modules)
: purge_mode(purge_mode) {
std::vector<RTLIL::Module *> scan_modules_worklist;
dict<RTLIL::Module *, std::vector<RTLIL::Module*>> dependents;
std::vector<RTLIL::Module *> propagate_kept_modules_worklist;
for (RTLIL::Module *module : selected_modules) {
if (keep_modules.count(module))
continue;
bool keep = scan_module(module, thread_pool, dependents, ALL_CELLS, scan_modules_worklist);
keep_modules[module] = keep;
if (keep)
propagate_kept_modules_worklist.push_back(module);
}
while (!scan_modules_worklist.empty()) {
RTLIL::Module *module = scan_modules_worklist.back();
scan_modules_worklist.pop_back();
if (keep_modules.count(module))
continue;
bool keep = scan_module(module, thread_pool, dependents, MINIMUM_CELLS, scan_modules_worklist);
keep_modules[module] = keep;
if (keep)
propagate_kept_modules_worklist.push_back(module);
}
while (!propagate_kept_modules_worklist.empty()) {
RTLIL::Module *module = propagate_kept_modules_worklist.back();
propagate_kept_modules_worklist.pop_back();
for (RTLIL::Module *dependent : dependents[module]) {
if (keep_modules[dependent])
continue;
keep_modules[dependent] = true;
propagate_kept_modules_worklist.push_back(dependent);
}
}
}
bool query(Cell *cell) const
{
if (keep_cell(cell, purge_mode))
return true;
if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
return true;
if (cell->module && cell->module->design) {
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
return cell_module != nullptr && keep_modules.at(cell_module);
}
return false;
}
private:
enum ScanCells {
// Scan every cell to see if it uses a module that is kept.
ALL_CELLS,
// Stop scanning cells if we determine early that this module is kept.
MINIMUM_CELLS,
};
bool scan_module(Module *module, ParallelDispatchThreadPool &thread_pool, dict<RTLIL::Module *, std::vector<RTLIL::Module*>> &dependents,
ScanCells scan_cells, std::vector<Module*> &worklist) const
{
MonotonicFlag keep_module;
if (module->get_bool_attribute(ID::keep)) {
if (scan_cells == MINIMUM_CELLS)
return true;
keep_module.set();
}
ParallelDispatchThreadPool::Subpool subpool(thread_pool, ThreadPool::work_pool_size(0, module->cells_size(), 1000));
ShardedVector<Module*> deps(subpool);
const RTLIL::Module *const_module = module;
bool purge_mode = this->purge_mode;
subpool.run([purge_mode, const_module, scan_cells, &deps, &keep_module](const ParallelDispatchThreadPool::RunCtx &ctx) {
bool keep = false;
for (int i : ctx.item_range(const_module->cells_size())) {
Cell *cell = const_module->cell_at(i);
if (keep_cell(cell, purge_mode)) {
if (scan_cells == MINIMUM_CELLS) {
keep_module.set();
return;
}
keep = true;
}
if (const_module->design) {
RTLIL::Module *cell_module = const_module->design->module(cell->type);
if (cell_module != nullptr)
deps.insert(ctx, cell_module);
}
}
if (keep) {
keep_module.set();
return;
}
for (int i : ctx.item_range(const_module->wires_size())) {
Wire *wire = const_module->wire_at(i);
if (wire->get_bool_attribute(ID::keep)) {
keep_module.set();
return;
}
}
});
if (scan_cells == MINIMUM_CELLS && keep_module.load())
return true;
for (Module *dep : deps) {
dependents[dep].push_back(module);
worklist.push_back(dep);
}
return keep_module.load();
}
static bool keep_cell(Cell *cell, bool purge_mode)
{
if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
return true;
if (cell->type.in(ID($overwrite_tag)))
return true;
if (cell->type == ID($print) || cell->type == ID($check))
return true;
if (cell->has_keep_attr())
return true;
if (!purge_mode && cell->type == ID($scopeinfo))
return true;
return false;
}
};
YOSYS_NAMESPACE_END
#endif /* OPT_CLEAN_KEEP_CACHE_H */

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/log.h"
#include "kernel/log_help.h"
#include "passes/opt/opt_clean/opt_clean.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
void rmunused_module(RTLIL::Module *module, bool rminit, CleanRunContext &clean_ctx)
{
if (clean_ctx.flags.verbose)
log("Finding unused cells or wires in module %s..\n", module->name);
// Use no more than one worker per thousand cells, rounded down, so
// we only start multithreading with at least 2000 cells.
int num_worker_threads = ThreadPool::work_pool_size(0, module->cells_size(), 10000);
ParallelDispatchThreadPool::Subpool subpool(clean_ctx.thread_pool, num_worker_threads);
remove_temporary_cells(module, subpool, clean_ctx.flags.verbose);
rmunused_module_cells(module, subpool, clean_ctx);
while (rmunused_module_signals(module, subpool, clean_ctx)) { }
if (rminit && rmunused_module_init(module, subpool, clean_ctx.flags.verbose))
while (rmunused_module_signals(module, subpool, clean_ctx)) { }
}
struct OptCleanPass : public Pass {
OptCleanPass() : Pass("opt_clean", "remove unused cells and wires") { }
bool formatted_help() override
{
auto *help = PrettyHelp::get_current();
help->set_group("passes/opt");
return false;
}
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" opt_clean [options] [selection]\n");
log("\n");
log("This pass identifies wires and cells that are unused and removes them. Other\n");
log("passes often remove cells but leave the wires in the design or reconnect the\n");
log("wires but leave the old cells in the design. This pass can be used to clean up\n");
log("after the passes that do the actual work.\n");
log("\n");
log("This pass only operates on completely selected modules without processes.\n");
log("\n");
log(" -purge\n");
log(" also remove internal nets if they have a public name\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool purge_mode = false;
log_header(design, "Executing OPT_CLEAN pass (remove unused cells and wires).\n");
log_push();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-purge") {
purge_mode = true;
continue;
}
break;
}
extra_args(args, argidx, design);
{
std::vector<RTLIL::Module*> selected_modules;
for (auto module : design->selected_whole_modules_warn())
if (!module->has_processes_warn())
selected_modules.push_back(module);
CleanRunContext clean_ctx(design, selected_modules, {purge_mode, true});
for (auto module : selected_modules)
rmunused_module(module, true, clean_ctx);
clean_ctx.stats.log();
design->optimize();
design->check();
}
log_pop();
request_garbage_collection();
}
} OptCleanPass;
struct CleanPass : public Pass {
CleanPass() : Pass("clean", "remove unused cells and wires") { }
bool formatted_help() override
{
auto *help = PrettyHelp::get_current();
help->set_group("passes/opt");
return false;
}
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" clean [options] [selection]\n");
log("\n");
log("This is identical to 'opt_clean', but less verbose.\n");
log("\n");
log("When commands are separated using the ';;' token, this command will be executed\n");
log("between the commands.\n");
log("\n");
log("When commands are separated using the ';;;' token, this command will be executed\n");
log("in -purge mode between the commands.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool purge_mode = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-purge") {
purge_mode = true;
continue;
}
break;
}
extra_args(args, argidx, design);
{
std::vector<RTLIL::Module*> selected_modules;
for (auto module : design->selected_unboxed_whole_modules())
if (!module->has_processes())
selected_modules.push_back(module);
CleanRunContext clean_ctx(design, selected_modules, {purge_mode, ys_debug()});
for (auto module : selected_modules)
rmunused_module(module, true, clean_ctx);
log_suppressed();
clean_ctx.stats.log();
design->optimize();
design->check();
}
request_garbage_collection();
}
} CleanPass;
PRIVATE_NAMESPACE_END

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/rtlil.h"
#include "kernel/threading.h"
#include "passes/opt/opt_clean/keep_cache.h"
#ifndef OPT_CLEAN_SHARED_H
#define OPT_CLEAN_SHARED_H
YOSYS_NAMESPACE_BEGIN
struct AnalysisContext {
SigMap assign_map;
const RTLIL::Module *mod;
ParallelDispatchThreadPool::Subpool &subpool;
AnalysisContext(RTLIL::Module* m, ParallelDispatchThreadPool::Subpool &p) : assign_map(m), mod(m), subpool(p) {}
};
struct RmStats {
int count_rm_cells = 0;
int count_rm_wires = 0;
void log()
{
if (count_rm_cells > 0 || count_rm_wires > 0)
YOSYS_NAMESPACE_PREFIX log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
}
};
struct Flags {
bool purge = false;
bool verbose = false;
};
struct CleanRunContext {
static constexpr auto ct_reg = StaticCellTypes::Categories::join(
StaticCellTypes::Compat::mem_ff,
StaticCellTypes::categories.is_anyinit);
NewCellTypes ct_all;
RmStats stats;
ParallelDispatchThreadPool thread_pool;
KeepCache keep_cache;
Flags flags;
private:
// Helper to compute thread pool size
static int compute_thread_pool_size(const std::vector<RTLIL::Module*>& selected_modules) {
int thread_pool_size = 0;
for (auto module : selected_modules)
thread_pool_size = std::max(thread_pool_size,
ThreadPool::work_pool_size(0, module->cells_size(), 10000));
return thread_pool_size;
}
public:
CleanRunContext(RTLIL::Design* design, const std::vector<RTLIL::Module*>& selected_modules, Flags f)
: thread_pool(compute_thread_pool_size(selected_modules)),
keep_cache(f.purge, thread_pool, selected_modules),
flags(f)
{
ct_all.setup(design);
}
~CleanRunContext() {
ct_all.clear();
}
};
void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose);
void rmunused_module_cells(Module *module, ParallelDispatchThreadPool::Subpool &subpool, CleanRunContext &clean_ctx);
bool rmunused_module_signals(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, CleanRunContext &clean_ctx);
bool rmunused_module_init(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose);
YOSYS_NAMESPACE_END
#endif /* OPT_CLEAN_SHARED_H */

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "passes/opt/opt_clean/opt_clean.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
// No collision handler for these, since we will use them such that collisions don't happen
struct ShardedSigBit {
using Accumulated = ShardedSigBit;
RTLIL::SigBit bit;
ShardedSigBit() = default;
ShardedSigBit(const RTLIL::SigBit &bit) : bit(bit) {}
};
struct ShardedSigBitEquality {
bool operator()(const ShardedSigBit &b1, const ShardedSigBit &b2) const {
return b1.bit == b2.bit;
}
};
using ShardedSigPool = ShardedHashtable<ShardedSigBit, ShardedSigBitEquality, SetCollisionHandler<ShardedSigBit>>;
struct ShardedSigSpec {
using Accumulated = ShardedSigSpec;
RTLIL::SigSpec spec;
ShardedSigSpec() = default;
ShardedSigSpec(RTLIL::SigSpec spec) : spec(std::move(spec)) {}
ShardedSigSpec(ShardedSigSpec &&) = default;
};
struct ShardedSigSpecEquality {
bool operator()(const ShardedSigSpec &s1, const ShardedSigSpec &s2) const {
return s1.spec == s2.spec;
}
};
using ShardedSigSpecPool = ShardedHashtable<ShardedSigSpec, ShardedSigSpecEquality, SetCollisionHandler<ShardedSigSpec>>;
struct ExactCellWires {
const ShardedSigSpecPool &exact_cells;
const SigMap &assign_map;
dict<RTLIL::Wire *, bool> cache;
ExactCellWires(const ShardedSigSpecPool &exact_cells, const SigMap &assign_map) : exact_cells(exact_cells), assign_map(assign_map) {}
void cache_result_for_bit(const SigBit &bit) {
if (bit.wire != nullptr)
(void)is_exactly_cell_driven(bit.wire);
}
bool is_exactly_cell_driven(RTLIL::Wire *wire) {
if (wire->port_input)
return true;
auto it = cache.find(wire);
if (it != cache.end())
return it->second;
SigSpec sig = assign_map(wire);
bool direct = exact_cells.find({sig, sig.hash_into(Hasher()).yield()}) != nullptr;
cache.insert({wire, direct});
return direct;
}
void cache_all(ShardedVector<RTLIL::SigBit> &bits) {
for (RTLIL::SigBit candidate : bits) {
cache_result_for_bit(candidate);
cache_result_for_bit(assign_map(candidate));
}
}
};
int count_nontrivial_wire_attrs(RTLIL::Wire *w)
{
int count = w->attributes.size();
count -= w->attributes.count(ID::src);
count -= w->attributes.count(ID::hdlname);
count -= w->attributes.count(ID::scopename);
count -= w->attributes.count(ID::unused_bits);
return count;
}
// Should we pick `s2` over `s1` to represent a signal?
bool compare_signals(const RTLIL::SigBit &s1, const RTLIL::SigBit &s2, const ShardedSigPool &regs, const ShardedSigPool &conns, ExactCellWires &cell_wires)
{
if (s1 == s2)
return false;
RTLIL::Wire *w1 = s1.wire;
RTLIL::Wire *w2 = s2.wire;
if (w1 == NULL || w2 == NULL)
return w2 == NULL;
if (w1->port_input != w2->port_input)
return w2->port_input;
if ((w1->port_input && w1->port_output) != (w2->port_input && w2->port_output))
return !(w2->port_input && w2->port_output);
if (w1->name.isPublic() && w2->name.isPublic()) {
ShardedSigPool::AccumulatedValue s1_val = {s1, s1.hash_top().yield()};
ShardedSigPool::AccumulatedValue s2_val = {s2, s2.hash_top().yield()};
bool regs1 = regs.find(s1_val) != nullptr;
bool regs2 = regs.find(s2_val) != nullptr;
if (regs1 != regs2)
return regs2;
bool w1_exact = cell_wires.is_exactly_cell_driven(w1);
bool w2_exact = cell_wires.is_exactly_cell_driven(w2);
if (w1_exact != w2_exact)
return w2_exact;
bool conns1 = conns.find(s1_val) != nullptr;
bool conns2 = conns.find(s2_val) != nullptr;
if (conns1 != conns2)
return conns2;
}
if (w1 == w2)
return s2.offset < s1.offset;
if (w1->port_output != w2->port_output)
return w2->port_output;
if (w1->name[0] != w2->name[0])
return w2->name.isPublic();
int attrs1 = count_nontrivial_wire_attrs(w1);
int attrs2 = count_nontrivial_wire_attrs(w2);
if (attrs1 != attrs2)
return attrs2 > attrs1;
return w2->name.lt_by_name(w1->name);
}
bool check_public_name(RTLIL::IdString id)
{
if (id.begins_with("$"))
return false;
const std::string &id_str = id.str();
if (id.begins_with("\\_") && (id.ends_with("_") || id_str.find("_[") != std::string::npos))
return false;
if (id_str.find(".$") != std::string::npos)
return false;
return true;
}
void add_spec(ShardedSigPool::Builder &builder, const ThreadIndex &thread, const RTLIL::SigSpec &spec) {
for (SigBit bit : spec)
if (bit.wire != nullptr)
builder.insert(thread, {bit, bit.hash_top().yield()});
}
bool check_any(const ShardedSigPool &sigs, const RTLIL::SigSpec &spec) {
for (SigBit b : spec)
if (sigs.find({b, b.hash_top().yield()}) != nullptr)
return true;
return false;
}
bool check_all(const ShardedSigPool &sigs, const RTLIL::SigSpec &spec) {
for (SigBit b : spec)
if (sigs.find({b, b.hash_top().yield()}) == nullptr)
return false;
return true;
}
struct UpdateConnection {
RTLIL::Cell *cell;
RTLIL::IdString port;
RTLIL::SigSpec spec;
};
void fixup_cell_ports(ShardedVector<UpdateConnection> &update_connections)
{
for (UpdateConnection &update : update_connections)
update.cell->connections_.at(update.port) = std::move(update.spec);
}
struct InitBits {
dict<SigBit, RTLIL::State> values;
// Wires that appear in the keys of the `values` dict
pool<Wire*> wires;
// Set init attributes on all wires of a connected group
void apply_normalised_inits() {
for (RTLIL::Wire *wire : wires) {
bool found = false;
Const val(State::Sx, wire->width);
for (int i = 0; i < wire->width; i++) {
auto it = values.find(RTLIL::SigBit(wire, i));
if (it != values.end()) {
val.set(i, it->second);
found = true;
}
}
if (found)
wire->attributes[ID::init] = val;
}
}
};
static InitBits consume_inits(ShardedVector<RTLIL::Wire*> &initialized_wires, const SigMap &assign_map)
{
InitBits init_bits;
for (RTLIL::Wire *initialized_wire : initialized_wires) {
auto it = initialized_wire->attributes.find(ID::init);
RTLIL::Const &val = it->second;
SigSpec sig = assign_map(initialized_wire);
for (int i = 0; i < GetSize(val) && i < GetSize(sig); i++)
if (val[i] != State::Sx && sig[i].wire != nullptr) {
init_bits.values[sig[i]] = val[i];
init_bits.wires.insert(sig[i].wire);
}
initialized_wire->attributes.erase(it);
}
return init_bits;
}
/**
* What kinds of things are signals connected to?
* Helps pick representatives out of groups of connected signals */
struct SigConnKinds {
// Wire bits directly driven by registers (with clk2fflogic exception)
ShardedSigPool raw_registers;
// Wire bits directly connected to any cell port
ShardedSigPool raw_cell_connected;
// Signals exactly driven by a known cell output,
// this will influence only our choice of representatives.
// A signal is exactly driven by a cell output iff all its bits are driven by this output
// and all bits of this output drive a bit of this signal.
// Additionally, all signals that sigmap to this signal are exactly driven by the port, too
ShardedSigSpecPool exact_cells;
SigConnKinds(bool purge_mode, const AnalysisContext& actx, CleanRunContext& clean_ctx) {
ShardedSigPool::Builder raw_register_builder(actx.subpool);
ShardedSigPool::Builder raw_cell_connected_builder(actx.subpool);
ShardedSigSpecPool::Builder exact_cell_output_builder(actx.subpool);
actx.subpool.run([&exact_cell_output_builder, &raw_register_builder, &raw_cell_connected_builder, purge_mode, &actx, &clean_ctx](const ParallelDispatchThreadPool::RunCtx &ctx) {
for (int i : ctx.item_range(actx.mod->cells_size())) {
RTLIL::Cell *cell = actx.mod->cell_at(i);
if (!purge_mode) {
if (clean_ctx.ct_reg(cell->type)) {
// Improve witness signal naming when clk2fflogic used
// see commit message e36c71b5
bool clk2fflogic = cell->get_bool_attribute(ID::clk2fflogic);
for (auto &[port, sig] : cell->connections())
if (clk2fflogic ? port == ID::D : clean_ctx.ct_all.cell_output(cell->type, port))
add_spec(raw_register_builder, ctx, sig);
}
for (auto &[_, sig] : cell->connections())
add_spec(raw_cell_connected_builder, ctx, sig);
}
if (clean_ctx.ct_all.cell_known(cell->type))
for (auto &[port, sig] : cell->connections())
if (clean_ctx.ct_all.cell_output(cell->type, port)) {
RTLIL::SigSpec spec = actx.assign_map(sig);
unsigned int hash = spec.hash_into(Hasher()).yield();
exact_cell_output_builder.insert(ctx, {std::move(spec), hash});
}
}
});
actx.subpool.run([&raw_register_builder, &raw_cell_connected_builder, &exact_cell_output_builder](const ParallelDispatchThreadPool::RunCtx &ctx) {
raw_register_builder.process(ctx);
raw_cell_connected_builder.process(ctx);
exact_cell_output_builder.process(ctx);
});
raw_registers = raw_register_builder;
raw_cell_connected = raw_cell_connected_builder;
exact_cells = exact_cell_output_builder;
}
void clear(const ParallelDispatchThreadPool::RunCtx &ctx) {
raw_registers.clear(ctx);
raw_cell_connected.clear(ctx);
exact_cells.clear(ctx);
}
};
ShardedVector<RTLIL::SigBit> build_candidates(ExactCellWires& cell_wires, const SigConnKinds& sig_analysis, const AnalysisContext& actx) {
ShardedVector<RTLIL::SigBit> candidates(actx.subpool);
actx.subpool.run([&actx, &sig_analysis, &candidates, &cell_wires](const ParallelDispatchThreadPool::RunCtx &ctx) {
std::optional<ExactCellWires> local_cell_wires;
ExactCellWires *this_thread_cell_wires = &cell_wires;
if (ctx.thread_num > 0) {
local_cell_wires.emplace(sig_analysis.exact_cells, actx.assign_map);
this_thread_cell_wires = &local_cell_wires.value();
}
for (int i : ctx.item_range(actx.mod->wires_size())) {
RTLIL::Wire *wire = actx.mod->wire_at(i);
for (int j = 0; j < wire->width; ++j) {
RTLIL::SigBit s1(wire, j);
RTLIL::SigBit s2 = actx.assign_map(s1);
if (compare_signals(s2, s1, sig_analysis.raw_registers, sig_analysis.raw_cell_connected, *this_thread_cell_wires))
candidates.insert(ctx, s1);
}
}
});
return candidates;
}
void update_assign_map(SigMap& assign_map, ShardedVector<RTLIL::SigBit>& sigmap_canonical_candidates, ExactCellWires& cell_wires, const SigConnKinds& sig_analysis) {
for (RTLIL::SigBit candidate : sigmap_canonical_candidates) {
RTLIL::SigBit current_canonical = assign_map(candidate);
// Resolves if two threads in build_candidates found different candidates
// for the same set
// TODO adds effort for single-threaded?
if (compare_signals(current_canonical, candidate, sig_analysis.raw_registers, sig_analysis.raw_cell_connected, cell_wires))
assign_map.add(candidate);
}
}
struct DeferredUpdates {
// Deferred updates to the assign_map
ShardedVector<UpdateConnection> update_connections;
// Wires we should remove init from
ShardedVector<RTLIL::Wire*> initialized_wires;
DeferredUpdates(ParallelDispatchThreadPool::Subpool &subpool) : update_connections(subpool), initialized_wires(subpool) {}
};
struct UsedSignals {
// here, "connected" means "driven or driving something"
// meanwhile, "used" means "driving something"
// sigmapped
ShardedSigPool connected;
// pre-sigmapped
ShardedSigPool raw_connected;
// sigmapped
ShardedSigPool used;
void clear(ParallelDispatchThreadPool::Subpool &subpool) {
subpool.run([this](const ParallelDispatchThreadPool::RunCtx &ctx) {
connected.clear(ctx);
raw_connected.clear(ctx);
used.clear(ctx);
});
}
};
DeferredUpdates analyse_connectivity(UsedSignals& used, SigConnKinds& sig_analysis, const AnalysisContext& actx, CleanRunContext &clean_ctx) {
DeferredUpdates deferred(actx.subpool);
ShardedSigPool::Builder conn_builder(actx.subpool);
ShardedSigPool::Builder raw_conn_builder(actx.subpool);
ShardedSigPool::Builder used_builder(actx.subpool);
// gather the usage information for cells and update cell connections with the altered sigmap
// also gather the usage information for ports, wires with `keep`
// also gather init bits
actx.subpool.run([&deferred, &conn_builder, &raw_conn_builder, &used_builder, &sig_analysis, &actx, &clean_ctx](const ParallelDispatchThreadPool::RunCtx &ctx) {
// Parallel destruction of these sharded structures
sig_analysis.clear(ctx);
for (int i : ctx.item_range(actx.mod->cells_size())) {
RTLIL::Cell *cell = actx.mod->cell_at(i);
for (const auto &[port, sig] : cell->connections_) {
SigSpec spec = actx.assign_map(sig);
if (spec != sig)
deferred.update_connections.insert(ctx, {cell, port, spec});
add_spec(raw_conn_builder, ctx, spec);
add_spec(conn_builder, ctx, spec);
if (!clean_ctx.ct_all.cell_output(cell->type, port))
add_spec(used_builder, ctx, spec);
}
}
for (int i : ctx.item_range(actx.mod->wires_size())) {
RTLIL::Wire *wire = actx.mod->wire_at(i);
if (wire->port_id > 0) {
RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
add_spec(raw_conn_builder, ctx, sig);
actx.assign_map.apply(sig);
add_spec(conn_builder, ctx, sig);
if (!wire->port_input)
add_spec(used_builder, ctx, sig);
}
if (wire->get_bool_attribute(ID::keep)) {
RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
actx.assign_map.apply(sig);
add_spec(conn_builder, ctx, sig);
}
auto it = wire->attributes.find(ID::init);
if (it != wire->attributes.end())
deferred.initialized_wires.insert(ctx, wire);
}
});
actx.subpool.run([&conn_builder, &raw_conn_builder, &used_builder](const ParallelDispatchThreadPool::RunCtx &ctx) {
conn_builder.process(ctx);
raw_conn_builder.process(ctx);
used_builder.process(ctx);
});
used = {conn_builder, raw_conn_builder, used_builder};
return deferred;
}
struct WireDeleter {
pool<RTLIL::Wire*> del_wires_queue;
ShardedVector<RTLIL::Wire*> remove_init;
ShardedVector<std::pair<RTLIL::Wire*, RTLIL::Const>> set_init;
ShardedVector<RTLIL::SigSig> new_connections;
ShardedVector<RTLIL::Wire*> remove_unused_bits;
ShardedVector<std::pair<RTLIL::Wire*, RTLIL::Const>> set_unused_bits;
WireDeleter(UsedSignals& used_sig_analysis, bool purge_mode, const AnalysisContext& actx) :
remove_init(actx.subpool),
set_init(actx.subpool),
new_connections(actx.subpool),
remove_unused_bits(actx.subpool),
set_unused_bits(actx.subpool) {
ShardedVector<RTLIL::Wire*> del_wires(actx.subpool);
actx.subpool.run([&actx, purge_mode, &del_wires, &used_sig_analysis, this](const ParallelDispatchThreadPool::RunCtx &ctx) {
for (int i : ctx.item_range(actx.mod->wires_size())) {
RTLIL::Wire *wire = actx.mod->wire_at(i);
SigSpec s1 = SigSpec(wire), s2 = actx.assign_map(s1);
log_assert(GetSize(s1) == GetSize(s2));
Const initval;
bool has_init_attribute = wire->attributes.count(ID::init);
bool init_changed = false;
if (has_init_attribute)
initval = wire->attributes.at(ID::init);
if (GetSize(initval) != GetSize(wire)) {
initval.resize(GetSize(wire), State::Sx);
init_changed = true;
}
if (GetSize(wire) == 0) {
// delete zero-width wires, unless they are module ports
if (wire->port_id == 0)
goto delete_this_wire;
} else
if (wire->port_id != 0 || wire->get_bool_attribute(ID::keep) || !initval.is_fully_undef()) {
// do not delete anything with "keep" or module ports or initialized wires
} else
if (!purge_mode && check_public_name(wire->name) && (check_any(used_sig_analysis.raw_connected, s1) || check_any(used_sig_analysis.connected, s2) || s1 != s2)) {
// do not get rid of public names unless in purge mode or if the wire is entirely unused, not even aliased
} else
if (!check_any(used_sig_analysis.raw_connected, s1)) {
// delete wires that aren't used by anything directly
goto delete_this_wire;
}
if (0)
{
delete_this_wire:
del_wires.insert(ctx, wire);
}
else
{
RTLIL::SigSig new_conn;
for (int i = 0; i < GetSize(s1); i++)
if (s1[i] != s2[i]) {
if (s2[i] == State::Sx && (initval[i] == State::S0 || initval[i] == State::S1)) {
s2[i] = initval[i];
initval.set(i, State::Sx);
init_changed = true;
}
new_conn.first.append(s1[i]);
new_conn.second.append(s2[i]);
}
if (new_conn.first.size() > 0)
new_connections.insert(ctx, std::move(new_conn));
if (initval.is_fully_undef()) {
if (has_init_attribute)
remove_init.insert(ctx, wire);
} else
if (init_changed)
set_init.insert(ctx, {wire, std::move(initval)});
std::string unused_bits;
if (!check_all(used_sig_analysis.used, s2)) {
for (int i = 0; i < GetSize(s2); i++) {
if (s2[i].wire == NULL)
continue;
SigBit b = s2[i];
if (used_sig_analysis.used.find({b, b.hash_top().yield()}) == nullptr) {
if (!unused_bits.empty())
unused_bits += " ";
unused_bits += stringf("%d", i);
}
}
}
if (unused_bits.empty() || wire->port_id != 0) {
if (wire->attributes.count(ID::unused_bits))
remove_unused_bits.insert(ctx, wire);
} else {
RTLIL::Const unused_bits_const(std::move(unused_bits));
if (wire->attributes.count(ID::unused_bits)) {
RTLIL::Const &unused_bits_attr = wire->attributes.at(ID::unused_bits);
if (unused_bits_attr != unused_bits_const)
set_unused_bits.insert(ctx, {wire, std::move(unused_bits_const)});
} else
set_unused_bits.insert(ctx, {wire, std::move(unused_bits_const)});
}
}
}
});
del_wires_queue.insert(del_wires.begin(), del_wires.end());
}
// Decide for each wire if we should be deleting it
// and fix up attributes
void commit_changes(RTLIL::Module* mod) {
for (RTLIL::Wire *wire : remove_init)
wire->attributes.erase(ID::init);
for (auto &p : set_init)
p.first->attributes[ID::init] = std::move(p.second);
for (auto &conn : new_connections)
mod->connect(std::move(conn));
for (RTLIL::Wire *wire : remove_unused_bits)
wire->attributes.erase(ID::unused_bits);
for (auto &p : set_unused_bits)
p.first->attributes[ID::unused_bits] = std::move(p.second);
}
int delete_wires(RTLIL::Module* mod, bool verbose) {
int deleted_and_unreported = 0;
for (auto wire : del_wires_queue) {
if (ys_debug() || (check_public_name(wire->name) && verbose))
log_debug(" removing unused non-port wire %s.\n", wire->name);
else
deleted_and_unreported++;
}
mod->remove(del_wires_queue);
return deleted_and_unreported;
}
};
PRIVATE_NAMESPACE_END
YOSYS_NAMESPACE_BEGIN
bool rmunused_module_signals(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, CleanRunContext &clean_ctx)
{
// Passing actx to function == function does parallel work
// Not passing module as function argument == function does not modify module
// The above sentence signals intent; it's not enforced due to constness laundering in wire_at / cell_at
AnalysisContext actx(module, subpool);
SigConnKinds conn_kinds(clean_ctx.flags.purge, actx, clean_ctx);
ExactCellWires cell_wires(conn_kinds.exact_cells, actx.assign_map);
// Collect sigmap representative candidates as built in parallel
// With parallel runs, this creates redundant candidates that have to resolve in update_assign_map
ShardedVector<RTLIL::SigBit> new_sigmap_rep_candidates = build_candidates(cell_wires, conn_kinds, actx);
// Cache all the cell_wires results that we might possible need. This avoids the results
// changing when we update `assign_map` below.
cell_wires.cache_all(new_sigmap_rep_candidates);
// Modify assign_map to reflect the connectivity we want, not the one we have
// this changes representative selection in assign_map
update_assign_map(actx.assign_map, new_sigmap_rep_candidates, cell_wires, conn_kinds);
// Remove all wire-wire connections
module->connections_.clear();
UsedSignals used;
DeferredUpdates deferred = analyse_connectivity(used, conn_kinds, actx, clean_ctx);
fixup_cell_ports(deferred.update_connections);
// Rip up and re-apply init attributes onto representative wires with x-bits
// in place of unset init bits
consume_inits(deferred.initialized_wires, actx.assign_map).apply_normalised_inits();
WireDeleter deleter(used, clean_ctx.flags.purge, actx);
used.clear(subpool);
deleter.commit_changes(module);
int deleted_and_unreported = deleter.delete_wires(module, clean_ctx.flags.verbose);
int deleted_total = GetSize(deleter.del_wires_queue);
clean_ctx.stats.count_rm_wires += deleted_total;
if (clean_ctx.flags.verbose && deleted_and_unreported)
log_debug(" removed %d unused temporary wires.\n", deleted_and_unreported);
if (deleted_total)
module->design->scratchpad_set_bool("opt.did_something", true);
return deleted_total != 0;
}
YOSYS_NAMESPACE_END

2
passes/opt/opt_demorgan.cc
View file

@ -43,7 +43,7 @@ void demorgan_worker(
if (GetSize(insig) < 1)
return;
log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig));
log("Inspecting %s cell %s (%d inputs)\n", cell->type.unescape(), cell->name.unescape(), GetSize(insig));
int num_inverted = 0;
for(int i=0; i<GetSize(insig); i++)
{

44
passes/opt/opt_dff.cc
View file

@ -301,7 +301,7 @@ struct OptDffWorker
initvals.remove_init(ff.sig_q[i]);
module->connect(ff.sig_q[i], State::S0);
log("Handling always-active CLR at position %d on %s (%s) from module %s (changing to const driver).\n",
i, log_id(cell), log_id(cell->type), log_id(module));
i, cell, cell->type.unescape(), module);
sr_removed = true;
} else if (is_always_active(ff.sig_set[i], ff.pol_set)) {
initvals.remove_init(ff.sig_q[i]);
@ -312,7 +312,7 @@ struct OptDffWorker
else
module->addNot(NEW_ID2_SUFFIX("not"), ff.sig_clr[i], ff.sig_q[i], false, cell->get_src_attribute());
log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n",
i, log_id(cell), log_id(cell->type), log_id(module));
i, cell, cell->type.unescape(), module);
sr_removed = true;
} else {
keep_bits.push_back(i);
@ -335,7 +335,7 @@ struct OptDffWorker
if (clr_inactive && signal_all_same(ff.sig_set)) {
log("Removing never-active CLR on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_sr = false;
ff.has_arst = true;
ff.pol_arst = ff.pol_set;
@ -344,7 +344,7 @@ struct OptDffWorker
changed = true;
} else if (set_inactive && signal_all_same(ff.sig_clr)) {
log("Removing never-active SET on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_sr = false;
ff.has_arst = true;
ff.pol_arst = ff.pol_clr;
@ -370,7 +370,7 @@ struct OptDffWorker
if (!failed) {
log("Converting CLR/SET to ARST on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_sr = false;
ff.has_arst = true;
ff.val_arst = val_arst_builder.build();
@ -389,7 +389,7 @@ struct OptDffWorker
// Converts constant Async Load to ARST
if (is_always_inactive(ff.sig_aload, ff.pol_aload)) {
log("Removing never-active async load on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_aload = false;
changed = true;
return false;
@ -398,7 +398,7 @@ struct OptDffWorker
if (is_active(ff.sig_aload, ff.pol_aload)) {
// ALOAD always active
log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
if (ff.has_sr) {
SigSpec tmp;
@ -433,7 +433,7 @@ struct OptDffWorker
// AD is constant -> ARST
if (ff.sig_ad.is_fully_const() && !ff.has_arst && !ff.has_sr) {
log("Changing const-value async load to async reset on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_arst = true;
ff.has_aload = false;
ff.sig_arst = ff.sig_aload;
@ -450,12 +450,12 @@ struct OptDffWorker
// Removes ARST if never active or replaces FF if always active
if (is_inactive(ff.sig_arst, ff.pol_arst)) {
log("Removing never-active ARST on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_arst = false;
changed = true;
} else if (is_always_active(ff.sig_arst, ff.pol_arst)) {
log("Handling always-active ARST on %s (%s) from module %s (changing to const driver).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.remove();
module->connect(ff.sig_q, ff.val_arst);
return true;
@ -469,12 +469,12 @@ struct OptDffWorker
// Removes SRST if never active or forces D to reset value if always active
if (is_inactive(ff.sig_srst, ff.pol_srst)) {
log("Removing never-active SRST on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_srst = false;
changed = true;
} else if (is_always_active(ff.sig_srst, ff.pol_srst)) {
log("Handling always-active SRST on %s (%s) from module %s (changing to const D).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_srst = false;
if (!ff.ce_over_srst)
ff.has_ce = false;
@ -489,7 +489,7 @@ struct OptDffWorker
if (is_always_inactive(ff.sig_ce, ff.pol_ce)) {
if (ff.has_srst && !ff.ce_over_srst) {
log("Handling never-active EN on %s (%s) from module %s (connecting SRST instead).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.pol_ce = ff.pol_srst;
ff.sig_ce = ff.sig_srst;
ff.has_srst = false;
@ -497,7 +497,7 @@ struct OptDffWorker
changed = true;
} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
log("Handling never-active EN on %s (%s) from module %s (removing D path).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_ce = ff.has_clk = ff.has_srst = false;
changed = true;
} else {
@ -507,7 +507,7 @@ struct OptDffWorker
}
} else if (is_active(ff.sig_ce, ff.pol_ce)) {
log("Removing always-active EN on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_ce = false;
changed = true;
}
@ -517,7 +517,7 @@ struct OptDffWorker
{
if (!opt.keepdc || ff.val_init.is_fully_def()) {
log("Handling const CLK on %s (%s) from module %s (removing D path).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_ce = ff.has_clk = ff.has_srst = false;
changed = true;
} else if (ff.has_ce || ff.has_srst || ff.sig_d != ff.sig_q) {
@ -532,7 +532,7 @@ struct OptDffWorker
// Detect feedback loops where D is hardwired to Q
if (ff.has_clk && ff.has_srst) {
log("Handling D = Q on %s (%s) from module %s (conecting SRST instead).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
if (ff.has_ce && ff.ce_over_srst) {
SigSpec ce = ff.pol_ce ? ff.sig_ce : create_not(ff.sig_ce, ff.is_fine, cell);
SigSpec srst = ff.pol_srst ? ff.sig_srst : create_not(ff.sig_srst, ff.is_fine, cell);
@ -549,7 +549,7 @@ struct OptDffWorker
changed = true;
} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
log("Handling D = Q on %s (%s) from module %s (removing D path).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_gclk = ff.has_clk = ff.has_ce = false;
changed = true;
}
@ -628,7 +628,7 @@ struct OptDffWorker
dff_cells.push_back(new_cell);
log("Adding SRST signal on %s (%s) from module %s (D = %s, Q = %s, rval = %s).\n",
log_id(cell), log_id(cell->type), log_id(module),
cell, cell->type.unescape(), module,
log_signal(new_ff.sig_d), log_signal(new_ff.sig_q), log_signal(new_ff.val_srst));
}
@ -703,7 +703,7 @@ struct OptDffWorker
dff_cells.push_back(new_cell);
log("Adding EN signal on %s (%s) from module %s (D = %s, Q = %s).\n",
log_id(cell), log_id(cell->type), log_id(module),
cell, cell->type.unescape(), module,
log_signal(new_ff.sig_d), log_signal(new_ff.sig_q));
}
@ -770,7 +770,7 @@ struct OptDffWorker
if (ff.has_aload && !ff.has_clk && ff.sig_ad == ff.sig_q) {
log_debug("Handling AD = Q on %s (%s) from module %s (removing async load path).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_aload = false;
changed = true;
}
@ -887,7 +887,7 @@ struct OptDffWorker
}
log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n",
val ? 1 : 0, i, log_id(cell), log_id(cell->type), log_id(module));
val ? 1 : 0, i, cell, cell->type.unescape(), module);
// Replace the Q output with the constant value
initvals.remove_init(ff.sig_q[i]);

64
passes/opt/opt_expr.cc
View file

@ -20,6 +20,7 @@
#include "kernel/register.h"
#include "kernel/sigtools.h"
#include "kernel/celltypes.h"
#include "kernel/newcelltypes.h"
#include "kernel/utils.h"
#include "kernel/log.h"
#include <stdlib.h>
@ -31,7 +32,7 @@ PRIVATE_NAMESPACE_BEGIN
bool did_something;
void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
void replace_undriven(RTLIL::Module *module, const NewCellTypes &ct)
{
SigMap sigmap(module);
SigPool driven_signals;
@ -87,7 +88,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
}
}
log_debug("Setting undriven signal in %s to constant: %s = %s\n", log_id(module), log_signal(sig), log_signal(val));
log_debug("Setting undriven signal in %s to constant: %s = %s\n", module, log_signal(sig), log_signal(val));
module->connect(sig, val);
did_something = true;
}
@ -104,11 +105,11 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
initval.set(i, State::Sx);
}
if (initval.is_fully_undef()) {
log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire));
log_debug("Removing init attribute from %s/%s.\n", module, wire);
wire->attributes.erase(ID::init);
did_something = true;
} else if (initval != wire->attributes.at(ID::init)) {
log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval));
log_debug("Updating init attribute on %s/%s: %s\n", module, wire, log_signal(initval));
wire->attributes[ID::init] = initval;
did_something = true;
}
@ -195,7 +196,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
return false;
log_debug("Replacing %s cell `%s' in module `%s' with cells using grouped bits:\n",
log_id(cell->type), log_id(cell), log_id(module));
cell->type.unescape(), cell, module);
for (int i = 0; i < GRP_N; i++)
{
@ -223,7 +224,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
new_a.replace(dict<SigBit,SigBit>{{State::Sx, State::S1}, {State::Sz, State::S1}}, &new_b);
else log_abort();
}
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), cell->type.unescape(), log_signal(new_a));
module->connect(new_y, new_b);
module->connect(new_conn);
continue;
@ -260,7 +261,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
}
}
if (!undef_y.empty()) {
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(undef_b), log_id(cell->type), log_signal(undef_a));
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(undef_b), cell->type.unescape(), log_signal(undef_a));
module->connect(undef_y, undef_b);
if (def_y.empty()) {
module->connect(new_conn);
@ -294,7 +295,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
module->connect(new_conn);
log_debug(" New cell `%s': A=%s", log_id(c), log_signal(new_a));
log_debug(" New cell `%s': A=%s", c, log_signal(new_a));
if (b_name == ID::B)
log_debug(", B=%s", log_signal(new_b));
log_debug("\n");
@ -310,7 +311,7 @@ void handle_polarity_inv(Cell *cell, IdString port, IdString param, const SigMap
SigSpec sig = assign_map(cell->getPort(port));
if (invert_map.count(sig)) {
log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
log_id(port), log_id(cell->type), log_id(cell), log_id(cell->module),
port.unescape(), cell->type.unescape(), cell, cell->module,
log_signal(sig), log_signal(invert_map.at(sig)));
cell->setPort(port, (invert_map.at(sig)));
cell->setParam(param, !cell->getParam(param).as_bool());
@ -339,7 +340,7 @@ void handle_clkpol_celltype_swap(Cell *cell, string type1, string type2, IdStrin
SigSpec sig = assign_map(cell->getPort(port));
if (invert_map.count(sig)) {
log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
log_id(port), log_id(cell->type), log_id(cell), log_id(cell->module),
port.unescape(), cell->type.unescape(), cell, cell->module,
log_signal(sig), log_signal(invert_map.at(sig)));
cell->setPort(port, (invert_map.at(sig)));
cell->type = cell->type == type1 ? type2 : type1;
@ -410,9 +411,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
}
CellTypes ct_memcells;
ct_memcells.setup_stdcells_mem();
if (!noclkinv)
for (auto cell : module->cells())
if (design->selected(module, cell)) {
@ -436,7 +434,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
if (!ct_memcells.cell_known(cell->type))
if (!StaticCellTypes::Compat::stdcells_mem(cell->type))
continue;
handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
@ -516,7 +514,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!cells.sort()) {
// There might be a combinational loop, or there might be constants on the output of cells. 'check' may find out more.
// ...unless this is a coarse-grained cell loop, but not a bit loop, in which case it won't, and all is good.
log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", log_id(module));
log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", module);
}
for (auto cell : cells.sorted)
@ -636,7 +634,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
{
if (cell->type == ID($reduce_xnor)) {
log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n",
log_id(cell->type), log_id(cell->name), log_id(module));
cell->type.unescape(), cell->name.unescape(), module);
cell->type = ID($not);
did_something = true;
} else {
@ -656,7 +654,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (a_fully_const != b_fully_const)
{
log_debug("Replacing %s cell `%s' in module `%s' having one fully constant input\n",
log_id(cell->type), log_id(cell->name), log_id(module));
cell->type.unescape(), cell->name.unescape(), module);
RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
int width = GetSize(cell->getPort(ID::Y));
@ -952,7 +950,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
break;
}
if (i > 0) {
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module));
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescape(), cell, module);
SigSpec new_a = sig_a.extract_end(i);
SigSpec new_b = sig_b.extract_end(i);
if (new_a.empty() && is_signed)
@ -1008,7 +1006,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
break;
}
if (i > 0) {
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module));
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescape(), cell, module);
SigSpec new_a = sig_a.extract_end(i);
SigSpec new_b = sig_b.extract_end(i);
if (new_a.empty() && is_signed)
@ -1082,7 +1080,7 @@ skip_fine_alu:
}
if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID::S))) != 0) {
log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", cell->type.unescape(), cell, module);
RTLIL::SigSpec tmp = cell->getPort(ID::A);
cell->setPort(ID::A, cell->getPort(ID::B));
cell->setPort(ID::B, tmp);
@ -1261,7 +1259,7 @@ skip_fine_alu:
RTLIL::SigSpec input = b;
ACTION_DO(ID::Y, cell->getPort(ID::A));
} else {
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescape(), cell, module);
cell->type = ID($not);
cell->parameters.erase(ID::B_WIDTH);
cell->parameters.erase(ID::B_SIGNED);
@ -1275,8 +1273,8 @@ skip_fine_alu:
if (cell->type.in(ID($eq), ID($ne)) &&
(assign_map(cell->getPort(ID::A)).is_fully_zero() || assign_map(cell->getPort(ID::B)).is_fully_zero()))
{
log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell),
log_id(module), cell->type == ID($eq) ? "$logic_not" : "$reduce_bool");
log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", cell->type.unescape(), cell,
module, cell->type == ID($eq) ? "$logic_not" : "$reduce_bool");
cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool);
if (assign_map(cell->getPort(ID::A)).is_fully_zero()) {
cell->setPort(ID::A, cell->getPort(ID::B));
@ -1323,7 +1321,7 @@ skip_fine_alu:
}
log_debug("Replacing %s cell `%s' (B=%s, SHR=%d) in module `%s' with fixed wiring: %s\n",
log_id(cell->type), log_id(cell), log_signal(assign_map(cell->getPort(ID::B))), shift_bits, log_id(module), log_signal(sig_y));
cell->type.unescape(), cell, log_signal(assign_map(cell->getPort(ID::B))), shift_bits, module, log_signal(sig_y));
module->connect(cell->getPort(ID::Y), sig_y);
module->remove(cell);
@ -1448,7 +1446,7 @@ skip_identity:
if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == State::S1 && cell->getPort(ID::B) == State::S0) {
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescape(), cell, module);
cell->setPort(ID::A, cell->getPort(ID::S));
cell->unsetPort(ID::B);
cell->unsetPort(ID::S);
@ -1466,7 +1464,7 @@ skip_identity:
}
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == State::S0) {
log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", cell->type.unescape(), cell, module);
cell->setPort(ID::A, cell->getPort(ID::S));
cell->unsetPort(ID::S);
if (cell->type == ID($mux)) {
@ -1485,7 +1483,7 @@ skip_identity:
}
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::B) == State::S1) {
log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", cell->type.unescape(), cell, module);
cell->setPort(ID::B, cell->getPort(ID::S));
cell->unsetPort(ID::S);
if (cell->type == ID($mux)) {
@ -1535,7 +1533,7 @@ skip_identity:
}
if (cell->getPort(ID::S).size() != new_s.size()) {
log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
GetSize(cell->getPort(ID::S)) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
GetSize(cell->getPort(ID::S)) - GetSize(new_s), cell->type.unescape(), cell, module);
cell->setPort(ID::A, new_a);
cell->setPort(ID::B, new_b);
cell->setPort(ID::S, new_s);
@ -2046,7 +2044,7 @@ skip_alu_split:
Const y_value(cell->type.in(ID($eq), ID($eqx)) ? 0 : 1, GetSize(y_sig));
log_debug("Replacing cell `%s' in module `%s' with constant driver %s.\n",
log_id(cell), log_id(module), log_signal(y_value));
cell, module, log_signal(y_value));
module->connect(y_sig, y_value);
module->remove(cell);
@ -2058,7 +2056,7 @@ skip_alu_split:
if (redundant_bits)
{
log_debug("Removed %d redundant input bits from %s cell `%s' in module `%s'.\n",
redundant_bits, log_id(cell->type), log_id(cell), log_id(module));
redundant_bits, cell->type.unescape(), cell, module);
cell->setPort(ID::A, sig_a);
cell->setPort(ID::B, sig_b);
@ -2209,7 +2207,7 @@ skip_alu_split:
if (replace || remove)
{
log_debug("Replacing %s cell `%s' (implementing %s) with %s.\n",
log_id(cell->type), log_id(cell), condition.c_str(), replacement.c_str());
cell->type.unescape(), cell, condition.c_str(), replacement.c_str());
if (replace)
module->connect(cell->getPort(ID::Y), replace_sig);
module->remove(cell);
@ -2554,10 +2552,10 @@ struct OptExprPass : public Pass {
}
extra_args(args, argidx, design);
CellTypes ct(design);
NewCellTypes ct(design);
for (auto module : design->selected_modules())
{
log("Optimizing module %s.\n", log_id(module));
log("Optimizing module %s.\n", module);
if (undriven) {
did_something = false;

30
passes/opt/opt_hier.cc
View file

@ -80,7 +80,7 @@ struct ModuleIndex {
} else {
classes[pair.second[i]].append(pair.first[i]);
}
}
}
}
}
@ -107,7 +107,7 @@ struct ModuleIndex {
if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
log_error("Port %s connected on instance %s not found in module %s"
" or width is not matching\n",
log_id(port_name), log_id(instantiation), log_id(module));
port_name.unescape(), instantiation, module);
}
if (port->port_input && port->port_output) {
@ -151,12 +151,12 @@ struct ModuleIndex {
if (nunused > 0) {
log("Disconnected %d input bits of instance '%s' (type '%s') in '%s'\n",
nunused, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
nunused, instantiation, instantiation->type.unescape(), parent.module);
changed = true;
}
if (nconstants > 0) {
log("Substituting constant for %d output bits of instance '%s' (type '%s') in '%s'\n",
nconstants, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
nconstants, instantiation, instantiation->type.unescape(), parent.module);
changed = true;
}
}
@ -195,7 +195,7 @@ struct ModuleIndex {
if (ntie_togethers > 0) {
log("Replacing %d output bits with tie-togethers on instance '%s' of '%s' in '%s'\n",
ntie_togethers, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
ntie_togethers, instantiation, instantiation->type.unescape(), parent.module);
changed = true;
}
@ -223,7 +223,7 @@ struct UsageData {
for (auto port_name : module->ports) {
Wire *port = module->wire(port_name);
log_assert(port);
if (port->port_input && port->port_output) {
// ignore bidirectional: hard to come up with sound handling
continue;
@ -296,7 +296,7 @@ struct UsageData {
if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
log_error("Port %s connected on instance %s not found in module %s"
" or width is not matching\n",
log_id(port_name), log_id(instance), log_id(module));
port_name.unescape(), instance, module);
}
if (port->port_input && port->port_output) {
@ -353,7 +353,7 @@ struct UsageData {
};
module->rewrite_sigspecs(disconnect_rewrite);
for (auto chunk : disconnect_outputs.chunks()) {
log("Disconnected unused output terminal '%s' in module '%s'\n", log_signal(chunk), log_id(module));
log("Disconnected unused output terminal '%s' in module '%s'\n", log_signal(chunk), module);
did_something = true;
module->connect(chunk, SigSpec(RTLIL::Sx, chunk.size()));
}
@ -374,7 +374,7 @@ struct UsageData {
SigSpec const_ = chunk;
const_.replace(constant_inputs);
log("Substituting constant %s for input terminal '%s' in module '%s'\n",
log_signal(const_), log_signal(chunk), log_id(module));
log_signal(const_), log_signal(chunk), module);
}
// Propagate tied-together inputs
@ -403,7 +403,7 @@ struct UsageData {
module->rewrite_sigspecs(ties_rewrite);
if (applied_ties.size()) {
log("Replacing %zu input terminal bits with tie-togethers in module '%s'\n",
applied_ties.size(), log_id(module));
applied_ties.size(), module);
}
return did_something;
}
@ -439,7 +439,7 @@ struct OptHierPass : Pass {
dict<IdString, ModuleIndex> indices;
for (auto module : d->modules()) {
log_debug("Building index for %s\n", log_id(module));
log_debug("Building index for %s\n", module);
indices.emplace(module->name, ModuleIndex(module));
}
@ -448,14 +448,14 @@ struct OptHierPass : Pass {
if (module->get_bool_attribute(ID::top) || is_dw_module(module))
continue;
log_debug("Starting usage data for %s\n", log_id(module));
log_debug("Starting usage data for %s\n", module);
usage_datas.emplace(module->name, UsageData(module));
}
for (auto module : d->modules()) {
for (auto cell : module->cells()) {
if (usage_datas.count(cell->type)) {
log_debug("Account for instance %s of %s in %s\n", log_id(cell), log_id(cell->type), log_id(module));
log_debug("Account for instance %s of %s in %s\n", cell, cell->type.unescape(), module);
usage_datas.at(cell->type).refine(cell, indices.at(module->name));
}
}
@ -471,14 +471,14 @@ struct OptHierPass : Pass {
ModuleIndex &parent_index = indices.at(module->name);
if (usage_datas.count(module->name)) {
log_debug("Applying usage data changes to %s\n", log_id(module));
log_debug("Applying usage data changes to %s\n", module);
did_something |= usage_datas.at(module->name).apply_changes(parent_index);
}
for (auto cell : module->cells()) {
Module *child = d->module(cell->type);
if (child != nullptr && !is_dw_module(child) && indices.count(cell->type)) {
log_debug("Applying changes to instance %s of %s in %s\n", log_id(cell), log_id(cell->type), log_id(module));
log_debug("Applying changes to instance %s of %s in %s\n", cell, cell->type.unescape(), module);
did_something |= indices.at(cell->type).apply_changes(parent_index, cell);
}
}

16
passes/opt/opt_lut.cc
View file

@ -121,7 +121,7 @@ struct OptLutWorker
SigSpec lut_input = cell->getPort(ID::A);
int lut_arity = 0;
log_debug("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, log_id(module), log_id(cell));
log_debug("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, module, cell);
luts.insert(cell);
// First, find all dedicated logic we're connected to. This results in an overapproximation
@ -162,7 +162,7 @@ struct OptLutWorker
{
if (lut_width <= dlogic_conn.first)
{
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, module, lut_dlogic.second);
log_debug(" LUT input A[%d] not present.\n", dlogic_conn.first);
legal = false;
break;
@ -173,7 +173,7 @@ struct OptLutWorker
if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)[0]))
{
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, module, lut_dlogic.second);
log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type, dlogic_conn.second, log_signal(lut_dlogic.second->getPort(dlogic_conn.second)));
legal = false;
break;
@ -182,7 +182,7 @@ struct OptLutWorker
if (legal)
{
log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type, module, lut_dlogic.second);
lut_legal_dlogics.insert(lut_dlogic);
for (auto &dlogic_conn : dlogic_map)
lut_dlogic_inputs.insert(dlogic_conn.first);
@ -258,7 +258,7 @@ struct OptLutWorker
if (const0_match || const1_match || input_match != -1)
{
log_debug("Found redundant cell %s.%s.\n", log_id(module), log_id(lut));
log_debug("Found redundant cell %s.%s.\n", module, lut);
SigBit value;
if (const0_match)
@ -341,7 +341,7 @@ struct OptLutWorker
int lutB_arity = luts_arity[lutB];
pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB];
log_debug("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
log_debug("Found %s.%s (cell A) feeding %s.%s (cell B).\n", module, lutA, module, lutB);
if (index.query_is_output(lutA->getPort(ID::Y)))
{
@ -421,13 +421,12 @@ struct OptLutWorker
}
RTLIL::Cell *lutM, *lutR;
pool<SigBit> lutM_inputs, lutR_inputs;
pool<SigBit> lutR_inputs;
pool<int> lutM_dlogic_inputs;
if (combine == COMBINE_A)
{
log_debug(" Combining LUTs into cell A.\n");
lutM = lutA;
lutM_inputs = lutA_inputs;
lutM_dlogic_inputs = lutA_dlogic_inputs;
lutR = lutB;
lutR_inputs = lutB_inputs;
@ -436,7 +435,6 @@ struct OptLutWorker
{
log_debug(" Combining LUTs into cell B.\n");
lutM = lutB;
lutM_inputs = lutB_inputs;
lutM_dlogic_inputs = lutB_dlogic_inputs;
lutR = lutA;
lutR_inputs = lutA_inputs;

17
passes/opt/opt_lut_ins.cc
View file

@ -39,7 +39,8 @@ struct OptLutInsPass : public Pass {
log("\n");
log(" -tech <technology>\n");
log(" Instead of generic $lut cells, operate on LUT cells specific\n");
log(" to the given technology. Valid values are: xilinx, lattice, gowin.\n");
log(" to the given technology. Valid values are: xilinx, lattice,\n");
log(" gowin, analogdevices.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -58,12 +59,12 @@ struct OptLutInsPass : public Pass {
}
extra_args(args, argidx, design);
if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "ecp5" && techname != "gowin")
if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "analogdevices" && techname != "gowin")
log_cmd_error("Unsupported technology: '%s'\n", techname);
for (auto module : design->selected_modules())
{
log("Optimizing LUTs in %s.\n", log_id(module));
log("Optimizing LUTs in %s.\n", module);
std::vector<Cell *> remove_cells;
// Gather LUTs.
@ -81,7 +82,7 @@ struct OptLutInsPass : public Pass {
inputs = cell->getPort(ID::A);
output = cell->getPort(ID::Y);
lut = cell->getParam(ID::LUT);
} else if (techname == "xilinx" || techname == "gowin") {
} else if (techname == "xilinx" || techname == "gowin" || techname == "analogdevices") {
if (cell->type == ID(LUT1)) {
inputs = {
cell->getPort(ID(I0)),
@ -126,11 +127,11 @@ struct OptLutInsPass : public Pass {
continue;
}
lut = cell->getParam(ID::INIT);
if (techname == "xilinx")
if (techname == "xilinx" || techname == "analogdevices")
output = cell->getPort(ID::O);
else
output = cell->getPort(ID::F);
} else if (techname == "lattice" || techname == "ecp5") {
} else if (techname == "lattice") {
if (cell->type == ID(LUT4)) {
inputs = {
cell->getPort(ID::A),
@ -180,7 +181,7 @@ struct OptLutInsPass : public Pass {
}
if (!doit)
continue;
log(" Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs));
log(" Optimizing lut %s (%d -> %d)\n", cell, GetSize(inputs), GetSize(new_inputs));
if (techname == "lattice" || techname == "ecp5") {
// Pad the LUT to 4 inputs, adding consts from the front.
int extra = 4 - GetSize(new_inputs);
@ -236,7 +237,7 @@ struct OptLutInsPass : public Pass {
} else {
// xilinx, gowin
cell->setParam(ID::INIT, new_lut);
if (techname == "xilinx")
if (techname == "xilinx" || techname == "analogdevices")
log_assert(GetSize(new_inputs) <= 6);
else
log_assert(GetSize(new_inputs) <= 4);

6
passes/opt/opt_mem.cc
View file

@ -108,13 +108,13 @@ struct OptMemPass : public Pass {
}
State bit;
if (!always_0[i]) {
log("%s.%s: removing const-1 lane %d\n", log_id(module->name), log_id(mem.memid), i);
log("%s.%s: removing const-1 lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
bit = State::S1;
} else if (!always_1[i]) {
log("%s.%s: removing const-0 lane %d\n", log_id(module->name), log_id(mem.memid), i);
log("%s.%s: removing const-0 lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
bit = State::S0;
} else {
log("%s.%s: removing const-x lane %d\n", log_id(module->name), log_id(mem.memid), i);
log("%s.%s: removing const-x lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
bit = State::Sx;
}
// Reconnect read port data.

4
passes/opt/opt_mem_feedback.cc
View file

@ -163,7 +163,7 @@ struct OptMemFeedbackWorker
{
auto &port = mem.wr_ports[i];
log(" Analyzing %s.%s write port %d.\n", log_id(module), log_id(mem.memid), i);
log(" Analyzing %s.%s write port %d.\n", module, mem.memid.unescape(), i);
for (int sub = 0; sub < (1 << port.wide_log2); sub++)
{
@ -232,7 +232,7 @@ struct OptMemFeedbackWorker
// Okay, let's do it.
log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", log_id(module), log_id(mem.memid));
log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", module, mem.memid.unescape());
// If a write port has a feedback path that we're about to bypass,
// but also has priority over some other write port, the feedback

2
passes/opt/opt_mem_widen.cc
View file

@ -65,7 +65,7 @@ struct OptMemWidenPass : public Pass {
factor_log2 = port.wide_log2;
if (factor_log2 == 0)
continue;
log("Widening base width of memory %s in module %s by factor %d.\n", log_id(mem.memid), log_id(module->name), 1 << factor_log2);
log("Widening base width of memory %s in module %s by factor %d.\n", mem.memid.unescape(), module->name.unescape(), 1 << factor_log2);
total_count++;
// The inits are too messy to expand one-by-one, for they may
// collide with one another after expansion. Just hit it with

2
passes/opt/opt_merge.cc
View file

@ -324,7 +324,7 @@ struct OptMergeThreadWorker
CellEqualOp> known_cells(0, CellHashOp(), CellEqualOp(*this));
std::vector<DuplicateCell> duplicates;
for (const std::vector<std::vector<CellHash>> &buckets : in.bucketed_cell_hashes) {
for (std::vector<std::vector<CellHash>> &buckets : in.bucketed_cell_hashes) {
// Clear out our buckets as we go. This keeps the work of deallocation
// off the main thread.
std::vector<CellHash> bucket = std::move(buckets[index]);

92
passes/opt/opt_muxtree.cc
View file

@ -21,11 +21,9 @@
#include "kernel/sigtools.h"
#include "kernel/log.h"
#include "kernel/celltypes.h"
#include <cstddef>
#include <stdlib.h>
#include <stdio.h>
#include <unordered_map>
#include <unordered_set>
#include <set>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -128,7 +126,7 @@ struct OptMuxtreeWorker
// In case of $pmux, port B is multiple slices, concatenated, one per bit of port S
for (int i = 0; i < GetSize(sig_s); i++) {
RTLIL::SigSpec sig = sig_b.extract(i*GetSize(sig_a), GetSize(sig_a));
RTLIL::SigSpec ctrl_sig = assign_map(sig_s.extract(i, 1));
RTLIL::SigSpec ctrl_sig = assign_map(SigSpec{sig_s[i]});
portinfo_t portinfo = used_port_bit(sig, this_mux_idx);
portinfo.ctrl_sig = sig2bits(ctrl_sig, false).front();
portinfo.const_activated = ctrl_sig.is_fully_const() && ctrl_sig.as_bool();
@ -202,6 +200,29 @@ struct OptMuxtreeWorker
root_muxes.at(driving_mux) = true;
}
struct knowledge_t
{
// Known inactive signals
// The payload is a reference counter used to manage the list
// When it is non-zero, the signal in known to be inactive
// When it reaches zero, the map element is removed
std::vector<int> known_inactive;
// database of known active signals
std::vector<int> known_active;
// this is just used to keep track of visited muxes in order to prohibit
// endless recursion in mux loops
std::vector<bool> visited_muxes;
// Initialize with the maximum possible sizes
knowledge_t(int num_bits, int num_muxes) {
known_inactive.assign(num_bits, 0);
known_active.assign(num_bits, 0);
visited_muxes.assign(num_muxes, false);
}
};
OptMuxtreeWorker(RTLIL::Design *design, RTLIL::Module *module) :
design(design), module(module), assign_map(module), removed_count(0)
{
@ -229,11 +250,13 @@ struct OptMuxtreeWorker
populate_roots();
knowledge_t shared_knowledge(GetSize(bit2info), GetSize(mux2info));
for (int mux_idx = 0; mux_idx < GetSize(root_muxes); mux_idx++)
if (root_muxes.at(mux_idx)) {
log_debug(" Root of a mux tree: %s%s\n", log_id(mux2info[mux_idx].cell), root_enable_muxes.at(mux_idx) ? " (pure)" : "");
log_debug(" Root of a mux tree: %s%s\n", mux2info[mux_idx].cell, root_enable_muxes.at(mux_idx) ? " (pure)" : "");
root_mux_rerun.erase(mux_idx);
eval_root_mux(mux_idx);
eval_root_mux(shared_knowledge, mux_idx);
if (glob_evals_left == 0) {
log(" Giving up (too many iterations)\n");
return;
@ -242,10 +265,10 @@ struct OptMuxtreeWorker
while (!root_mux_rerun.empty()) {
int mux_idx = *root_mux_rerun.begin();
log_debug(" Root of a mux tree: %s (rerun as non-pure)\n", log_id(mux2info[mux_idx].cell));
log_debug(" Root of a mux tree: %s (rerun as non-pure)\n", mux2info[mux_idx].cell);
log_assert(root_enable_muxes.at(mux_idx));
root_mux_rerun.erase(mux_idx);
eval_root_mux(mux_idx);
eval_root_mux(shared_knowledge, mux_idx);
if (glob_evals_left == 0) {
log(" Giving up (too many iterations)\n");
return;
@ -336,22 +359,6 @@ struct OptMuxtreeWorker
return results;
}
struct knowledge_t
{
// Known inactive signals
// The payload is a reference counter used to manage the list
// When it is non-zero, the signal in known to be inactive
// When it reaches zero, the map element is removed
std::unordered_map<int, int> known_inactive;
// database of known active signals
std::unordered_map<int, int> known_active;
// this is just used to keep track of visited muxes in order to prohibit
// endless recursion in mux loops
std::unordered_set<int> visited_muxes;
};
static void activate_port(knowledge_t &knowledge, int port_idx, const muxinfo_t &muxinfo) {
// First, mark all other ports inactive
for (int i = 0; i < GetSize(muxinfo.ports); i++) {
@ -366,11 +373,10 @@ struct OptMuxtreeWorker
}
static void deactivate_port(knowledge_t &knowledge, int port_idx, const muxinfo_t &muxinfo) {
auto unlearn = [](std::unordered_map<int, int>& knowns, int i) {
auto it = knowns.find(i);
if (it != knowns.end())
if (--it->second == 0)
knowns.erase(it);
auto unlearn = [](std::vector<int>& knowns, int bit_idx) {
if (knowns[bit_idx] > 0) {
--knowns[bit_idx];
}
};
if (port_idx < GetSize(muxinfo.ports)-1 && !muxinfo.ports[port_idx].const_activated)
@ -418,9 +424,9 @@ struct OptMuxtreeWorker
vector<int> input_mux_queue;
for (int m : muxinfo.ports[port_idx].input_muxes) {
if (knowledge.visited_muxes.count(m))
if (knowledge.visited_muxes[m])
continue;
knowledge.visited_muxes.insert(m);
knowledge.visited_muxes[m] = true;
input_mux_queue.push_back(m);
}
for (int m : input_mux_queue) {
@ -433,7 +439,7 @@ struct OptMuxtreeWorker
// Ran out of subtree depth, re-eval this input tree in the next re-run
root_mux_rerun.insert(m);
root_enable_muxes.at(m) = true;
log_debug(" Removing pure flag from root mux %s.\n", log_id(mux2info[m].cell));
log_debug(" Removing pure flag from root mux %s.\n", mux2info[m].cell);
} else {
auto new_limits = limits.subtree();
// Since our knowledge includes assumption,
@ -453,7 +459,7 @@ struct OptMuxtreeWorker
// Allow revisiting input muxes, since evaluating other ports should
// revisit these input muxes with different activation assumptions
for (int m : input_mux_queue)
knowledge.visited_muxes.erase(m);
knowledge.visited_muxes[m] = false;
// Undo our assumptions that the port is active
deactivate_port(knowledge, port_idx, muxinfo);
@ -475,11 +481,11 @@ struct OptMuxtreeWorker
vector<int> bits = sig2bits(sig, false);
for (int i = 0; i < GetSize(bits); i++) {
if (bits[i] >= 0) {
if (knowledge.known_inactive.count(bits[i]) > 0) {
if (knowledge.known_inactive[bits[i]] > 0) {
sig[i] = State::S0;
did_something = true;
} else
if (knowledge.known_active.count(bits[i]) > 0) {
if (knowledge.known_active[bits[i]] > 0) {
sig[i] = State::S1;
did_something = true;
}
@ -513,8 +519,8 @@ struct OptMuxtreeWorker
}
if (did_something) {
log(" Replacing known input bits on port %s of cell %s: %s -> %s\n", log_id(portname),
log_id(muxinfo.cell), log_signal(muxinfo.cell->getPort(portname)), log_signal(sig));
log(" Replacing known input bits on port %s of cell %s: %s -> %s\n", portname.unescape(),
muxinfo.cell, log_signal(muxinfo.cell->getPort(portname)), log_signal(sig));
muxinfo.cell->setPort(portname, sig);
}
}
@ -526,7 +532,7 @@ struct OptMuxtreeWorker
glob_evals_left--;
muxinfo_t &muxinfo = mux2info[mux_idx];
log_debug("\t\teval %s (replace %d enable %d)\n", log_id(muxinfo.cell), limits.do_replace_known, limits.do_mark_ports_observable);
log_debug("\t\teval %s (replace %d enable %d)\n", muxinfo.cell, limits.do_replace_known, limits.do_mark_ports_observable);
// set input ports to constants if we find known active or inactive signals
if (limits.do_replace_known) {
@ -552,7 +558,7 @@ struct OptMuxtreeWorker
portinfo_t &portinfo = muxinfo.ports[port_idx];
if (portinfo.const_deactivated)
continue;
if (knowledge.known_active.count(portinfo.ctrl_sig) > 0) {
if (knowledge.known_active[portinfo.ctrl_sig] > 0) {
eval_mux_port(knowledge, mux_idx, port_idx, limits);
return;
}
@ -566,7 +572,7 @@ struct OptMuxtreeWorker
if (portinfo.const_deactivated)
continue;
if (port_idx < GetSize(muxinfo.ports)-1)
if (knowledge.known_inactive.count(portinfo.ctrl_sig) > 0)
if (knowledge.known_inactive[portinfo.ctrl_sig] > 0)
continue;
eval_mux_port(knowledge, mux_idx, port_idx, limits);
@ -575,14 +581,14 @@ struct OptMuxtreeWorker
}
}
void eval_root_mux(int mux_idx)
void eval_root_mux(knowledge_t &knowledge, int mux_idx)
{
log_assert(glob_evals_left > 0);
knowledge_t knowledge;
knowledge.visited_muxes.insert(mux_idx);
knowledge.visited_muxes[mux_idx] = true;
limits_t limits = {};
limits.do_mark_ports_observable = root_enable_muxes.at(mux_idx);
eval_mux(knowledge, mux_idx, limits);
knowledge.visited_muxes[mux_idx] = false;
}
};

25
passes/opt/opt_reduce.cc
View file

@ -110,22 +110,20 @@ struct OptReduceWorker
RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec new_sig_b, new_sig_s;
pool<RTLIL::SigSpec> handled_sig;
dict<RTLIL::SigSpec, std::vector<RTLIL::SigBit>> grouped_b_to_s;
handled_sig.insert(sig_a);
for (int i = 0; i < sig_s.size(); i++)
{
RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.size(), sig_a.size());
if (handled_sig.count(this_b) > 0)
continue;
RTLIL::SigSpec this_s = sig_s.extract(i, 1);
for (int j = i+1; j < sig_s.size(); j++) {
RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.size(), sig_a.size());
if (this_b == that_b)
this_s.append(sig_s.extract(j, 1));
int port_width = sig_a.size();
for (int i = 0; i < sig_s.size(); i++) {
RTLIL::SigSpec this_b = sig_b.extract(i*port_width, port_width);
if (grouped_b_to_s.count(this_b)) {
grouped_b_to_s[this_b].push_back(sig_s[i]);
} else {
grouped_b_to_s[this_b] = {sig_s[i]};
}
}
for (auto &[this_b, this_s_bit] : grouped_b_to_s) {
RTLIL::SigSpec this_s{this_s_bit};
if (this_s.size() > 1)
{
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID2_SUFFIX("reduce_or"), ID($reduce_or)); // SILIMATE: Improve the naming
@ -142,7 +140,6 @@ struct OptReduceWorker
new_sig_b.append(this_b);
new_sig_s.append(this_s);
handled_sig.insert(this_b);
}
if (new_sig_s.size() == 0)

6
passes/opt/opt_share.cc
View file

@ -446,7 +446,7 @@ struct OptSharePass : public Pass {
while (mux_port_offset + op_conn_width < mux_port_size &&
op_outsig_offset + op_conn_width < op_outsig_size &&
mux_insig[mux_port_offset + op_conn_width] == op_outsig[op_outsig_offset + op_conn_width])
op_conn_width++;
op_conn_width++;
log_assert(op_conn_width >= 1);
@ -561,9 +561,9 @@ struct OptSharePass : public Pass {
log_debug(" Found cells that share an operand and can be merged by moving the %s %s in front "
"of "
"them:\n",
log_id(shared.mux->type), log_id(shared.mux));
shared.mux->type.unescape(), shared.mux);
for (const auto& op : shared.ports)
log_debug(" %s\n", log_id(op.op));
log_debug(" %s\n", op.op);
log_debug("\n");
merge_operators(module, shared.mux, shared.ports, shared.shared_operand, sigmap);

27
passes/opt/peepopt.cc
View file

@ -73,6 +73,12 @@ struct PeepoptPass : public Pass {
log(" limits the amount of padding to a multiple of the data, \n");
log(" to avoid high resource usage from large temporary MUX trees.\n");
log("\n");
log(" * shiftpow2 - Replace A>>(B<<K) with a $bmux word multiplexer when\n");
log(" the output width is at most the stride 1<<K. This handles\n");
log(" power-of-two aligned word selects.\n");
log(" Scratchpad: 'peepopt.shiftpow2.max_data_multiple' (default: 2)\n");
log(" limits padding for out-of-range select values.\n");
log("\n");
log("If -formalclk is specified it instead employs the following rules:\n");
log("\n");
log(" * clockgateff - Replace latch based clock gating patterns with a flip-flop\n");
@ -127,16 +133,17 @@ struct PeepoptPass : public Pass {
if (formalclk) {
pm.run_formal_clockgateff();
} else {
pm.run_shiftadd();
pm.run_shiftmul_right();
pm.run_shiftmul_left();
pm.run_muldiv();
pm.run_muldiv_c();
pm.run_modshr_onehot();
pm.run_addsub_c();
pm.run_sub_neg();
if (muxorder)
pm.run_muxorder();
pm.run_shiftadd();
pm.run_shiftmul_right();
pm.run_shiftmul_left();
pm.run_shiftpow2();
pm.run_muldiv();
pm.run_muldiv_c();
pm.run_modshr_onehot();
pm.run_addsub_c();
pm.run_sub_neg();
if (muxorder)
pm.run_muxorder();
}
}
}

2
passes/opt/peepopt_formal_clockgateff.pmg
View file

@ -44,7 +44,7 @@ endmatch
code
log("replacing clock gate pattern in %s with ff: latch=%s, and=%s\n",
log_id(module), log_id(latch), log_id(and_gate));
module, latch, and_gate);
// Add a flip-flop and rewire the AND gate to use the output of this flop
// instead of the latch. We don't delete the latch in case its output is

2
passes/opt/peepopt_muldiv.pmg
View file

@ -32,7 +32,7 @@ code
val_y.extend_u0(GetSize(div_y), param(div, \A_SIGNED).as_bool());
did_something = true;
log("muldiv pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
log("muldiv pattern in %s: mul=%s, div=%s\n", module, mul, div);
module->connect(div_y, val_y);
autoremove(div);
accept;

2
passes/opt/peepopt_muldiv_c.pmg
View file

@ -119,7 +119,7 @@ code
autoremove(div);
// Log, fixup, accept
log("muldiv_const pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
log("muldiv_const pattern in %s: mul=%s, div=%s\n", module, mul, div);
mul->fixup_parameters();
accept;
endcode

2
passes/opt/peepopt_shiftadd.pmg
View file

@ -112,7 +112,7 @@ code
did_something = true;
log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \
log_id(module), log_id(shift), log_id(add), offset);
module, shift, add, offset);
SigSpec new_a;
if(offset<0) {

2
passes/opt/peepopt_shiftmul_left.pmg
View file

@ -102,7 +102,7 @@ code
}
did_something = true;
log("left shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
log("left shiftmul pattern in %s: shift=%s, mul=%s\n", module, shift, mul);
int const_factor = mul_const.as_int();
int new_const_factor = 1 << factor_bits;

2
passes/opt/peepopt_shiftmul_right.pmg
View file

@ -76,7 +76,7 @@ code
reject;
did_something = true;
log("right shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
log("right shiftmul pattern in %s: shift=%s, mul=%s\n", module, shift, mul);
int const_factor = mul_const.as_int();
int new_const_factor = 1 << factor_bits;

87
passes/opt/peepopt_shiftpow2.pmg Normal file
View file

@ -0,0 +1,87 @@
pattern shiftpow2
//
// Optimize shifts that result from expressions such as foo[s*W+:W]
// when W is a power of two and the multiply has been folded away.
//
match shift
select shift->type.in($shift, $shiftx, $shr)
filter !port(shift, \B).empty()
endmatch
code
{
// make sure the shift amount cannot be negative
SigSpec amount = port(shift, \B);
bool b_signed = shift->type.in($shift, $shiftx) && param(shift, \B_SIGNED).as_bool();
if (!b_signed)
amount.append(State::S0);
if (amount.bits().back() != State::S0)
reject;
while (GetSize(amount) > 1 && amount.bits().back() == State::S0)
amount.remove(GetSize(amount) - 1);
// low zero bits encode the power-of-two scale
int log2scale = 0;
while (!amount.empty() && amount[0] == State::S0) {
amount.remove(0);
log2scale++;
}
if (log2scale < 1)
reject;
if (amount.empty() || amount.is_fully_const())
reject;
SigSpec sel = amount;
int sel_width = GetSize(sel);
int width = param(shift, \Y_WIDTH).as_int();
if (log2scale >= 8 * (int)sizeof(int) - 1)
reject;
int stride = 1 << log2scale;
// avoid overlapping selections
if (width > stride)
reject;
if (sel_width > 20)
reject;
long long ways = 1LL << sel_width;
SigSpec A = port(shift, \A);
int a_width = GetSize(A);
bool a_signed = !shift->type.in($shiftx) && param(shift, \A_SIGNED).as_bool();
int extended_a_width = a_signed ? std::max(a_width, width) : a_width;
// limit padding for out-of-range select values
int max_ratio = module->design->scratchpad_get_int("peepopt.shiftpow2.max_data_multiple", 2);
if (ways * (long long)width > (long long)max_ratio * std::max(a_width, width))
reject;
did_something = true;
log("shiftpow2 pattern in %s: shift=%s, index=%s, stride=%d, width=%d, ways=%lld\n",
module, shift, log_signal(sel), stride, width, ways);
// way m holds A[m*stride +: width], way 0 in the LSBs
State fill = shift->type.in($shiftx) ? State::Sx : State::S0;
SigSpec bmux_a;
for (long long m = 0; m < ways; m++) {
long long base = m * (long long)stride;
for (int b = 0; b < width; b++) {
long long idx = base + b;
if (idx < a_width)
bmux_a.append(A[idx]);
else if (idx < extended_a_width)
bmux_a.append(A.back());
else
bmux_a.append(fill);
}
}
module->addBmux(NEW_ID, bmux_a, sel, port(shift, \Y));
autoremove(shift);
accept;
}
endcode

12
passes/opt/pmux2shiftx.cc
View file

@ -390,7 +390,7 @@ struct Pmux2ShiftxPass : public Pass {
if (verbose) {
printed_pmux_header = true;
log("Inspecting $pmux cell %s/%s.\n", log_id(module), log_id(cell));
log("Inspecting $pmux cell %s/%s.\n", module, cell);
log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
}
@ -441,7 +441,7 @@ struct Pmux2ShiftxPass : public Pass {
if (!printed_pmux_header) {
printed_pmux_header = true;
log("Inspecting $pmux cell %s/%s.\n", log_id(module), log_id(cell));
log("Inspecting $pmux cell %s/%s.\n", module, cell);
log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
}
@ -714,7 +714,7 @@ struct Pmux2ShiftxPass : public Pass {
Cell *c = module->addShiftx(NEW_ID2_SUFFIX("shiftx"), data, shifted_cmp, outsig, false, src);
updated_S.append(en);
updated_B.append(outsig);
log(" created $shiftx cell %s.\n", log_id(c));
log(" created $shiftx cell %s.\n", c);
// remove this sig and continue with the next block
seldb.erase(sig);
@ -799,7 +799,7 @@ struct OnehotPass : public Pass {
continue;
if (verbose)
log("Checking $eq(%s, %s) cell %s/%s.\n", log_signal(A), log_signal(B), log_id(module), log_id(cell));
log("Checking $eq(%s, %s) cell %s/%s.\n", log_signal(A), log_signal(B), module, cell);
if (!onehot_db.query(A)) {
if (verbose)
@ -831,7 +831,7 @@ struct OnehotPass : public Pass {
if (verbose)
log(" replacing with constant 0 driver.\n");
else
log("Replacing one-hot $eq(%s, %s) cell %s/%s with constant 0 driver.\n", log_signal(A), log_signal(B), log_id(module), log_id(cell));
log("Replacing one-hot $eq(%s, %s) cell %s/%s with constant 0 driver.\n", log_signal(A), log_signal(B), module, cell);
module->connect(Y, SigSpec(1, GetSize(Y)));
}
else
@ -840,7 +840,7 @@ struct OnehotPass : public Pass {
if (verbose)
log(" replacing with signal %s.\n", log_signal(sig));
else
log("Replacing one-hot $eq(%s, %s) cell %s/%s with signal %s.\n",log_signal(A), log_signal(B), log_id(module), log_id(cell), log_signal(sig));
log("Replacing one-hot $eq(%s, %s) cell %s/%s with signal %s.\n",log_signal(A), log_signal(B), module, cell, log_signal(sig));
sig.extend_u0(GetSize(Y));
module->connect(Y, sig);
}

171
passes/opt/share.cc
View file

@ -23,6 +23,7 @@
#include "kernel/modtools.h"
#include "kernel/utils.h"
#include "kernel/macc.h"
#include "kernel/newcelltypes.h"
#include <iterator>
USING_YOSYS_NAMESPACE
@ -35,22 +36,20 @@ struct ShareWorkerConfig
{
int limit;
size_t pattern_limit;
bool opt_force;
bool opt_aggressive;
bool opt_fast;
pool<RTLIL::IdString> generic_uni_ops, generic_bin_ops, generic_cbin_ops, generic_other_ops;
StaticCellTypes::Categories::Category generic_uni_ops, generic_bin_ops, generic_cbin_ops, generic_other_ops;
};
struct ShareWorker
{
const ShareWorkerConfig config;
int limit;
pool<RTLIL::IdString> generic_ops;
StaticCellTypes::Categories::Category generic_ops;
RTLIL::Design *design;
RTLIL::Module *module;
CellTypes fwd_ct, cone_ct;
ModWalker modwalker;
pool<RTLIL::Cell*> cells_to_remove;
@ -75,7 +74,7 @@ struct ShareWorker
queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end());
for (auto &it : module->cells_)
if (!fwd_ct.cell_known(it.second->type)) {
if (!StaticCellTypes::Compat::internals_nomem_noff(it.second->type)) {
pool<RTLIL::SigBit> &bits = modwalker.cell_inputs[it.second];
queue_bits.insert(bits.begin(), bits.end());
}
@ -95,7 +94,7 @@ struct ShareWorker
queue_bits.insert(bits.begin(), bits.end());
visited_cells.insert(pbit.cell);
}
if (fwd_ct.cell_known(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) {
if (StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) {
pool<RTLIL::SigBit> &bits = modwalker.cell_inputs[pbit.cell];
terminal_bits.insert(bits.begin(), bits.end());
queue_bits.insert(bits.begin(), bits.end());
@ -363,11 +362,6 @@ struct ShareWorker
not_a_muxed_cell:
continue;
if (config.opt_force) {
shareable_cells.insert(cell);
continue;
}
if (cell->type.in(ID($memrd), ID($memrd_v2))) {
if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
continue;
@ -388,7 +382,7 @@ struct ShareWorker
continue;
}
if (generic_ops.count(cell->type)) {
if (generic_ops(cell->type)) {
if (config.opt_aggressive)
shareable_cells.insert(cell);
continue;
@ -412,7 +406,7 @@ struct ShareWorker
return true;
}
if (config.generic_uni_ops.count(c1->type))
if (config.generic_uni_ops(c1->type))
{
if (!config.opt_aggressive)
{
@ -429,7 +423,7 @@ struct ShareWorker
return true;
}
if (config.generic_bin_ops.count(c1->type) || c1->type == ID($alu))
if (config.generic_bin_ops(c1->type) || c1->type == ID($alu))
{
if (!config.opt_aggressive)
{
@ -449,7 +443,7 @@ struct ShareWorker
return true;
}
if (config.generic_cbin_ops.count(c1->type))
if (config.generic_cbin_ops(c1->type))
{
if (!config.opt_aggressive)
{
@ -511,7 +505,7 @@ struct ShareWorker
{
log_assert(c1->type == c2->type);
if (config.generic_uni_ops.count(c1->type))
if (config.generic_uni_ops(c1->type))
{
if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool())
{
@ -560,11 +554,11 @@ struct ShareWorker
return supercell;
}
if (config.generic_bin_ops.count(c1->type) || config.generic_cbin_ops.count(c1->type) || c1->type == ID($alu))
if (config.generic_bin_ops(c1->type) || config.generic_cbin_ops(c1->type) || c1->type == ID($alu))
{
bool modified_src_cells = false;
if (config.generic_cbin_ops.count(c1->type))
if (config.generic_cbin_ops(c1->type))
{
int score_unflipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int()) +
max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int());
@ -758,7 +752,7 @@ struct ShareWorker
recursion_state.insert(cell);
for (auto c : consumer_cells)
if (fwd_ct.cell_known(c->type)) {
if (StaticCellTypes::Compat::internals_nomem_noff(c->type)) {
const pool<RTLIL::SigBit> &bits = find_forbidden_controls(c);
forbidden_controls_cache[cell].insert(bits.begin(), bits.end());
}
@ -897,7 +891,7 @@ struct ShareWorker
return activation_patterns_cache.at(cell);
}
for (auto &pbit : modwalker.signal_consumers[bit]) {
log_assert(fwd_ct.cell_known(pbit.cell->type));
log_assert(StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type));
if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && (pbit.port == ID::A || pbit.port == ID::B))
driven_data_muxes.insert(pbit.cell);
else
@ -964,7 +958,7 @@ struct ShareWorker
optimize_activation_patterns(activation_patterns_cache[cell]);
if (activation_patterns_cache[cell].empty()) {
log("%sFound cell that is never activated: %s\n", indent, log_id(cell));
log("%sFound cell that is never activated: %s\n", indent, cell);
RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell];
module->connect(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size())));
cells_to_remove.insert(cell);
@ -1129,7 +1123,7 @@ struct ShareWorker
for (auto &loop : toposort.loops) {
log("### loop ###\n");
for (auto &c : loop)
log("%s (%s)\n", log_id(c), log_id(c->type));
log("%s (%s)\n", c, c->type.unescape());
}
return found_scc;
@ -1214,24 +1208,10 @@ struct ShareWorker
ShareWorker(ShareWorkerConfig config, RTLIL::Design* design) :
config(config), design(design), modwalker(design)
{
generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end());
generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end());
generic_ops.insert(config.generic_cbin_ops.begin(), config.generic_cbin_ops.end());
generic_ops.insert(config.generic_other_ops.begin(), config.generic_other_ops.end());
fwd_ct.setup_internals();
cone_ct.setup_internals();
cone_ct.cell_types.erase(ID($mul));
cone_ct.cell_types.erase(ID($mod));
cone_ct.cell_types.erase(ID($div));
cone_ct.cell_types.erase(ID($modfloor));
cone_ct.cell_types.erase(ID($divfloor));
cone_ct.cell_types.erase(ID($pow));
cone_ct.cell_types.erase(ID($shl));
cone_ct.cell_types.erase(ID($shr));
cone_ct.cell_types.erase(ID($sshl));
cone_ct.cell_types.erase(ID($sshr));
generic_ops = StaticCellTypes::Categories::join(generic_ops, config.generic_uni_ops);
generic_ops = StaticCellTypes::Categories::join(generic_ops, config.generic_bin_ops);
generic_ops = StaticCellTypes::Categories::join(generic_ops, config.generic_cbin_ops);
generic_ops = StaticCellTypes::Categories::join(generic_ops, config.generic_other_ops);
}
void operator()(RTLIL::Module *module) {
@ -1260,14 +1240,14 @@ struct ShareWorker
return;
log("Found %d cells in module %s that may be considered for resource sharing.\n",
GetSize(shareable_cells), log_id(module));
GetSize(shareable_cells), module);
while (!shareable_cells.empty() && config.limit != 0)
{
RTLIL::Cell *cell = *shareable_cells.begin();
shareable_cells.erase(cell);
log(" Analyzing resource sharing options for %s (%s):\n", log_id(cell), log_id(cell->type));
log(" Analyzing resource sharing options for %s (%s):\n", cell, cell->type.unescape());
const pool<ssc_pair_t> &cell_activation_patterns = find_cell_activation_patterns(cell, " ");
RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns);
@ -1295,12 +1275,12 @@ struct ShareWorker
log(" Found %d candidates:", GetSize(candidates));
for (auto c : candidates)
log(" %s", log_id(c));
log(" %s", c);
log("\n");
for (auto other_cell : candidates)
{
log(" Analyzing resource sharing with %s (%s):\n", log_id(other_cell), log_id(other_cell->type));
log(" Analyzing resource sharing with %s (%s):\n", other_cell, other_cell->type.unescape());
const pool<ssc_pair_t> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell, " ");
RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns);
@ -1352,13 +1332,13 @@ struct ShareWorker
RTLIL::SigSpec all_ctrl_signals;
for (auto &p : filtered_cell_activation_patterns) {
log(" Activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second));
log(" Activation pattern for cell %s: %s = %s\n", cell, log_signal(p.first), log_signal(p.second));
cell_active.push_back(qcsat.ez->vec_eq(qcsat.importSig(p.first), qcsat.importSig(p.second)));
all_ctrl_signals.append(p.first);
}
for (auto &p : filtered_other_cell_activation_patterns) {
log(" Activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second));
log(" Activation pattern for cell %s: %s = %s\n", other_cell, log_signal(p.first), log_signal(p.second));
other_cell_active.push_back(qcsat.ez->vec_eq(qcsat.importSig(p.first), qcsat.importSig(p.second)));
all_ctrl_signals.append(p.first);
}
@ -1369,13 +1349,13 @@ struct ShareWorker
qcsat.prepare();
if (!qcsat.ez->solve(sub1)) {
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(cell));
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", cell);
cells_to_remove.insert(cell);
break;
}
if (!qcsat.ez->solve(sub2)) {
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(other_cell));
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", other_cell);
cells_to_remove.insert(other_cell);
shareable_cells.erase(other_cell);
continue;
@ -1411,20 +1391,20 @@ struct ShareWorker
if (restrict_activation_patterns(optimized_cell_activation_patterns, optimized_other_cell_activation_patterns)) {
for (auto &p : optimized_cell_activation_patterns)
log(" Simplified activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second));
log(" Simplified activation pattern for cell %s: %s = %s\n", cell, log_signal(p.first), log_signal(p.second));
for (auto &p : optimized_other_cell_activation_patterns)
log(" Simplified activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second));
log(" Simplified activation pattern for cell %s: %s = %s\n", other_cell, log_signal(p.first), log_signal(p.second));
}
}
if (find_in_input_cone(cell, other_cell)) {
log(" Sharing not possible: %s is in input cone of %s.\n", log_id(other_cell), log_id(cell));
log(" Sharing not possible: %s is in input cone of %s.\n", other_cell, cell);
continue;
}
if (find_in_input_cone(other_cell, cell)) {
log(" Sharing not possible: %s is in input cone of %s.\n", log_id(cell), log_id(other_cell));
log(" Sharing not possible: %s is in input cone of %s.\n", cell, other_cell);
continue;
}
@ -1444,14 +1424,14 @@ struct ShareWorker
if (cell_select_score <= other_cell_select_score) {
RTLIL::SigSpec act = make_cell_activation_logic(optimized_cell_activation_patterns, supercell_aux);
supercell = make_supercell(cell, other_cell, act, supercell_aux);
log(" Activation signal for %s: %s\n", log_id(cell), log_signal(act));
log(" Activation signal for %s: %s\n", cell, log_signal(act));
} else {
RTLIL::SigSpec act = make_cell_activation_logic(optimized_other_cell_activation_patterns, supercell_aux);
supercell = make_supercell(other_cell, cell, act, supercell_aux);
log(" Activation signal for %s: %s\n", log_id(other_cell), log_signal(act));
log(" Activation signal for %s: %s\n", other_cell, log_signal(act));
}
log(" New cell: %s (%s)\n", log_id(supercell), log_id(supercell->type));
log(" New cell: %s (%s)\n", supercell, supercell->type.unescape());
cells_to_remove.insert(cell);
cells_to_remove.insert(other_cell);
@ -1496,9 +1476,9 @@ struct ShareWorker
}
if (!cells_to_remove.empty()) {
log("Removing %d cells in module %s:\n", GetSize(cells_to_remove), log_id(module));
log("Removing %d cells in module %s:\n", GetSize(cells_to_remove), module);
for (auto c : cells_to_remove) {
log(" Removing cell %s (%s).\n", log_id(c), log_id(c->type));
log(" Removing cell %s (%s).\n", c, c->type.unescape());
remove_cell(c);
}
}
@ -1523,14 +1503,6 @@ struct SharePass : public Pass {
log("This pass merges shareable resources into a single resource. A SAT solver\n");
log("is used to determine if two resources are share-able.\n");
log("\n");
log(" -force\n");
log(" Per default the selection of cells that is considered for sharing is\n");
log(" narrowed using a list of cell types. With this option all selected\n");
log(" cells are considered for resource sharing.\n");
log("\n");
log(" IMPORTANT NOTE: If the -all option is used then no cells with internal\n");
log(" state must be selected!\n");
log("\n");
log(" -aggressive\n");
log(" Per default some heuristics are used to reduce the number of cells\n");
log(" considered for resource sharing to only large resources. This options\n");
@ -1557,58 +1529,53 @@ struct SharePass : public Pass {
config.limit = -1;
config.pattern_limit = design->scratchpad_get_int("share.pattern_limit", 1000);
config.opt_force = false;
config.opt_aggressive = false;
config.opt_fast = false;
config.generic_uni_ops.insert(ID($not));
// config.generic_uni_ops.insert(ID($pos));
config.generic_uni_ops.insert(ID($neg));
config.generic_uni_ops.set_id(ID($not));
// config.generic_uni_ops.set_id(ID($pos));
config.generic_uni_ops.set_id(ID($neg));
config.generic_cbin_ops.insert(ID($and));
config.generic_cbin_ops.insert(ID($or));
config.generic_cbin_ops.insert(ID($xor));
config.generic_cbin_ops.insert(ID($xnor));
config.generic_cbin_ops.set_id(ID($and));
config.generic_cbin_ops.set_id(ID($or));
config.generic_cbin_ops.set_id(ID($xor));
config.generic_cbin_ops.set_id(ID($xnor));
config.generic_bin_ops.insert(ID($shl));
config.generic_bin_ops.insert(ID($shr));
config.generic_bin_ops.insert(ID($sshl));
config.generic_bin_ops.insert(ID($sshr));
config.generic_bin_ops.set_id(ID($shl));
config.generic_bin_ops.set_id(ID($shr));
config.generic_bin_ops.set_id(ID($sshl));
config.generic_bin_ops.set_id(ID($sshr));
config.generic_bin_ops.insert(ID($lt));
config.generic_bin_ops.insert(ID($le));
config.generic_bin_ops.insert(ID($eq));
config.generic_bin_ops.insert(ID($ne));
config.generic_bin_ops.insert(ID($eqx));
config.generic_bin_ops.insert(ID($nex));
config.generic_bin_ops.insert(ID($ge));
config.generic_bin_ops.insert(ID($gt));
config.generic_bin_ops.set_id(ID($lt));
config.generic_bin_ops.set_id(ID($le));
config.generic_bin_ops.set_id(ID($eq));
config.generic_bin_ops.set_id(ID($ne));
config.generic_bin_ops.set_id(ID($eqx));
config.generic_bin_ops.set_id(ID($nex));
config.generic_bin_ops.set_id(ID($ge));
config.generic_bin_ops.set_id(ID($gt));
config.generic_cbin_ops.insert(ID($add));
config.generic_cbin_ops.insert(ID($mul));
config.generic_cbin_ops.set_id(ID($add));
config.generic_cbin_ops.set_id(ID($mul));
config.generic_bin_ops.insert(ID($sub));
config.generic_bin_ops.insert(ID($div));
config.generic_bin_ops.insert(ID($mod));
config.generic_bin_ops.insert(ID($divfloor));
config.generic_bin_ops.insert(ID($modfloor));
// config.generic_bin_ops.insert(ID($pow));
config.generic_bin_ops.set_id(ID($sub));
config.generic_bin_ops.set_id(ID($div));
config.generic_bin_ops.set_id(ID($mod));
config.generic_bin_ops.set_id(ID($divfloor));
config.generic_bin_ops.set_id(ID($modfloor));
// config.generic_bin_ops.set_id(ID($pow));
config.generic_uni_ops.insert(ID($logic_not));
config.generic_cbin_ops.insert(ID($logic_and));
config.generic_cbin_ops.insert(ID($logic_or));
config.generic_uni_ops.set_id(ID($logic_not));
config.generic_cbin_ops.set_id(ID($logic_and));
config.generic_cbin_ops.set_id(ID($logic_or));
config.generic_other_ops.insert(ID($alu));
config.generic_other_ops.insert(ID($macc));
config.generic_other_ops.set_id(ID($alu));
config.generic_other_ops.set_id(ID($macc));
log_header(design, "Executing SHARE pass (SAT-based resource sharing).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-force") {
config.opt_force = true;
continue;
}
if (args[argidx] == "-aggressive") {
config.opt_aggressive = true;
continue;

28
passes/opt/wreduce.cc
View file

@ -107,14 +107,14 @@ struct WreduceWorker
sig_removed.append(bits_removed[i]);
if (GetSize(bits_removed) == GetSize(sig_y)) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
module->connect(sig_y, sig_removed);
module->remove(cell);
return;
}
log_debug("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n",
GetSize(sig_removed), GetSize(sig_y), log_id(module), log_id(cell), log_id(cell->type));
GetSize(sig_removed), GetSize(sig_y), module, cell, cell->type.unescape());
int n_removed = GetSize(sig_removed);
int n_kept = GetSize(sig_y) - GetSize(sig_removed);
@ -207,13 +207,13 @@ struct WreduceWorker
return;
if (GetSize(sig_q) == 0) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
module->remove(cell);
return;
}
log_debug("Removed top %d bits (of %d) from FF cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before,
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
for (auto bit : sig_d)
work_queue_bits.insert(bit);
@ -261,7 +261,7 @@ struct WreduceWorker
if (bits_removed) {
log_debug("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n",
bits_removed, GetSize(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type));
bits_removed, GetSize(sig) + bits_removed, port, module, cell, cell->type.unescape());
cell->setPort(stringf("\\%c", port), sig);
did_something = true;
}
@ -334,7 +334,7 @@ struct WreduceWorker
if (!port_a_signed && !port_b_signed && signed_cost < unsigned_cost) {
log_debug("Converting cell %s.%s (%s) from unsigned to signed.\n",
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
cell->setParam(ID::A_SIGNED, 1);
cell->setParam(ID::B_SIGNED, 1);
port_a_signed = true;
@ -342,7 +342,7 @@ struct WreduceWorker
did_something = true;
} else if (port_a_signed && port_b_signed && unsigned_cost < signed_cost) {
log_debug("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
cell->setParam(ID::A_SIGNED, 0);
cell->setParam(ID::B_SIGNED, 0);
port_a_signed = false;
@ -362,7 +362,7 @@ struct WreduceWorker
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 &&
GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
log_debug("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
cell->setParam(ID::A_SIGNED, 0);
cell->setParam(ID::B_SIGNED, 0);
port_a_signed = false;
@ -375,7 +375,7 @@ struct WreduceWorker
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A));
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
log_debug("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
cell->setParam(ID::A_SIGNED, 0);
port_a_signed = false;
did_something = true;
@ -436,14 +436,14 @@ struct WreduceWorker
}
if (GetSize(sig) == 0) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
module->remove(cell);
return;
}
if (bits_removed) {
log_debug("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
bits_removed, GetSize(sig) + bits_removed, module, cell, cell->type.unescape());
cell->setPort(ID::Y, sig);
did_something = true;
}
@ -637,7 +637,7 @@ struct WreducePass : public Pass {
}
if (original_a_width != GetSize(A)) {
log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n",
original_a_width-GetSize(A), original_a_width, log_id(module), log_id(c), log_id(c->type));
original_a_width-GetSize(A), original_a_width, module, c, c->type.unescape());
c->setPort(ID::A, A);
c->setParam(ID::A_WIDTH, GetSize(A));
}
@ -653,7 +653,7 @@ struct WreducePass : public Pass {
}
if (original_b_width != GetSize(B)) {
log_debug("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n",
original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type));
original_b_width-GetSize(B), original_b_width, module, c, c->type.unescape());
c->setPort(ID::B, B);
c->setParam(ID::B_WIDTH, GetSize(B));
}
@ -669,7 +669,7 @@ struct WreducePass : public Pass {
log_debug("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n",
cur_addrbits-max_addrbits, cur_addrbits,
c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init",
log_id(module), log_id(c), log_id(memid));
module, c, memid.unescape());
c->setParam(ID::ABITS, max_addrbits);
c->setPort(ID::ADDR, c->getPort(ID::ADDR).extract(0, max_addrbits));
}