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Merge remote-tracking branch 'upstream/main' into silimate

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Mohamed Gaber 2026-06-09 16:22:51 +03:00
commit e58125b605
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213
passes/cmds/CMakeLists.txt Normal file
View file

@ -0,0 +1,213 @@
add_subdirectory(sdc)
yosys_pass(exec
exec.cc
ENABLE_IF
YOSYS_ENABLE_SPAWN
)
yosys_pass(add
add.cc
)
yosys_pass(delete
delete.cc
)
yosys_pass(design
design.cc
ESSENTIAL
)
yosys_pass(design_equal
design_equal.cc
)
yosys_pass(select
select.cc
PROVIDES
cd
ls
ESSENTIAL
)
yosys_pass(show
show.cc
LIBRARIES
$<${YOSYS_ENABLE_READLINE}:PkgConfig::readline>
$<${YOSYS_ENABLE_EDITLINE}:PkgConfig::editline>
REQUIRES
read_rtlil
read_verilog
)
yosys_pass(viz
viz.cc
)
yosys_pass(rename
rename.cc
REQUIRES
write_verilog
)
yosys_pass(autoname
autoname.cc
)
yosys_pass(connect
connect.cc
)
yosys_pass(scatter
scatter.cc
)
yosys_pass(setundef
setundef.cc
)
yosys_pass(splitnets
splitnets.cc
)
yosys_pass(splitcells
splitcells.cc
)
yosys_pass(stat
stat.cc
REQUIRES
libparse
)
yosys_pass(internal_stats
internal_stats.cc
REQUIRES
libparse
)
yosys_pass(setattr
setattr.cc
PROVIDES
wbflip
setparam
chparam
)
yosys_pass(copy
copy.cc
)
yosys_pass(splice
splice.cc
)
yosys_pass(scc
scc.cc
)
yosys_pass(glift
glift.cc
)
yosys_pass(torder
torder.cc
)
yosys_pass(logcmd
logcmd.cc
)
yosys_pass(tee
tee.cc
)
yosys_pass(write_file
write_file.cc
)
yosys_pass(connwrappers
connwrappers.cc
)
yosys_pass(trace
trace.cc
PROVIDES
debug
)
yosys_pass(plugin
plugin.cc
INCLUDE_DIRS
${pybind11_INCLUDE_DIR}
LIBRARIES
$<${YOSYS_ENABLE_PLUGINS}:${Dlfcn_LIBRARIES}>
$<${YOSYS_ENABLE_PYTHON}:Python3::Module>
ESSENTIAL
)
yosys_pass(check
check.cc
)
yosys_pass(edgetypes
edgetypes.cc
)
yosys_pass(portlist
portlist.cc
)
yosys_pass(chformal
chformal.cc
)
yosys_pass(chtype
chtype.cc
)
yosys_pass(blackbox
blackbox.cc
)
yosys_pass(ltp
ltp.cc
)
yosys_pass(linux_perf
linux_perf.cc
)
yosys_pass(bugpoint
bugpoint.cc
REQUIRES
proc_clean
opt_clean
design
ENABLE_IF
YOSYS_ENABLE_SPAWN
)
yosys_pass(scratchpad
scratchpad.cc
)
yosys_pass(logger
logger.cc
)
yosys_pass(printattrs
printattrs.cc
)
yosys_pass(sta
sta.cc
)
yosys_pass(clean_zerowidth
clean_zerowidth.cc
)
yosys_pass(xprop
xprop.cc
REQUIRES
bmuxmap
demuxmap
)
yosys_pass(dft_tag
dft_tag.cc
)
yosys_pass(future
future.cc
)
yosys_pass(box_derive
box_derive.cc
)
yosys_pass(example_dt
example_dt.cc
)
yosys_pass(portarcs
portarcs.cc
)
yosys_pass(wrapcell
wrapcell.cc
)
yosys_pass(setenv
setenv.cc
)
yosys_pass(abstract
abstract.cc
)
yosys_pass(test_select
test_select.cc
)
yosys_pass(timeest
timeest.cc
)
yosys_pass(linecoverage
linecoverage.cc
)
yosys_pass(sort
sort.cc
)
yosys_pass(icell_liberty
icell_liberty.cc
)

64
passes/cmds/Makefile.inc
View file

@ -1,64 +0,0 @@
ifeq ($(DISABLE_SPAWN),0)
OBJS += passes/cmds/exec.o
endif
OBJS += passes/cmds/add.o
OBJS += passes/cmds/delete.o
OBJS += passes/cmds/design.o
OBJS += passes/cmds/design_equal.o
OBJS += passes/cmds/select.o
OBJS += passes/cmds/show.o
OBJS += passes/cmds/viz.o
OBJS += passes/cmds/rename.o
OBJS += passes/cmds/autoname.o
OBJS += passes/cmds/connect.o
OBJS += passes/cmds/scatter.o
OBJS += passes/cmds/setundef.o
OBJS += passes/cmds/splitnets.o
OBJS += passes/cmds/splitcells.o
OBJS += passes/cmds/stat.o
OBJS += passes/cmds/internal_stats.o
OBJS += passes/cmds/setattr.o
OBJS += passes/cmds/copy.o
OBJS += passes/cmds/splice.o
OBJS += passes/cmds/scc.o
OBJS += passes/cmds/glift.o
OBJS += passes/cmds/torder.o
OBJS += passes/cmds/logcmd.o
OBJS += passes/cmds/tee.o
OBJS += passes/cmds/write_file.o
OBJS += passes/cmds/connwrappers.o
OBJS += passes/cmds/trace.o
OBJS += passes/cmds/plugin.o
OBJS += passes/cmds/check.o
OBJS += passes/cmds/edgetypes.o
OBJS += passes/cmds/portlist.o
OBJS += passes/cmds/chformal.o
OBJS += passes/cmds/chtype.o
OBJS += passes/cmds/blackbox.o
OBJS += passes/cmds/ltp.o
OBJS += passes/cmds/linux_perf.o
ifeq ($(DISABLE_SPAWN),0)
OBJS += passes/cmds/bugpoint.o
endif
OBJS += passes/cmds/scratchpad.o
OBJS += passes/cmds/logger.o
OBJS += passes/cmds/printattrs.o
OBJS += passes/cmds/sta.o
OBJS += passes/cmds/clean_zerowidth.o
OBJS += passes/cmds/xprop.o
OBJS += passes/cmds/dft_tag.o
OBJS += passes/cmds/future.o
OBJS += passes/cmds/box_derive.o
OBJS += passes/cmds/example_dt.o
OBJS += passes/cmds/portarcs.o
OBJS += passes/cmds/wrapcell.o
OBJS += passes/cmds/setenv.o
OBJS += passes/cmds/abstract.o
OBJS += passes/cmds/test_select.o
OBJS += passes/cmds/timeest.o
OBJS += passes/cmds/linecoverage.o
OBJS += passes/cmds/sort.o
OBJS += passes/cmds/icell_liberty.o
include $(YOSYS_SRC)/passes/cmds/sdc/Makefile.inc

9
passes/cmds/abstract.cc
View file

@ -67,7 +67,7 @@ struct Slice {
int wire_offset(RTLIL::Wire *wire, int index) const {
int rtl_offset = indices == RtlilSlice ? index : wire->from_hdl_index(index);
if (rtl_offset < 0 || rtl_offset >= wire->width) {
log_error("Slice %s is out of bounds for wire %s in module %s", to_string(), log_id(wire), log_id(wire->module));
log_error("Slice %s is out of bounds for wire %s in module %s", to_string(), wire, wire->module);
}
return rtl_offset;
}
@ -187,7 +187,7 @@ unsigned int abstract_state(Module* mod, EnableLogic enable, const std::vector<S
for (int i = 0; i < GetSize(ff.sig_q); i++) {
SigBit bit = ff.sig_q[i];
if (selected_reps.count(sigmap(bit))) {
log_debug("Abstracting state for %s.Q[%i] in module %s due to selections:\n", log_id(ff.cell), i, log_id(mod));
log_debug("Abstracting state for %s.Q[%i] in module %s due to selections:\n", ff.cell, i, mod);
explain_selections(selected_reps.at(sigmap(bit)));
offsets_to_abstract.insert(i);
}
@ -271,7 +271,7 @@ unsigned int abstract_value(Module* mod, EnableLogic enable, const std::vector<S
for (int i = 0; i < conn.second.size(); i++) {
if (selected_reps.count(sigmap(conn.second[i]))) {
log_debug("Abstracting value for %s.%s[%i] in module %s due to selections:\n",
log_id(cell), log_id(conn.first), i, log_id(mod));
cell, conn.first.unescape(), i, mod);
explain_selections(selected_reps.at(sigmap(conn.second[i])));
offsets_to_abstract.insert(i);
}
@ -289,7 +289,7 @@ unsigned int abstract_value(Module* mod, EnableLogic enable, const std::vector<S
for (auto bit : SigSpec(wire))
if (selected_reps.count(sigmap(bit))) {
log_debug("Abstracting value for module input port bit %s in module %s due to selections:\n",
log_signal(bit), log_id(mod));
log_signal(bit), mod);
explain_selections(selected_reps.at(sigmap(bit)));
offsets_to_abstract.insert(bit.offset);
}
@ -469,6 +469,7 @@ struct AbstractPass : public Pass {
switch (enable) {
case Enable::Always:
log_assert(false);
YS_FALLTHROUGH
case Enable::ActiveLow:
case Enable::ActiveHigh: {
if (enable_name.empty())

10
passes/cmds/autoname.cc
View file

@ -48,7 +48,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
for (auto bit : conn.second)
if (bit.wire != nullptr && bit.wire->name[0] != '$') {
if (suffix.empty())
suffix = stringf("_%s_%s", log_id(cell->type), log_id(conn.first));
suffix = stringf("_%s_%s", cell->type.unescape(), conn.first.unescape());
name_proposal proposed_name(
bit.wire->name.str() + suffix,
cell->output(conn.first) ? 0 : wire_score.at(bit.wire)
@ -66,7 +66,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
for (auto bit : conn.second)
if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) {
if (suffix.empty())
suffix = stringf("_%s", log_id(conn.first));
suffix = stringf("_%s", conn.first.unescape());
name_proposal proposed_name(
cell->name.str() + suffix,
cell->output(conn.first) ? 0 : wire_score.at(bit.wire)
@ -90,7 +90,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
if (best_name < it.second)
continue;
IdString n = module->uniquify(IdString(it.second.name));
log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
log_debug("Rename cell %s in %s to %s.\n", it.first, module, n.unescape());
module->rename(it.first, n);
count++;
}
@ -99,7 +99,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
if (best_name < it.second)
continue;
IdString n = module->uniquify(IdString(it.second.name));
log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
log_debug("Rename wire %s in %s to %s.\n", it.first, module, n.unescape());
module->rename(it.first, n);
count++;
}
@ -151,7 +151,7 @@ struct AutonamePass : public Pass {
count += n;
}
if (count > 0)
log("Renamed %d objects in module %s (%d iterations).\n", count, log_id(module), iter);
log("Renamed %d objects in module %s (%d iterations).\n", count, module, iter);
}
}
} AutonamePass;

4
passes/cmds/box_derive.cc
View file

@ -79,7 +79,7 @@ struct BoxDerivePass : Pass {
if (!base_name.empty()) {
base_override = d->module(base_name);
if (!base_override)
log_cmd_error("Base module %s not found.\n", log_id(base_name));
log_cmd_error("Base module %s not found.\n", base_name.unescape());
}
dict<std::pair<RTLIL::IdString, dict<RTLIL::IdString, RTLIL::Const>>, Module*> done;
@ -109,7 +109,7 @@ struct BoxDerivePass : Pass {
IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr));
if (!new_name.isPublic())
log_error("Derived module %s cannot be renamed to private name %s.\n",
log_id(derived), log_id(new_name));
derived, new_name.unescape());
derived->attributes.erase(naming_attr);
d->rename(derived, new_name);
}

20
passes/cmds/bugpoint.cc
View file

@ -212,7 +212,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove module %s.\n", log_id(module));
log_header(design, "Trying to remove module %s.\n", module);
removed_module = module;
break;
}
@ -242,7 +242,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove module port %s.\n", log_id(wire));
log_header(design, "Trying to remove module port %s.\n", wire);
wire->port_input = wire->port_output = false;
mod->fixup_ports();
return design_copy;
@ -265,7 +265,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove cell %s.%s.\n", log_id(mod), log_id(cell));
log_header(design, "Trying to remove cell %s.%s.\n", mod, cell);
removed_cell = cell;
break;
}
@ -296,7 +296,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove cell port %s.%s.%s.\n", log_id(mod), log_id(cell), log_id(it.first));
log_header(design, "Trying to remove cell port %s.%s.%s.\n", mod, cell, it.first.unescape());
RTLIL::SigSpec port_x(State::Sx, port.size());
cell->unsetPort(it.first);
cell->setPort(it.first, port_x);
@ -305,7 +305,7 @@ struct BugpointPass : public Pass {
if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed)
{
log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", log_id(mod), log_id(cell), log_id(it.first));
log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", mod, cell, it.first.unescape());
RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
wire->set_bool_attribute(ID($bugpoint));
wire->port_input = cell->input(it.first);
@ -334,7 +334,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove process %s.%s.\n", log_id(mod), log_id(process.first));
log_header(design, "Trying to remove process %s.%s.\n", mod, process.first.unescape());
removed_process = process.second;
break;
}
@ -363,7 +363,7 @@ struct BugpointPass : public Pass {
{
if (index++ == seed)
{
log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->first), log_signal(it->second), log_id(mod), log_id(pr.first));
log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->first), log_signal(it->second), mod, pr.first.unescape());
cs->actions.erase(it);
return design_copy;
}
@ -389,7 +389,7 @@ struct BugpointPass : public Pass {
{
if (index++ == seed)
{
log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->first), log_signal(it->second), log_id(mod), log_id(pr.first));
log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->first), log_signal(it->second), mod, pr.first.unescape());
sy->actions.erase(it);
return design_copy;
}
@ -399,7 +399,7 @@ struct BugpointPass : public Pass {
{
if (index++ == seed)
{
log_header(design, "Trying to remove sync %s memwr %s %s %s %s in %s.%s.\n", log_signal(sy->signal), log_id(it->memid), log_signal(it->address), log_signal(it->data), log_signal(it->enable), log_id(mod), log_id(pr.first));
log_header(design, "Trying to remove sync %s memwr %s %s %s %s in %s.%s.\n", log_signal(sy->signal), it->memid.unescape(), log_signal(it->address), log_signal(it->data), log_signal(it->enable), mod, pr.first.unescape());
sy->mem_write_actions.erase(it);
// Remove the bit for removed action from other actions' priority masks.
for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) {
@ -437,7 +437,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove wire %s.%s.\n", log_id(mod), log_id(wire));
log_header(design, "Trying to remove wire %s.%s.\n", mod, wire);
removed_wire = wire;
break;
}

126
passes/cmds/check.cc
View file

@ -20,9 +20,10 @@
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/celledges.h"
#include "kernel/celltypes.h"
#include "kernel/newcelltypes.h"
#include "kernel/utils.h"
#include "kernel/log_help.h"
#include "kernel/mem.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -117,7 +118,7 @@ struct CheckPass : public Pass {
for (auto module : design->selected_whole_modules_warn())
{
log("Checking module %s...\n", log_id(module));
log("Checking module %s...\n", module);
SigMap sigmap(module);
dict<SigBit, vector<string>> wire_drivers;
@ -133,7 +134,7 @@ struct CheckPass : public Pass {
for (auto bit : sigmap(action.first))
wire_drivers[bit].push_back(
stringf("action %s <= %s (case rule) in process %s",
log_signal(action.first), log_signal(action.second), log_id(proc_it.first)));
log_signal(action.first), log_signal(action.second), proc_it.first.unescape()));
for (auto bit : sigmap(action.second))
if (bit.wire) used_wires.insert(bit);
@ -154,7 +155,7 @@ struct CheckPass : public Pass {
for (auto bit : sigmap(action.first))
wire_drivers[bit].push_back(
stringf("action %s <= %s (sync rule) in process %s",
log_signal(action.first), log_signal(action.second), log_id(proc_it.first)));
log_signal(action.first), log_signal(action.second), proc_it.first.unescape()));
for (auto bit : sigmap(action.second))
if (bit.wire) used_wires.insert(bit);
}
@ -259,7 +260,7 @@ struct CheckPass : public Pass {
{
if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
if (allow_tbuf && cell->type == ID($_TBUF_)) goto cell_allowed;
log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", log_id(module), log_id(cell), log_id(cell->type));
log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", module, cell, cell->type.unescape());
counter++;
cell_allowed:;
}
@ -275,10 +276,10 @@ struct CheckPass : public Pass {
if (input && bit.wire)
used_wires.insert(bit);
if (output && !input && bit.wire)
wire_drivers_count[bit]++;
wire_drivers_count[bit]++;
if (output && (bit.wire || !input))
wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", log_id(conn.first), i,
log_id(cell), log_id(cell->type)));
wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", conn.first.unescape(), i,
cell, cell->type.unescape()));
if (output)
driver_cells[bit] = cell;
}
@ -298,7 +299,7 @@ struct CheckPass : public Pass {
SigSpec sig = sigmap(wire);
for (int i = 0; i < GetSize(sig); i++)
if (sig[i].wire || !wire->port_output)
wire_drivers[sig[i]].push_back(stringf("module input %s[%d]", log_id(wire), i));
wire_drivers[sig[i]].push_back(stringf("module input %s[%d]", wire, i));
}
if (wire->port_output)
for (auto bit : sigmap(wire))
@ -312,7 +313,7 @@ struct CheckPass : public Pass {
if (initval[i] == State::S0 || initval[i] == State::S1)
init_bits.insert(sigmap(SigBit(wire, i)));
if (noinit) {
log_warning("Wire %s.%s has an unprocessed 'init' attribute.\n", log_id(module), log_id(wire));
log_warning("Wire %s.%s has an unprocessed 'init' attribute.\n", module, wire);
counter++;
}
}
@ -329,7 +330,7 @@ struct CheckPass : public Pass {
for (auto it : wire_drivers)
if (wire_drivers_count[it.first] > 1) {
string message = stringf("multiple conflicting drivers for %s.%s:\n", log_id(module), log_signal(it.first));
string message = stringf("multiple conflicting drivers for %s.%s:\n", module, log_signal(it.first));
for (auto str : it.second)
message += stringf(" %s\n", str);
log_warning("%s", message);
@ -338,13 +339,13 @@ struct CheckPass : public Pass {
for (auto bit : used_wires)
if (!wire_drivers.count(bit)) {
log_warning("Wire %s.%s is used but has no driver.\n", log_id(module), log_signal(bit));
log_warning("Wire %s.%s is used but has no driver.\n", module, log_signal(bit));
counter++;
}
topo.sort();
for (auto &loop : topo.loops) {
string message = stringf("found logic loop in module %s:\n", log_id(module));
string message = stringf("found logic loop in module %s:\n", module);
// `loop` only contains wire bits, or an occasional special helper node for cells for
// which we have done the edges fallback. The cell and its ports that led to an edge are
@ -378,8 +379,8 @@ struct CheckPass : public Pass {
SigBit edge_to = sigmap(cell->getPort(to_port))[to_bit];
if (edge_from == from && edge_to == to && nhits++ < HITS_LIMIT)
message += stringf(" %s[%d] --> %s[%d]\n", log_id(from_port), from_bit,
log_id(to_port), to_bit);
message += stringf(" %s[%d] --> %s[%d]\n", from_port.unescape(), from_bit,
to_port.unescape(), to_bit);
if (nhits == HITS_LIMIT)
message += " ...\n";
}
@ -397,7 +398,7 @@ struct CheckPass : public Pass {
driver_src = stringf(" source: %s", src_attr);
}
message += stringf(" cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src);
message += stringf(" cell %s (%s)%s\n", driver, driver->type.unescape(), driver_src);
if (!coarsened_cells.count(driver)) {
MatchingEdgePrinter printer(message, sigmap, prev, bit);
@ -437,7 +438,7 @@ struct CheckPass : public Pass {
init_sig.sort_and_unify();
for (auto chunk : init_sig.chunks()) {
log_warning("Wire %s.%s has 'init' attribute and is not driven by an FF cell.\n", log_id(module), log_signal(chunk));
log_warning("Wire %s.%s has 'init' attribute and is not driven by an FF cell.\n", module, log_signal(chunk));
counter++;
}
}
@ -453,4 +454,95 @@ struct CheckPass : public Pass {
}
} CheckPass;
struct CheckMemPass : public Pass {
CheckMemPass() : Pass("check_mem", "check for obvious memory problems in the design") { }
bool formatted_help() override {
auto *help = PrettyHelp::get_current();
help->set_group("passes/status");
auto content_root = help->get_root();
content_root->usage("check_mem [selection]");
content_root->paragraph(
"This pass identifies the following problems in the current design: "
"addressing invalid memory."
);
content_root->option("-non-const", "also check non-const address signals (may produce false-positives)");
content_root->option("-assert", "produce a runtime error if any problems are found in the current design");
return true;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
int counter = 0;
bool assert_mode = false;
bool nonconst_mode = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-assert") {
assert_mode = true;
continue;
}
if (args[argidx] == "-non-const") {
nonconst_mode = true;
continue;
}
break;
}
extra_args(args, argidx, design);
log_header(design, "Executing CHECK_MEM pass.\n");
for (auto *module : design->selected_unboxed_modules_warn()) {
for (auto mem : Mem::get_selected_memories(module)) {
int min_addr = mem.mem->start_offset;
int max_addr = mem.mem->size + min_addr - 1;
for (auto &init : mem.inits) {
int start = init.addr.as_int();
if (start < min_addr) {
log_warning("Mem %s.%s starts at %d but initializes address %d.\n", log_id(module), log_id(mem.mem), min_addr, start);
counter++;
}
int end = start + (GetSize(init.data) / mem.width) - 1;
if (end > max_addr) {
log_warning("Mem %s.%s ends at %d but initializes address %d.\n", log_id(module), log_id(mem.mem), max_addr, end);
counter++;
}
}
auto check_addr = [min_addr, max_addr, &counter, module, &mem, &nonconst_mode](SigSpec &addr_sig, const char* access) {
if (addr_sig.is_fully_const()) {
auto addr = addr_sig.as_int();
if (addr < min_addr || addr > max_addr) {
log_warning("Mem %s.%s contains entries for addresses %d..%d but %s address %d.\n", log_id(module), log_id(mem.mem), min_addr, max_addr, access, addr);
counter++;
}
} else if (nonconst_mode) {
// TODO check addr_sig.has_const() for constant MSb/LSb that may change effective min/max
// TODO consider sat solver for variable addresses
int addr_sig_min = 0;
int addr_sig_max = (1 << addr_sig.size()) - 1;
if (min_addr > addr_sig_min || max_addr < addr_sig_max) {
log_warning("Mem %s.%s contains entries for addresses %d..%d but has a potentially dangerous non-const input %s\n", log_id(module), log_id(mem.mem), min_addr, max_addr, log_signal(addr_sig));
counter++;
}
}
};
// TODO test ABITS and WIDTH?
// TODO can we limit ports via selection?
for (auto &rd_port : mem.rd_ports)
check_addr(rd_port.addr, "reads");
for (auto &wr_port : mem.wr_ports)
check_addr(wr_port.addr, "writes");
}
}
if (assert_mode && counter > 0)
log_error("Found %d problems in 'check_mem -assert'.\n", counter);
}
} CheckMemPass;
PRIVATE_NAMESPACE_END

4
passes/cmds/chformal.cc
View file

@ -330,7 +330,7 @@ struct ChformalPass : public Pass {
for (auto cell : constr_cells)
{
if (is_triggered_check_cell(cell))
log_error("Cannot delay edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", log_id(cell));
log_error("Cannot delay edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", cell);
for (int i = 0; i < mode_arg; i++)
{
@ -411,7 +411,7 @@ struct ChformalPass : public Pass {
continue;
if (is_triggered_check_cell(cell))
log_error("Cannot lower edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", log_id(cell));
log_error("Cannot lower edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", cell);
Cell *plain_cell = module->addCell(NEW_ID, formal_flavor(cell));

2
passes/cmds/connect.cc
View file

@ -122,7 +122,7 @@ struct ConnectPass : public Pass {
RTLIL::Module *module = nullptr;
for (auto mod : design->selected_modules()) {
if (module != nullptr)
log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name));
log_cmd_error("Multiple modules selected: %s, %s\n", module->name.unescape(), mod->name.unescape());
module = mod;
}
if (module == nullptr)

4
passes/cmds/connwrappers.cc
View file

@ -134,8 +134,8 @@ struct ConnwrappersWorker
}
if (old_sig.size())
log("Connected extended bits of %s.%s:%s: %s -> %s\n", log_id(module->name), log_id(cell->name),
log_id(conn.first), log_signal(old_sig), log_signal(conn.second));
log("Connected extended bits of %s.%s:%s: %s -> %s\n", module->name.unescape(), cell->name.unescape(),
conn.first.unescape(), log_signal(old_sig), log_signal(conn.second));
}
}
}

4
passes/cmds/design.cc
View file

@ -266,7 +266,7 @@ struct DesignPass : public Pass {
for (auto mod : copy_src_modules)
{
log("Importing %s as %s.\n", log_id(mod), log_id(prefix));
log("Importing %s as %s.\n", mod, RTLIL::unescape_id(prefix));
RTLIL::Module *t = mod->clone();
t->name = prefix;
@ -295,7 +295,7 @@ struct DesignPass : public Pass {
{
std::string trg_name = prefix + "." + (cell->type.c_str() + (*cell->type.c_str() == '\\'));
log("Importing %s as %s.\n", log_id(fmod), log_id(trg_name));
log("Importing %s as %s.\n", fmod, RTLIL::unescape_id(trg_name));
if (copy_to_design->module(trg_name) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_name));

72
passes/cmds/design_equal.cc
View file

@ -38,9 +38,9 @@ public:
[[noreturn]]
void formatted_error(std::string err)
{
log("Module A: %s\n", log_id(mod_a->name));
log("Module A: %s\n", mod_a->name.unescape());
log_module(mod_a, " ");
log("Module B: %s\n", log_id(mod_b->name));
log("Module B: %s\n", mod_b->name.unescape());
log_module(mod_b, " ");
log_cmd_error("Designs are different: %s\n", err);
}
@ -68,20 +68,20 @@ public:
{
for (const auto &it : a->attributes) {
if (b->attributes.count(it.first) == 0)
return "missing attribute " + std::string(log_id(it.first)) + " in second design";
return "missing attribute " + std::string(it.first.unescape()) + " in second design";
if (it.second != b->attributes.at(it.first))
return "attribute " + std::string(log_id(it.first)) + " mismatch: " + log_const(it.second) + " != " + log_const(b->attributes.at(it.first));
return "attribute " + std::string(it.first.unescape()) + " mismatch: " + log_const(it.second) + " != " + log_const(b->attributes.at(it.first));
}
for (const auto &it : b->attributes)
if (a->attributes.count(it.first) == 0)
return "missing attribute " + std::string(log_id(it.first)) + " in first design";
return "missing attribute " + std::string(it.first.unescape()) + " in first design";
return "";
}
std::string compare_wires(const RTLIL::Wire *a, const RTLIL::Wire *b)
{
if (a->name != b->name)
return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape();
if (a->width != b->width)
return "width mismatch: " + std::to_string(a->width) + " != " + std::to_string(b->width);
if (a->start_offset != b->start_offset)
@ -105,19 +105,19 @@ public:
{
for (const auto &it : mod_a->wires_) {
if (mod_b->wires_.count(it.first) == 0)
error("Module %s missing wire %s in second design.\n", log_id(mod_a->name), log_id(it.first));
error("Module %s missing wire %s in second design.\n", mod_a->name.unescape(), it.first.unescape());
if (std::string mismatch = compare_wires(it.second, mod_b->wires_.at(it.first)); !mismatch.empty())
error("Module %s wire %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
error("Module %s wire %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch);
}
for (const auto &it : mod_b->wires_)
if (mod_a->wires_.count(it.first) == 0)
error("Module %s missing wire %s in first design.\n", log_id(mod_b->name), log_id(it.first));
error("Module %s missing wire %s in first design.\n", mod_b->name.unescape(), it.first.unescape());
}
std::string compare_memories(const RTLIL::Memory *a, const RTLIL::Memory *b)
{
if (a->name != b->name)
return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape();
if (a->width != b->width)
return "width mismatch: " + std::to_string(a->width) + " != " + std::to_string(b->width);
if (a->start_offset != b->start_offset)
@ -132,31 +132,31 @@ public:
std::string compare_cells(const RTLIL::Cell *a, const RTLIL::Cell *b)
{
if (a->name != b->name)
return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape();
if (a->type != b->type)
return "type mismatch: " + std::string(log_id(a->type)) + " != " + log_id(b->type);
return "type mismatch: " + std::string(a->type.unescape()) + " != " + b->type.unescape();
if (std::string mismatch = compare_attributes(a, b); !mismatch.empty())
return mismatch;
for (const auto &it : a->parameters) {
if (b->parameters.count(it.first) == 0)
return "parameter mismatch: missing parameter " + std::string(log_id(it.first)) + " in second design";
return "parameter mismatch: missing parameter " + std::string(it.first.unescape()) + " in second design";
if (it.second != b->parameters.at(it.first))
return "parameter mismatch: " + std::string(log_id(it.first)) + " mismatch: " + log_const(it.second) + " != " + log_const(b->parameters.at(it.first));
return "parameter mismatch: " + std::string(it.first.unescape()) + " mismatch: " + log_const(it.second) + " != " + log_const(b->parameters.at(it.first));
}
for (const auto &it : b->parameters)
if (a->parameters.count(it.first) == 0)
return "parameter mismatch: missing parameter " + std::string(log_id(it.first)) + " in first design";
return "parameter mismatch: missing parameter " + std::string(it.first.unescape()) + " in first design";
for (const auto &it : a->connections()) {
if (b->connections().count(it.first) == 0)
return "connection mismatch: missing connection " + std::string(log_id(it.first)) + " in second design";
return "connection mismatch: missing connection " + std::string(it.first.unescape()) + " in second design";
if (!compare_sigspec(it.second, b->connections().at(it.first)))
return "connection " + std::string(log_id(it.first)) + " mismatch: " + log_signal(it.second) + " != " + log_signal(b->connections().at(it.first));
return "connection " + std::string(it.first.unescape()) + " mismatch: " + log_signal(it.second) + " != " + log_signal(b->connections().at(it.first));
}
for (const auto &it : b->connections())
if (a->connections().count(it.first) == 0)
return "connection mismatch: missing connection " + std::string(log_id(it.first)) + " in first design";
return "connection mismatch: missing connection " + std::string(it.first.unescape()) + " in first design";
return "";
}
@ -165,26 +165,26 @@ public:
{
for (const auto &it : mod_a->cells_) {
if (mod_b->cells_.count(it.first) == 0)
error("Module %s missing cell %s in second design.\n", log_id(mod_a->name), log_id(it.first));
error("Module %s missing cell %s in second design.\n", mod_a->name.unescape(), it.first.unescape());
if (std::string mismatch = compare_cells(it.second, mod_b->cells_.at(it.first)); !mismatch.empty())
error("Module %s cell %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
error("Module %s cell %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch);
}
for (const auto &it : mod_b->cells_)
if (mod_a->cells_.count(it.first) == 0)
error("Module %s missing cell %s in first design.\n", log_id(mod_b->name), log_id(it.first));
error("Module %s missing cell %s in first design.\n", mod_b->name.unescape(), it.first.unescape());
}
void check_memories()
{
for (const auto &it : mod_a->memories) {
if (mod_b->memories.count(it.first) == 0)
error("Module %s missing memory %s in second design.\n", log_id(mod_a->name), log_id(it.first));
error("Module %s missing memory %s in second design.\n", mod_a->name.unescape(), it.first.unescape());
if (std::string mismatch = compare_memories(it.second, mod_b->memories.at(it.first)); !mismatch.empty())
error("Module %s memory %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
error("Module %s memory %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch);
}
for (const auto &it : mod_b->memories)
if (mod_a->memories.count(it.first) == 0)
error("Module %s missing memory %s in first design.\n", log_id(mod_b->name), log_id(it.first));
error("Module %s missing memory %s in first design.\n", mod_b->name.unescape(), it.first.unescape());
}
std::string compare_case_rules(const RTLIL::CaseRule *a, const RTLIL::CaseRule *b)
@ -251,7 +251,7 @@ public:
const auto &ma = a->mem_write_actions[i];
const auto &mb = b->mem_write_actions[i];
if (ma.memid != mb.memid)
return "mem_write_actions " + std::to_string(i) + " memid mismatch: " + log_id(ma.memid) + " != " + log_id(mb.memid);
return "mem_write_actions " + std::to_string(i) + " memid mismatch: " + ma.memid.unescape() + " != " + mb.memid.unescape();
if (!compare_sigspec(ma.address, mb.address))
return "mem_write_actions " + std::to_string(i) + " address mismatch: " + log_signal(ma.address) + " != " + log_signal(mb.address);
if (!compare_sigspec(ma.data, mb.data))
@ -268,7 +268,7 @@ public:
std::string compare_processes(const RTLIL::Process *a, const RTLIL::Process *b)
{
if (a->name != b->name) return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
if (a->name != b->name) return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape();
if (std::string mismatch = compare_attributes(a, b); !mismatch.empty())
return mismatch;
if (std::string mismatch = compare_case_rules(&a->root_case, &b->root_case); !mismatch.empty())
@ -285,13 +285,13 @@ public:
{
for (auto &it : mod_a->processes) {
if (mod_b->processes.count(it.first) == 0)
error("Module %s missing process %s in second design.\n", log_id(mod_a->name), log_id(it.first));
error("Module %s missing process %s in second design.\n", mod_a->name.unescape(), it.first.unescape());
if (std::string mismatch = compare_processes(it.second, mod_b->processes.at(it.first)); !mismatch.empty())
error("Module %s process %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch.c_str());
error("Module %s process %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch.c_str());
}
for (auto &it : mod_b->processes)
if (mod_a->processes.count(it.first) == 0)
error("Module %s missing process %s in first design.\n", log_id(mod_b->name), log_id(it.first));
error("Module %s missing process %s in first design.\n", mod_b->name.unescape(), it.first.unescape());
}
void check_connections()
@ -299,13 +299,13 @@ public:
const auto &conns_a = mod_a->connections();
const auto &conns_b = mod_b->connections();
if (conns_a.size() != conns_b.size()) {
error("Module %s connection count differs: %zu != %zu\n", log_id(mod_a->name), conns_a.size(), conns_b.size());
error("Module %s connection count differs: %zu != %zu\n", mod_a->name.unescape(), conns_a.size(), conns_b.size());
} else {
for (size_t i = 0; i < conns_a.size(); i++) {
if (!compare_sigspec(conns_a[i].first, conns_b[i].first))
error("Module %s connection %zu LHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first));
error("Module %s connection %zu LHS %s != %s.\n", mod_a->name.unescape(), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first));
if (!compare_sigspec(conns_a[i].second, conns_b[i].second))
error("Module %s connection %zu RHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second));
error("Module %s connection %zu RHS %s != %s.\n", mod_a->name.unescape(), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second));
}
}
}
@ -313,9 +313,9 @@ public:
void check()
{
if (mod_a->name != mod_b->name)
error("Modules have different names: %s != %s\n", log_id(mod_a->name), log_id(mod_b->name));
error("Modules have different names: %s != %s\n", mod_a->name.unescape(), mod_b->name.unescape());
if (std::string mismatch = compare_attributes(mod_a, mod_b); !mismatch.empty())
error("Module %s %s.\n", log_id(mod_a->name), mismatch);
error("Module %s %s.\n", mod_a->name.unescape(), mismatch);
check_wires();
check_cells();
check_memories();
@ -349,7 +349,7 @@ struct DesignEqualPass : public Pass {
for (auto &it : design->modules_) {
RTLIL::Module *mod = it.second;
if (!other->has(mod->name))
log_error("Second design missing module %s.\n", log_id(mod->name));
log_error("Second design missing module %s.\n", mod->name.unescape());
ModuleComparator cmp(mod, other->module(mod->name));
cmp.check();
@ -357,7 +357,7 @@ struct DesignEqualPass : public Pass {
for (auto &it : other->modules_) {
RTLIL::Module *mod = it.second;
if (!design->has(mod->name))
log_error("First design missing module %s.\n", log_id(mod->name));
log_error("First design missing module %s.\n", mod->name.unescape());
}
log("Designs are identical.\n");

12
passes/cmds/dft_tag.cc
View file

@ -98,7 +98,7 @@ struct DftTagWorker {
}
for (auto cell : overwrite_cells) {
log_debug("Applying $overwrite_tag %s for signal %s\n", log_id(cell->name), log_signal(cell->getPort(ID::A)));
log_debug("Applying $overwrite_tag %s for signal %s\n", cell->name.unescape(), log_signal(cell->getPort(ID::A)));
SigSpec orig_signal = cell->getPort(ID::A);
SigSpec interposed_signal = divert_users(orig_signal);
auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal);
@ -470,9 +470,9 @@ struct DftTagWorker {
if (!warned_cells.insert(cell).second)
return;
if (cell->type.isPublic())
log_warning("Unhandled cell %s (%s) during tag propagation\n", log_id(cell), log_id(cell->type));
log_warning("Unhandled cell %s (%s) during tag propagation\n", cell, cell->type.unescape());
else
log_debug("Unhandled cell %s (%s) during tag propagation\n", log_id(cell), log_id(cell->type));
log_debug("Unhandled cell %s (%s) during tag propagation\n", cell, cell->type.unescape());
}
void process_cell(IdString tag, Cell *cell)
@ -691,7 +691,7 @@ struct DftTagWorker {
// TODO handle some more variants
if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
if (ff.has_clk && !tags(ff.sig_clk).empty())
log_warning("Tags on CLK input ignored for %s (%s)\n", log_id(cell), log_id(cell->type));
log_warning("Tags on CLK input ignored for %s (%s)\n", cell, cell->type.unescape());
int width = ff.width;
@ -709,7 +709,7 @@ struct DftTagWorker {
emit_tag_signal(tag, sig_q, ff.sig_q);
return;
} else {
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", log_id(cell), log_id(cell->type));
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescape());
// For unhandled FFs, the default propagation would cause combinational loops
emit_tag_signal(tag, ff.sig_q, Const(0, ff.width));
@ -739,7 +739,7 @@ struct DftTagWorker {
// which is an over-approximation (unless the cell is a module that
// generates tags itself in which case it could be arbitrary).
if (warned_cells.insert(cell).second)
log_warning("Unhandled cell %s (%s) while emitting tag signals\n", log_id(cell), log_id(cell->type));
log_warning("Unhandled cell %s (%s) while emitting tag signals\n", cell, cell->type.unescape());
}
void emit_tags()

8
passes/cmds/edgetypes.cc
View file

@ -92,12 +92,12 @@ struct EdgetypePass : public Pass {
auto sink_bit_index = std::get<2>(sink);
string source_str = multibit_ports.count(std::pair<IdString, IdString>(source_cell_type, source_port_name)) ?
stringf("%s.%s[%d]", log_id(source_cell_type), log_id(source_port_name), source_bit_index) :
stringf("%s.%s", log_id(source_cell_type), log_id(source_port_name));
stringf("%s.%s[%d]", source_cell_type.unescape(), source_port_name.unescape(), source_bit_index) :
stringf("%s.%s", source_cell_type.unescape(), source_port_name.unescape());
string sink_str = multibit_ports.count(std::pair<IdString, IdString>(sink_cell_type, sink_port_name)) ?
stringf("%s.%s[%d]", log_id(sink_cell_type), log_id(sink_port_name), sink_bit_index) :
stringf("%s.%s", log_id(sink_cell_type), log_id(sink_port_name));
stringf("%s.%s[%d]", sink_cell_type.unescape(), sink_port_name.unescape(), sink_bit_index) :
stringf("%s.%s", sink_cell_type.unescape(), sink_port_name.unescape());
edge_cache.insert(source_str + " " + sink_str);
}

10
passes/cmds/example_dt.cc
View file

@ -226,13 +226,13 @@ struct ExampleDtPass : public Pass
{
auto ref = compute_graph[i];
log("n%d ", i);
log("%s", log_id(ref.function().name));
log("%s", ref.function().name.unescape());
for (auto const &param : ref.function().parameters)
{
if (param.second.empty())
log("[%s]", log_id(param.first));
log("[%s]", param.first.unescape());
else
log("[%s=%s]", log_id(param.first), log_const(param.second));
log("[%s=%s]", param.first.unescape(), log_const(param.second));
}
log("(");
@ -244,13 +244,13 @@ struct ExampleDtPass : public Pass
}
log(")\n");
if (ref.has_sparse_attr())
log("// wire %s\n", log_id(ref.sparse_attr()));
log("// wire %s\n", ref.sparse_attr().unescape());
log("// was #%d %s\n", ref.attr(), log_signal(queue[ref.attr()]));
}
for (auto const &key : compute_graph.keys())
{
log("return %d as %s \n", key.second, log_id(key.first));
log("return %d as %s \n", key.second, key.first.unescape());
}
}
log("Plugin test passed!\n");

4
passes/cmds/future.cc
View file

@ -86,13 +86,13 @@ struct FutureWorker {
log_error("Found multiple drivers for future_ff target signal %s\n", log_signal(bit));
auto driver = *found_driver->second.begin();
if (!driver.cell->is_builtin_ff() && driver.cell->type != ID($anyinit))
log_error("Driver for future_ff target signal %s has non-FF cell type %s\n", log_signal(bit), log_id(driver.cell->type));
log_error("Driver for future_ff target signal %s has non-FF cell type %s\n", log_signal(bit), driver.cell->type.unescape());
FfData ff(&initvals, driver.cell);
if (!ff.has_clk && !ff.has_gclk)
log_error("Driver for future_ff target signal %s has cell type %s, which is not clocked\n", log_signal(bit),
log_id(driver.cell->type));
driver.cell->type.unescape());
ff.unmap_ce_srst();

9
passes/cmds/icell_liberty.cc
View file

@ -1,5 +1,6 @@
#include "kernel/yosys.h"
#include "kernel/celltypes.h"
#include "kernel/newcelltypes.h"
#include "kernel/ff.h"
USING_YOSYS_NAMESPACE
@ -70,10 +71,10 @@ struct LibertyStubber {
std::sort(sorted_ports.begin(), sorted_ports.end(), cmp);
std::string clock_pin_name = "";
for (auto x : sorted_ports) {
std::string port_name = RTLIL::unescape_id(x);
std::string port_name = x.unescape();
bool is_input = base_type.inputs.count(x);
bool is_output = base_type.outputs.count(x);
f << "\t\tpin (" << RTLIL::unescape_id(x.str()) << ") {\n";
f << "\t\tpin (" << x.unescape() << ") {\n";
if (is_input && !is_output) {
i.item("direction", "input");
} else if (!is_input && is_output) {
@ -123,7 +124,7 @@ struct LibertyStubber {
return;
}
if (RTLIL::builtin_ff_cell_types().count(base_name))
if (StaticCellTypes::categories.is_ff(base_name))
return liberty_flop(base, derived, f);
auto& base_type = ct.cell_types[base_name];
@ -131,7 +132,7 @@ struct LibertyStubber {
for (auto x : derived->ports) {
bool is_input = base_type.inputs.count(x);
bool is_output = base_type.outputs.count(x);
f << "\t\tpin (" << RTLIL::unescape_id(x.str()) << ") {\n";
f << "\t\tpin (" << x.unescape() << ") {\n";
if (is_input && !is_output) {
f << "\t\t\tdirection : input;\n";
} else if (!is_input && is_output) {

6
passes/cmds/linecoverage.cc
View file

@ -93,9 +93,9 @@ struct CoveragePass : public Pass {
for (auto module : design->modules())
{
log_debug("Module %s:\n", log_id(module));
log_debug("Module %s:\n", module);
for (auto wire: module->wires()) {
log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute(), log_id(wire->name));
log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute(), wire->name.unescape());
for (auto src: wire->get_strpool_attribute(ID::src)) {
auto filename = extract_src_filename(src);
if (filename.empty()) continue;
@ -109,7 +109,7 @@ struct CoveragePass : public Pass {
}
}
for (auto cell: module->cells()) {
log_debug("%s\t%s\t%s\n", module->selected(cell) ? "*" : " ", cell->get_src_attribute(), log_id(cell->name));
log_debug("%s\t%s\t%s\n", module->selected(cell) ? "*" : " ", cell->get_src_attribute(), cell->name.unescape());
for (auto src: cell->get_strpool_attribute(ID::src)) {
auto filename = extract_src_filename(src);
if (filename.empty()) continue;

8
passes/cmds/ltp.cc
View file

@ -90,7 +90,7 @@ struct LtpWorker
return;
if (busy.count(bit) > 0) {
log_warning("Detected loop at %s in %s\n", log_signal(bit), log_id(module));
log_warning("Detected loop at %s in %s\n", log_signal(bit), module);
return;
}
@ -117,7 +117,7 @@ struct LtpWorker
auto &bitinfo = bits.at(bit);
if (get<2>(bitinfo)) {
printpath(get<1>(bitinfo));
log("%5d: %s (via %s)\n", get<0>(bitinfo), log_signal(bit), log_id(get<2>(bitinfo)));
log("%5d: %s (via %s)\n", get<0>(bitinfo), log_signal(bit), get<2>(bitinfo));
} else {
log("%5d: %s\n", get<0>(bitinfo), log_signal(bit));
}
@ -130,13 +130,13 @@ struct LtpWorker
runner(it.first, 0, State::Sx, nullptr);
log("\n");
log("Longest topological path in %s (length=%d):\n", log_id(module), maxlvl);
log("Longest topological path in %s (length=%d):\n", module, maxlvl);
if (maxlvl >= 0)
printpath(maxbit);
if (bit2ff.count(maxbit))
log("%5s: %s (via %s)\n", "ff", log_signal(get<0>(bit2ff.at(maxbit))), log_id(get<1>(bit2ff.at(maxbit))));
log("%5s: %s (via %s)\n", "ff", log_signal(get<0>(bit2ff.at(maxbit))), get<1>(bit2ff.at(maxbit)));
}
};

8
passes/cmds/portarcs.cc
View file

@ -107,7 +107,7 @@ struct PortarcsPass : Pass {
log_assert(w->port_input || w->port_output);
if (w->port_input && w->port_output) {
log_warning("Module '%s' with ambiguous direction on port %s ignored.\n",
log_id(m), log_id(w));
m, w);
ambiguous_ports = true;
break;
}
@ -128,7 +128,7 @@ struct PortarcsPass : Pass {
if (!cell->type.in(ID($buf), ID($input_port), ID($connect), ID($tribuf))) {
auto tdata = tinfo.find(cell->type);
if (tdata == tinfo.end())
log_cmd_error("Missing timing data for module '%s'.\n", log_id(cell->type));
log_cmd_error("Missing timing data for module '%s'.\n", cell->type.unescape());
for (auto [edge, delay] : tdata->second.comb) {
auto from = edge.first.get_connection(cell);
auto to = edge.second.get_connection(cell);
@ -141,7 +141,7 @@ struct PortarcsPass : Pass {
}
if (!sort.sort())
log_error("Failed to sort instances in module %s.\n", log_id(m));
log_error("Failed to sort instances in module %s.\n", m);
ordering = sort.sorted;
}
@ -244,7 +244,7 @@ struct PortarcsPass : Pass {
if (draw_mode) {
auto bit_str = [](SigBit bit) {
return stringf("%s%d", RTLIL::unescape_id(bit.wire->name.str()), bit.offset);
return stringf("%s%d", bit.wire, bit.offset);
};
std::vector<std::string> headings;

4
passes/cmds/portlist.cc
View file

@ -71,9 +71,9 @@ struct PortlistPass : public Pass {
ports.push_back(stringf("%s [%d:%d] %s", w->port_input ? w->port_output ? "inout" : "input" : "output",
w->upto ? w->start_offset : w->start_offset + w->width - 1,
w->upto ? w->start_offset + w->width - 1 : w->start_offset,
log_id(w)));
w));
}
log("module %s%s\n", log_id(module), m_mode ? " (" : "");
log("module %s%s\n", module, m_mode ? " (" : "");
for (int i = 0; i < GetSize(ports); i++)
log("%s%s\n", ports[i], m_mode && i+1 < GetSize(ports) ? "," : "");
if (m_mode)

10
passes/cmds/printattrs.cc
View file

@ -47,9 +47,9 @@ struct PrintAttrsPass : public Pass {
static void log_const(RTLIL::IdString s, const RTLIL::Const &x, const unsigned int indent) {
if (x.flags & RTLIL::CONST_FLAG_STRING)
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), log_id(s), x.decode_string());
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), s.unescape(), x.decode_string());
else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)
log("%s(* %s=%s *)\n", get_indent_str(indent), log_id(s), x.as_string());
log("%s(* %s=%s *)\n", get_indent_str(indent), s.unescape(), x.as_string());
else
log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
}
@ -63,14 +63,14 @@ struct PrintAttrsPass : public Pass {
for (auto mod : design->selected_modules())
{
if (design->selected_whole_module(mod)) {
log("%s%s\n", get_indent_str(indent), log_id(mod->name));
log("%s%s\n", get_indent_str(indent), mod->name.unescape());
indent += 2;
for (auto &it : mod->attributes)
log_const(it.first, it.second, indent);
}
for (auto cell : mod->selected_cells()) {
log("%s%s\n", get_indent_str(indent), log_id(cell->name));
log("%s%s\n", get_indent_str(indent), cell->name.unescape());
indent += 2;
for (auto &it : cell->attributes)
log_const(it.first, it.second, indent);
@ -78,7 +78,7 @@ struct PrintAttrsPass : public Pass {
}
for (auto wire : mod->selected_wires()) {
log("%s%s\n", get_indent_str(indent), log_id(wire->name));
log("%s%s\n", get_indent_str(indent), wire->name.unescape());
indent += 2;
for (auto &it : wire->attributes)
log_const(it.first, it.second, indent);

29
passes/cmds/rename.cc
View file

@ -31,13 +31,13 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
to_name = RTLIL::escape_id(to_name);
if (module->count_id(to_name))
log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name, module->name);
log_cmd_error("There is already an object `%s' in module `%s'.\n", RTLIL::unescape_id(to_name), module->name);
RTLIL::Wire *wire_to_rename = module->wire(from_name);
RTLIL::Cell *cell_to_rename = module->cell(from_name);
if (wire_to_rename != nullptr) {
log("Renaming wire %s to %s in module %s.\n", log_id(wire_to_rename), log_id(to_name), log_id(module));
log("Renaming wire %s to %s in module %s.\n", wire_to_rename, RTLIL::unescape_id(to_name), module);
module->rename(wire_to_rename, to_name);
if (wire_to_rename->port_id || flag_output) {
if (flag_output)
@ -50,12 +50,12 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
if (cell_to_rename != nullptr) {
if (flag_output)
log_cmd_error("Called with -output but the specified object is a cell.\n");
log("Renaming cell %s to %s in module %s.\n", log_id(cell_to_rename), log_id(to_name), log_id(module));
log("Renaming cell %s to %s in module %s.\n", cell_to_rename, RTLIL::unescape_id(to_name), module);
module->rename(cell_to_rename, to_name);
return;
}
log_cmd_error("Object `%s' not found!\n", from_name);
log_cmd_error("Object `%s' not found!\n", RTLIL::unescape_id(from_name));
}
static std::string derive_name_from_src(const std::string &src, int counter)
@ -254,18 +254,17 @@ struct RenamePass : public Pass {
log("\n");
log(" rename -enumerate [-pattern <pattern>] [selection]\n");
log("\n");
log("Assign short auto-generated names to all selected wires and cells with private\n");
log("names. The -pattern option can be used to set the pattern for the new names.\n");
log("The character %% in the pattern is replaced with a integer number. The default\n");
log("pattern is '_%%_'.\n");
log("Assigns auto-generated names to objects used in formal verification\n");
log("that do not have a public name. This applies to all formal property\n");
log("cells, $any*/$all* output wires, and their containing cells.\n");
log("\n");
log("\n");
log(" rename -witness\n");
log("\n");
log("Assigns auto-generated names to all $any*/$all* output wires and containing\n");
log("cells that do not have a public name. This ensures that, during formal\n");
log("verification, a solver-found trace can be fully specified using a public\n");
log("hierarchical names.\n");
log("Assigns auto-generated names to objects used in formal verification\n");
log("that do not have a public name. This applies to all formal property\n");
log("cells ($assert, $assume, $cover, $live, $fair, $check), $any*/$all*\n");
log("output wires, and their containing cells.\n");
log("\n");
log("\n");
log(" rename -hide [selection]\n");
@ -519,7 +518,7 @@ struct RenamePass : public Pass {
if (module == nullptr)
log_cmd_error("No top module found!\n");
log("Renaming module %s to %s.\n", log_id(module), log_id(new_name));
log("Renaming module %s to %s.\n", module, new_name.unescape());
design->rename(module, new_name);
}
else
@ -533,7 +532,7 @@ struct RenamePass : public Pass {
for (auto module : design->selected_modules())
{
if (module->memories.size() != 0 || module->processes.size() != 0) {
log_warning("Skipping module %s with unprocessed memories or processes\n", log_id(module));
log_warning("Skipping module %s with unprocessed memories or processes\n", module);
continue;
}
@ -622,7 +621,7 @@ struct RenamePass : public Pass {
RTLIL::Module *module_to_rename = nullptr;
for (auto module : design->modules())
if (module->name == from_name || RTLIL::unescape_id(module->name) == from_name) {
if (module->name == from_name || module->name.unescape() == from_name) {
module_to_rename = module;
break;
}

6
passes/cmds/scc.cc
View file

@ -87,7 +87,7 @@ struct SccWorker
RTLIL::Cell *c = cellStack.back();
cellStack.pop_back();
cellsOnStack.erase(c);
log(" %s", RTLIL::id2cstr(c->name));
log(" %s", c);
cell2scc[c] = sccList.size();
scc.insert(c);
}
@ -201,7 +201,7 @@ struct SccWorker
if (!nofeedbackMode && cellToNextCell[cell].count(cell)) {
log("Found an SCC:");
pool<RTLIL::Cell*> scc;
log(" %s", RTLIL::id2cstr(cell->name));
log(" %s", cell);
cell2scc[cell] = sccList.size();
scc.insert(cell);
sccList.push_back(scc);
@ -221,7 +221,7 @@ struct SccWorker
run(cell, 0, maxDepth);
}
log("Found %d SCCs in module %s.\n", int(sccList.size()), RTLIL::id2cstr(module->name));
log("Found %d SCCs in module %s.\n", int(sccList.size()), module);
}
void select(RTLIL::Selection &sel)

9
passes/cmds/sdc/CMakeLists.txt Normal file
View file

@ -0,0 +1,9 @@
yosys_pass(sdc
sdc.cc
LIBRARIES
$<${YOSYS_ENABLE_TCL}:PkgConfig::tcl>
DATA_DIR
sdc
DATA_FILES
graph-stubs.sdc
)

3
passes/cmds/sdc/Makefile.inc
View file

@ -1,3 +0,0 @@
OBJS += passes/cmds/sdc/sdc.o
$(eval $(call add_share_file,share/sdc,passes/cmds/sdc/graph-stubs.sdc))

5
passes/cmds/sdc/sdc.cc
View file

@ -1,3 +1,4 @@
#include "kernel/yosys_config.h"
#ifdef YOSYS_ENABLE_TCL
#include "kernel/register.h"
@ -148,7 +149,7 @@ struct SdcObjects {
path += "/";
path += name;
design_cells.push_back(std::make_pair(path, cell));
for (auto pin : cell->connections()) {
for (auto& pin : cell->connections()) {
IdString pin_name = pin.first;
std::string pin_name_sdc = path + "/" + pin.first.str().substr(1);
design_pins.push_back(std::make_pair(pin_name_sdc, std::make_pair(cell, pin_name)));
@ -168,7 +169,7 @@ struct SdcObjects {
RTLIL::Wire *wire = top->wire(port);
if (!wire) {
// This should not be possible. See https://github.com/YosysHQ/yosys/pull/5594#issue-3791198573
log_error("Port %s doesn't exist", log_id(port));
log_error("Port %s doesn't exist", port.unescape());
}
design_ports.push_back(std::make_pair(port.str().substr(1), wire));
}

26
passes/cmds/select.cc
View file

@ -18,15 +18,13 @@
*/
#include "kernel/yosys.h"
#include "kernel/celltypes.h"
#include "kernel/newcelltypes.h"
#include "kernel/sigtools.h"
#include "kernel/log_help.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
using RTLIL::id2cstr;
static std::vector<RTLIL::Selection> work_stack;
static bool match_ids(RTLIL::IdString id, const std::string &pattern)
@ -488,7 +486,7 @@ static int parse_comma_list(std::set<RTLIL::IdString> &tokens, const std::string
}
}
static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::vector<expand_rule_t> &rules, std::set<RTLIL::IdString> &limits, int max_objects, char mode, CellTypes &ct, bool eval_only)
static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::vector<expand_rule_t> &rules, std::set<RTLIL::IdString> &limits, int max_objects, char mode, NewCellTypes &ct, bool eval_only)
{
int sel_objects = 0;
bool is_input, is_output;
@ -564,7 +562,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
std::vector<expand_rule_t> rules;
std::set<RTLIL::IdString> limits;
CellTypes ct;
NewCellTypes ct;
if (mode != 'x')
ct.setup(design);
@ -1022,9 +1020,9 @@ static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::S
for (auto mod : design->all_selected_modules())
{
if (whole_modules && sel->selected_whole_module(mod->name))
desc += stringf("%s\n", id2cstr(mod->name));
desc += stringf("%s\n", mod);
for (auto it : mod->selected_members())
desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(it->name));
desc += stringf("%s/%s\n", mod, it);
}
if (push_selection) design->pop_selection();
return desc;
@ -1414,7 +1412,7 @@ struct SelectPass : public Pass {
if (arg == "-module" && argidx+1 < args.size()) {
RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
if (design->module(mod_name) == nullptr)
log_cmd_error("No such module: %s\n", id2cstr(mod_name));
log_cmd_error("No such module: %s\n", mod_name.unescape());
design->selected_active_module = mod_name.str();
got_module = true;
continue;
@ -1527,10 +1525,10 @@ struct SelectPass : public Pass {
for (auto mod : design->all_selected_modules())
{
if (sel->selected_whole_module(mod->name) && list_mode)
log("%s\n", id2cstr(mod->name));
log("%s\n", mod);
if (!list_mod_mode)
for (auto it : mod->selected_members())
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(it->name))
LOG_OBJECT("%s/%s\n", mod->name.unescape().c_str(), it->name.unescape().c_str())
}
if (count_mode)
{
@ -1654,10 +1652,10 @@ struct SelectPass : public Pass {
if (sel.full_selection)
log("*\n");
for (auto &it : sel.selected_modules)
log("%s\n", id2cstr(it));
log("%s\n", it.unescape());
for (auto &it : sel.selected_members)
for (auto &it2 : it.second)
log("%s/%s\n", id2cstr(it.first), id2cstr(it2));
log("%s/%s\n", it.first.unescape(), it2.unescape());
return;
}
@ -1779,7 +1777,7 @@ static void log_matches(const char *title, Module *module, const T &list)
log("\n%d %s:\n", int(matches.size()), title);
std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
for (auto id : matches)
log(" %s\n", RTLIL::id2cstr(id));
log(" %s\n", id.unescape());
}
}
@ -1817,7 +1815,7 @@ struct LsPass : public Pass {
log("\n%d %s:\n", int(matches.size()), "modules");
std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
for (auto id : matches)
log(" %s%s\n", log_id(id), design->selected_whole_module(design->module(id)) ? "" : "*");
log(" %s%s\n", id.unescape(), design->selected_whole_module(design->module(id)) ? "" : "*");
}
}
else

4
passes/cmds/setattr.cc
View file

@ -246,9 +246,9 @@ struct ChparamPass : public Pass {
if (!new_parameters.empty())
log_cmd_error("The options -set and -list cannot be used together.\n");
for (auto module : design->selected_modules()) {
log("%s:\n", log_id(module));
log("%s:\n", module);
for (auto param : module->avail_parameters)
log(" %s\n", log_id(param));
log(" %s\n", param.unescape());
}
return;
}

41
passes/cmds/setundef.cc
View file

@ -310,6 +310,8 @@ struct SetundefPass : public Pass {
RTLIL::SigSpec sig = undriven_signals.export_all();
for (auto &c : sig.chunks()) {
if (!design->selected(module, c.wire))
continue;
RTLIL::Wire * wire;
if (c.wire->width == c.width) {
wire = c.wire;
@ -328,12 +330,12 @@ struct SetundefPass : public Pass {
SigMap sigmap(module);
SigPool undriven_signals;
for (auto &it : module->wires_)
undriven_signals.add(sigmap(it.second));
for (auto wire : module->selected_wires())
undriven_signals.add(sigmap(wire));
for (auto &it : module->wires_)
if (it.second->port_input)
undriven_signals.del(sigmap(it.second));
for (auto wire : module->selected_wires())
if (wire->port_input)
undriven_signals.del(sigmap(wire));
CellTypes ct(design);
for (auto &it : module->cells_)
@ -367,6 +369,14 @@ struct SetundefPass : public Pass {
if (!cell->is_builtin_ff())
continue;
bool cell_selected = design->selected(module, cell);
bool wire_selected = false;
for (auto bit : sigmap(cell->getPort(ID::Q)))
if (bit.wire && design->selected(module, bit.wire))
wire_selected = true;
if (!cell_selected && !wire_selected)
continue;
for (auto bit : sigmap(cell->getPort(ID::Q)))
ffbits.insert(bit);
}
@ -502,14 +512,21 @@ struct SetundefPass : public Pass {
}
}
for (auto &it : module->cells_)
if (!it.second->get_bool_attribute(ID::xprop_decoder))
it.second->rewrite_sigspecs(worker);
for (auto &it : module->processes)
it.second->rewrite_sigspecs(worker);
for (auto cell : module->selected_cells())
if (!cell->get_bool_attribute(ID::xprop_decoder))
cell->rewrite_sigspecs(worker);
for (auto proc : module->selected_processes())
proc->rewrite_sigspecs(worker);
for (auto &it : module->connections_) {
worker(it.first);
worker(it.second);
SigSpec lhs = it.first;
bool selected = false;
for (auto &chunk : lhs.chunks())
if (chunk.wire && module->design->selected(module, chunk.wire))
selected = true;
if (selected) {
worker(it.first);
worker(it.second);
}
}
if (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST)

18
passes/cmds/show.cc
View file

@ -442,7 +442,7 @@ struct ShowWorker
id2num(wire->name), shape.c_str(), is_borderless? " margin=0, width=0" : "", findLabel(wire->name.str()),
is_borderless
? "color=\"none\", fontcolor=\"black\""
: nextColor(RTLIL::SigSpec(wire), "color=\"black\", fontcolor=\"black\"").c_str(),
: nextColor(RTLIL::SigSpec(wire), "color=\"black\", fontcolor=\"black\"").c_str(),
src_href.c_str());
if (wire->port_input)
all_sources.insert(stringf("n%d", id2num(wire->name)));
@ -549,7 +549,7 @@ struct ShowWorker
net_conn_map[node].color = nextColor(sig, net_conn_map[node].color);
}
std::string proc_src = RTLIL::unescape_id(proc->name);
std::string proc_src = proc->name.unescape();
if (proc->attributes.count(ID::src) > 0)
proc_src = proc->attributes.at(ID::src).decode_string();
fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\", %s];\n", pidx, findLabel(proc->name.str()), proc_src.c_str(), findColor(proc->name).c_str());
@ -645,16 +645,16 @@ struct ShowWorker
module = mod;
if (design->selected_whole_module(module->name)) {
if (module->get_blackbox_attribute()) {
// log("Skipping blackbox module %s.\n", log_id(module->name));
//log("Skipping blackbox module %s.\n", module->name.unescape());
continue;
} else
if (module->cells().size() == 0 && module->connections().empty() && module->processes.empty()) {
log("Skipping empty module %s.\n", log_id(module->name));
log("Skipping empty module %s.\n", module->name.unescape());
continue;
} else
log("Dumping module %s to page %d.\n", log_id(module->name), ++page_counter);
log("Dumping module %s to page %d.\n", module->name.unescape(), ++page_counter);
} else
log("Dumping selected parts of module %s to page %d.\n", log_id(module->name), ++page_counter);
log("Dumping selected parts of module %s to page %d.\n", module->name.unescape(), ++page_counter);
handle_module();
}
}
@ -770,7 +770,7 @@ struct ShowPass : public Pass {
std::vector<std::pair<std::string, RTLIL::Selection>> color_selections;
std::vector<std::pair<std::string, RTLIL::Selection>> label_selections;
#if defined(_WIN32) || defined(YOSYS_DISABLE_SPAWN)
#if defined(_WIN32) || !defined(YOSYS_ENABLE_SPAWN)
std::string format = "dot";
std::string prefix = "show";
#else
@ -948,13 +948,13 @@ struct ShowPass : public Pass {
std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file);
#undef DOT_CMD
log("Exec: %s\n", cmd);
#if !defined(YOSYS_DISABLE_SPAWN)
#if defined(YOSYS_ENABLE_SPAWN)
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
#endif
}
#if defined(YOSYS_DISABLE_SPAWN)
#if !defined(YOSYS_ENABLE_SPAWN)
log_assert(viewer_exe.empty() && !format.empty());
#else
if (viewer_exe != "none") {

2
passes/cmds/splice.cc
View file

@ -149,7 +149,7 @@ struct SpliceWorker
void run()
{
log("Splicing signals in module %s:\n", log_id(module->name));
log("Splicing signals in module %s:\n", module->name.unescape());
driven_bits.push_back(RTLIL::State::Sm);
driven_bits.push_back(RTLIL::State::Sm);

13
passes/cmds/splitcells.cc
View file

@ -93,7 +93,7 @@ struct SplitcellsWorker
}
slices.push_back(GetSize(outsig));
log_debug("Splitting %s cell %s/%s into %d slices:\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(slices)-1);
log_debug("Splitting %s cell %s/%s into %d slices:\n", cell->type.unescape(), module, cell, GetSize(slices)-1);
for (int i = 1; i < GetSize(slices); i++)
{
int slice_msb = slices[i]-1;
@ -130,7 +130,7 @@ struct SplitcellsWorker
if (slice->hasParam(ID::WIDTH))
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Y)));
log_debug(" slice %d: %s => %s\n", i, log_id(slice_name), log_signal(slice->getPort(ID::Y)));
log_debug(" slice %d: %s => %s\n", i, slice_name, log_signal(slice->getPort(ID::Y)));
}
module->remove(cell);
@ -176,8 +176,7 @@ struct SplitcellsWorker
}
slices.push_back(GetSize(outsig));
log_debug("Splitting %s cell %s/%s into %d slices:\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(slices)-1);
int wire_offset = user_index(0);
log_debug("Splitting %s cell %s/%s into %d slices:\n", cell->type.unescape(), module, cell, GetSize(slices)-1);
for (int i = 1; i < GetSize(slices); i++)
{
int slice_msb = slices[i]-1;
@ -220,7 +219,7 @@ struct SplitcellsWorker
"%c%d%c", format[0], bit_offset, format[1]);
} else { // no '[' or '.', so no concatenation using wire, use slice_lsb + name_lsb offset instead
wire_indices = stringf(
"%c%d%c", format[0], slice_lsb + wire_offset, format[1]);
"%c%d%c", format[0], slice_lsb + user_index(0), format[1]);
}
} else {
// Fallback
@ -255,7 +254,7 @@ struct SplitcellsWorker
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Q)));
log_debug(" slice %d: %s => %s\n", i, log_id(slice_name), log_signal(slice->getPort(ID::Q)));
log_debug(" slice %d: %s => %s\n", i, slice_name.unescape(), log_signal(slice->getPort(ID::Q)));
}
module->remove(cell);
@ -344,7 +343,7 @@ struct SplitcellsPass : public Pass {
if (count_split_pre)
log("Split %d cells in module %s into %d cell slices.\n",
count_split_pre, log_id(module), count_split_post);
count_split_pre, module, count_split_post);
}
}
} SplitnetsPass;

16
passes/cmds/sta.cc
View file

@ -66,12 +66,12 @@ struct StaWorker
Module *inst_module = design->module(cell->type);
if (!inst_module) {
if (unrecognised_cells.insert(cell->type).second)
log_warning("Cell type '%s' not recognised! Ignoring.\n", log_id(cell->type));
log_warning("Cell type '%s' not recognised! Ignoring.\n", cell->type.unescape());
continue;
}
if (!inst_module->get_blackbox_attribute()) {
log_warning("Cell type '%s' is not a black- nor white-box! Ignoring.\n", log_id(cell->type));
log_warning("Cell type '%s' is not a black- nor white-box! Ignoring.\n", cell->type.unescape());
continue;
}
@ -82,7 +82,7 @@ struct StaWorker
if (!timing.count(derived_type)) {
auto &t = timing.setup_module(inst_module);
if (t.has_inputs && t.comb.empty() && t.arrival.empty() && t.required.empty())
log_warning("Module '%s' has no timing arcs!\n", log_id(cell->type));
log_warning("Module '%s' has no timing arcs!\n", cell->type.unescape());
}
auto &t = timing.at(derived_type);
@ -203,10 +203,10 @@ struct StaWorker
return;
}
log("Latest arrival time in '%s' is %d:\n", log_id(module), maxarrival);
log("Latest arrival time in '%s' is %d:\n", module, maxarrival);
auto it = endpoints.find(maxbit);
if (it != endpoints.end() && it->second.sink)
log(" %6d %s (%s.%s)\n", maxarrival, log_id(it->second.sink), log_id(it->second.sink->type), log_id(it->second.port));
log(" %6d %s (%s.%s)\n", maxarrival, it->second.sink, it->second.sink->type.unescape(), it->second.port.unescape());
else {
log(" %6d (%s)\n", maxarrival, b.wire->port_output ? "<primary output>" : "<unknown>");
if (!b.wire->port_output)
@ -217,7 +217,7 @@ struct StaWorker
int arrival = b.wire->get_intvec_attribute(ID::sta_arrival)[b.offset];
if (jt->second.driver) {
log(" %s\n", log_signal(b));
log(" %6d %s (%s.%s->%s)\n", arrival, log_id(jt->second.driver), log_id(jt->second.driver->type), log_id(jt->second.src_port), log_id(jt->second.dst_port));
log(" %6d %s (%s.%s->%s)\n", arrival, jt->second.driver, jt->second.driver->type.unescape(), jt->second.src_port.unescape(), jt->second.dst_port.unescape());
}
else if (b.wire->port_input)
log(" %6d %s (%s)\n", arrival, log_signal(b), "<primary input>");
@ -234,13 +234,13 @@ struct StaWorker
continue;
if (!b.wire->attributes.count(ID::sta_arrival)) {
log_warning("Endpoint %s.%s has no (* sta_arrival *) value.\n", log_id(module), log_signal(b));
log_warning("Endpoint %s.%s has no (* sta_arrival *) value.\n", module, log_signal(b));
continue;
}
auto arrival = b.wire->get_intvec_attribute(ID::sta_arrival)[b.offset];
if (arrival < 0) {
log_warning("Endpoint %s.%s has no (* sta_arrival *) value.\n", log_id(module), log_signal(b));
log_warning("Endpoint %s.%s has no (* sta_arrival *) value.\n", module, log_signal(b));
continue;
}
arrival += i.second.required;

18
passes/cmds/stat.cc
View file

@ -253,7 +253,7 @@ struct statdata_t
log(" Number of cells: %6u\n", num_cells);
for (auto &it : num_cells_by_type)
if (it.second)
log(" %-26s %6u\n", log_id(it.first), it.second);
log(" %-26s %6u\n", it.first.unescape(), it.second);
if (!unknown_cell_area.empty()) {
log("\n");
@ -267,7 +267,7 @@ struct statdata_t
log(" of which used for sequential elements: %f (%.2f%%)\n", sequential_area, 100.0*sequential_area/area);
}
if (tech == "xilinx")
if (tech == "xilinx" || tech == "analogdevices")
{
log("\n");
log(" Estimated number of LCs: %10u\n", estimate_xilinx_lc());
@ -305,12 +305,12 @@ struct statdata_t
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second);
log(" %s: %u", json11::Json(it.first.unescape()).dump().c_str(), it.second);
first_line = false;
}
log("\n");
log(" }");
if (tech == "xilinx")
if (tech == "xilinx" || tech == "analogdevices")
{
log(",\n");
log(" \"estimated_num_lc\": %u", estimate_xilinx_lc());
@ -336,7 +336,7 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
for (auto &it : num_cells_by_type)
if (mod_stat.count(it.first) > 0) {
if (!quiet)
log(" %*s%-*s %6u\n", 2*level, "", 26-2*level, log_id(it.first), it.second);
log(" %*s%-*s %6u\n", 2*level, "", 26-2*level, it.first.unescape(), it.second);
mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1, quiet) * it.second;
mod_data.num_cells -= it.second;
} else {
@ -435,7 +435,7 @@ struct StatPass : public Pass {
log("\n");
log(" -tech <technology>\n");
log(" print area estimate for the specified technology. Currently supported\n");
log(" values for <technology>: xilinx, cmos\n");
log(" values for <technology>: xilinx, analogdevices, cmos\n");
log("\n");
log(" -width\n");
log(" annotate internal cell types with their word width.\n");
@ -494,7 +494,7 @@ struct StatPass : public Pass {
if(!json_mode)
log_header(design, "Printing statistics.\n");
if (techname != "" && techname != "xilinx" && techname != "cmos" && !json_mode)
if (techname != "" && techname != "xilinx" && techname != "analogdevices" && techname != "cmos" && !json_mode)
log_cmd_error("Unsupported technology: '%s'\n", techname);
if (json_mode) {
@ -521,7 +521,7 @@ struct StatPass : public Pass {
first_module = false;
} else {
log("\n");
log("=== %s%s ===\n", log_id(mod->name), mod->is_selected_whole() ? "" : " (partially selected)");
log("=== %s%s ===\n", mod->name.unescape(), mod->is_selected_whole() ? "" : " (partially selected)");
log("\n");
data.log_data(mod->name, false);
}
@ -538,7 +538,7 @@ struct StatPass : public Pass {
log("\n");
log("=== design hierarchy ===\n");
log("\n");
log(" %-28s %6d\n", log_id(top_mod->name), 1);
log(" %-28s %6d\n", top_mod->name.unescape(), 1);
}
statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0, /*quiet=*/json_mode);

4
passes/cmds/test_select.cc
View file

@ -144,10 +144,10 @@ struct TestSelectPass : public Pass {
for (auto *mod : sub_sel) {
if (mod->is_selected_whole()) {
log_debug(" Adding %s.\n", id2cstr(mod->name));
log_debug(" Adding %s.\n", mod);
selected_modules.insert(mod->name);
} else for (auto *memb : mod->selected_members()) {
log_debug(" Adding %s.%s.\n", id2cstr(mod->name), id2cstr(memb->name));
log_debug(" Adding %s.%s.\n", mod, memb);
selected_members[mod->name].insert(memb);
}
}

22
passes/cmds/timeest.cc
View file

@ -83,7 +83,7 @@ struct EstimateSta {
void run()
{
log("\nModule %s\n", log_id(m));
log("\nModule %s\n", m);
if (clk.has_value())
log("Domain %s\n", log_signal(*clk));
@ -97,10 +97,10 @@ struct EstimateSta {
FfData ff(nullptr, cell);
if (!ff.has_clk) {
log_warning("Ignoring unsupported storage element '%s' (%s)\n",
log_id(cell), log_id(cell->type));
cell, cell->type.unescape());
continue;
}
if (ff.sig_clk != clk)
if (!clk || ff.sig_clk.as_bit() != *clk)
continue;
launch.append(ff.sig_q);
sample.append(ff.sig_d);
@ -121,7 +121,7 @@ struct EstimateSta {
aigs.emplace(fingerprint, Aig(cell));
if (aigs.at(fingerprint).name.empty()) {
log_error("Unsupported cell '%s' in module '%s'",
log_id(cell->type), log_id(m));
cell->type.unescape(), m);
}
}
@ -141,15 +141,15 @@ struct EstimateSta {
for (auto &mem : Mem::get_all_memories(m)) {
for (auto &rd : mem.rd_ports) {
if (!rd.clk_enable) {
log_error("Unsupported async memory port '%s'\n", log_id(rd.cell));
log_error("Unsupported async memory port '%s'\n", rd.cell);
continue;
}
if (sigmap(rd.clk) != clk)
if (!clk || sigmap(rd.clk).as_bit() != *clk)
continue;
add_seq(rd.cell, rd.data, {rd.addr, rd.srst, rd.en});
}
for (auto &wr : mem.wr_ports) {
if (sigmap(wr.clk) != clk)
if (!clk || sigmap(wr.clk).as_bit() != *clk)
continue;
add_seq(wr.cell, {}, {wr.en, wr.addr, wr.data});
}
@ -165,7 +165,7 @@ struct EstimateSta {
} else if (port->port_output && !port->port_input) {
all_outputs.append(port);
} else if (port->port_output && port->port_input) {
log_warning("Ignoring bi-directional port %s\n", log_id(port));
log_warning("Ignoring bi-directional port %s\n", port);
}
}
add_seq(nullptr, all_inputs, all_outputs);
@ -216,7 +216,7 @@ struct EstimateSta {
}
if (!topo.sort())
log_error("Module '%s' contains combinational loops", log_id(m));
log_error("Module '%s' contains combinational loops", m);
// now we determine how long it takes for signals to stabilize
@ -342,7 +342,7 @@ struct EstimateSta {
std::string src_attr = cell->get_src_attribute();
cell_src = stringf(" source: %s", src_attr);
}
log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src);
log(" cell %s (%s)%s\n", cell, cell->type.unescape(), cell_src);
printed.insert(cell);
}
} else {
@ -425,7 +425,7 @@ struct TimeestPass : Pass {
if (clk_domain_specified) {
if (!m->wire(RTLIL::escape_id(clk_name))) {
log_warning("No domain '%s' in module %s\n", clk_name.c_str(), log_id(m));
log_warning("No domain '%s' in module %s\n", clk_name.c_str(), m);
continue;
}

8
passes/cmds/torder.cc
View file

@ -18,7 +18,7 @@
*/
#include "kernel/yosys.h"
#include "kernel/celltypes.h"
#include "kernel/newcelltypes.h"
#include "kernel/sigtools.h"
#include "kernel/utils.h"
#include "kernel/log_help.h"
@ -74,7 +74,7 @@ struct TorderPass : public Pass {
for (auto module : design->selected_modules())
{
log("module %s\n", log_id(module));
log("module %s\n", module);
SigMap sigmap(module);
dict<SigBit, pool<IdString>> bit_drivers, bit_users;
@ -116,12 +116,12 @@ struct TorderPass : public Pass {
for (auto &it : toposort.loops) {
log(" loop");
for (auto cell : it)
log(" %s", log_id(cell));
log(" %s", cell);
log("\n");
}
for (auto cell : toposort.sorted)
log(" cell %s\n", log_id(cell));
log(" cell %s\n", cell);
}
}
} TorderPass;

12
passes/cmds/trace.cc
View file

@ -28,34 +28,34 @@ struct TraceMonitor : public RTLIL::Monitor
{
void notify_module_add(RTLIL::Module *module) override
{
log("#TRACE# Module add: %s\n", log_id(module));
log("#TRACE# Module add: %s\n", module);
}
void notify_module_del(RTLIL::Module *module) override
{
log("#TRACE# Module delete: %s\n", log_id(module));
log("#TRACE# Module delete: %s\n", module);
}
void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
{
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, port.unescape(), log_signal(sig), log_signal(old_sig));
}
void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override
{
log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second));
log("#TRACE# Connection in module %s: %s = %s\n", module, log_signal(sigsig.first), log_signal(sigsig.second));
}
void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) override
{
log("#TRACE# New connections in module %s:\n", log_id(module));
log("#TRACE# New connections in module %s:\n", module);
for (auto &sigsig : sigsig_vec)
log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second));
}
void notify_blackout(RTLIL::Module *module) override
{
log("#TRACE# Blackout in module %s:\n", log_id(module));
log("#TRACE# Blackout in module %s:\n", module);
}
};

14
passes/cmds/viz.cc
View file

@ -279,7 +279,7 @@ struct Graph {
Graph(Module *module, const VizConfig &config) : module(module), config(config)
{
log("Running 'viz -%d' for module %s:\n", config.effort, log_id(module));
log("Running 'viz -%d' for module %s:\n", config.effort, module);
log(" Phase %d: Construct initial graph\n", phase_counter++);
SigMap sigmap(module);
@ -718,7 +718,7 @@ struct VizWorker
void write_dot(FILE *f)
{
fprintf(f, "digraph \"%s\" {\n", log_id(module));
fprintf(f, "digraph \"%s\" {\n", module->name.unescape().c_str());
fprintf(f, " rankdir = LR;\n");
dict<GraphNode*, std::vector<std::vector<std::string>>> extra_lines;
@ -734,7 +734,7 @@ struct VizWorker
buffer.emplace_back();
for (auto name : g->names())
buffer.back().push_back(log_id(name));
buffer.back().push_back(name.unescape());
std::sort(buffer.back().begin(), buffer.back().end());
std::sort(buffer.begin(), buffer.end());
@ -782,7 +782,7 @@ struct VizWorker
g->names().sort();
std::string label; // = stringf("vg=%d\\n", g->index);
for (auto n : g->names())
label = label + (label.empty() ? "" : "\\n") + log_id(n);
label = label + (label.empty() ? "" : "\\n") + n.unescape();
fprintf(f, "\tn%d [shape=rectangle,label=\"%s\"];\n", g->index, label.c_str());
} else {
std::string label = stringf("vg=%d | %d cells", g->index, GetSize(g->names()));
@ -898,7 +898,7 @@ struct VizPass : public Pass {
log_header(design, "Generating Graphviz representation of design.\n");
log_push();
#if defined(_WIN32) || defined(YOSYS_DISABLE_SPAWN)
#if defined(_WIN32) || !defined(YOSYS_ENABLE_SPAWN)
std::string format = "dot";
std::string prefix = "show";
#else
@ -1029,13 +1029,13 @@ struct VizPass : public Pass {
std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file);
#undef DOT_CMD
log("Exec: %s\n", cmd);
#if !defined(YOSYS_DISABLE_SPAWN)
#if defined(YOSYS_ENABLE_SPAWN)
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
#endif
}
#if defined(YOSYS_DISABLE_SPAWN)
#if !defined(YOSYS_ENABLE_SPAWN)
log_assert(viewer_exe.empty() && !format.empty());
#else
if (!viewer_exe.empty()) {

10
passes/cmds/wrapcell.cc
View file

@ -70,7 +70,7 @@ std::optional<std::string> format_with_params(std::string fmt, const dict<IdStri
} else {
auto id = RTLIL::escape_id(std::string(beg, it));
if (!parameters.count(id)) {
log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt);
log("Parameter %s referenced in format string '%s' not found\n", id, fmt);
return {};
}
@ -210,7 +210,7 @@ struct WrapcellPass : Pass {
if (!ct.cell_known(cell->type))
log_error("Non-internal cell type '%s' on cell '%s' in module '%s' unsupported\n",
log_id(cell->type), log_id(cell), log_id(module));
cell->type.unescape(), cell, module);
std::vector<std::pair<IdString, int>> unused_outputs, used_outputs;
for (auto conn : cell->connections()) {
@ -227,13 +227,13 @@ struct WrapcellPass : Pass {
if (!unused_outputs.empty()) {
context.unused_outputs += "_unused";
for (auto chunk : collect_chunks(unused_outputs))
context.unused_outputs += "_" + RTLIL::unescape_id(chunk.format(cell));
context.unused_outputs += "_" + chunk.format(cell).unescape();
}
std::optional<std::string> unescaped_name = format_with_params(name_fmt, cell->parameters, context);
if (!unescaped_name)
log_error("Formatting error when processing cell '%s' in module '%s'\n",
log_id(cell), log_id(module));
cell, module);
IdString name = RTLIL::escape_id(unescaped_name.value());
if (d->module(name))
@ -274,7 +274,7 @@ struct WrapcellPass : Pass {
if (!value)
log_error("Formatting error when processing cell '%s' in module '%s'\n",
log_id(cell), log_id(module));
cell, module);
subm->set_string_attribute(rule.name, value.value());
}

16
passes/cmds/xprop.cc
View file

@ -463,7 +463,11 @@ struct XpropWorker
return;
}
log_warning("Unhandled cell %s (%s) during maybe-x marking\n", log_id(cell), log_id(cell->type));
if (cell->type.in(ID($scopeinfo))) {
return;
}
log_warning("Unhandled cell %s (%s) during maybe-x marking\n", cell, cell->type.unescape());
mark_outputs_maybe_x(cell);
}
@ -858,7 +862,7 @@ struct XpropWorker
if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
if (ff.has_clk && maybe_x(ff.sig_clk)) {
log_warning("Only non-x CLK inputs are currently supported for %s (%s)\n", log_id(cell), log_id(cell->type));
log_warning("Only non-x CLK inputs are currently supported for %s (%s)\n", cell, cell->type.unescape());
} else {
auto init_q = ff.val_init;
auto init_q_is_1 = init_q;
@ -903,7 +907,7 @@ struct XpropWorker
return;
}
} else {
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", log_id(cell), log_id(cell->type));
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescape());
}
}
@ -960,9 +964,9 @@ struct XpropWorker
log("Running 'demuxmap' preserves x-propagation and can be run before 'xprop'.\n");
if (options.required)
log_error("Unhandled cell %s (%s)\n", log_id(cell), log_id(cell->type));
log_error("Unhandled cell %s (%s)\n", cell, cell->type.unescape());
else
log_warning("Unhandled cell %s (%s)\n", log_id(cell), log_id(cell->type));
log_warning("Unhandled cell %s (%s)\n", cell, cell->type.unescape());
}
void split_ports()
@ -976,7 +980,7 @@ struct XpropWorker
auto wire = module->wire(port);
if (module->design->selected(module, wire)) {
if (wire->port_input == wire->port_output) {
log_warning("Port %s not an input or an output port which is not supported by xprop\n", log_id(wire));
log_warning("Port %s not an input or an output port which is not supported by xprop\n", wire);
} else if ((options.split_inputs && !options.assume_def_inputs && wire->port_input) || (options.split_outputs && wire->port_output)) {
auto port_d = module->uniquify(stringf("%s_d", port));
auto port_x = module->uniquify(stringf("%s_x", port));