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Populate generate for xilinx_srl.fixed pattern

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This commit is contained in:
Eddie Hung 2019-08-26 14:21:17 -07:00
parent cf9e017127
commit e574edc3e9
1 changed files with 54 additions and 22 deletions
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76
passes/pmgen/xilinx_srl.pmg
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@ -18,22 +18,46 @@ match first
select !first->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || !param(first, \IS_D_INVERTED).as_bool() select !first->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || !param(first, \IS_D_INVERTED).as_bool()
select !first->type.in(\FDRE, \FDRE_1) || port(first, \R) == State::S0 select !first->type.in(\FDRE, \FDRE_1) || port(first, \R) == State::S0
filter !non_first_cells.count(first) filter !non_first_cells.count(first)
//generate generate
// SigSpec A = module->addWire(NEW_ID); SigSpec C = module->addWire(NEW_ID);
// SigSpec B = module->addWire(NEW_ID); SigSpec D = module->addWire(NEW_ID);
// SigSpec Y = module->addWire(NEW_ID); SigSpec Q = module->addWire(NEW_ID);
// switch (rng(3)) auto r = rng(8);
// { Cell* cell;
// case 0: switch (r)
// module->addAndGate(NEW_ID, A, B, Y); {
// break; case 0:
// case 1: case 1:
// module->addOrGate(NEW_ID, A, B, Y); case 2:
// break; case 3:
// case 2: cell = module->addCell(NEW_ID, \FDRE);
// module->addXorGate(NEW_ID, A, B, Y); if (r & 1)
// break; cell->setPort(\R, State::S1);
// } else
cell->setPort(\R, State::S0);
if (r & 2)
cell->setPort(\CE, State::S1);
else
cell->setPort(\CE, State::S0);
break;
case 4:
cell = module->addCell(NEW_ID, $_DFF_N_);
break;
case 5:
case 6:
cell = module->addCell(NEW_ID, $_DFFE_PP_);
if (r & 1)
cell->setPort(\E, State::S1);
else
cell->setPort(\E, State::S0);
break;
case 7:
cell = module->addCell(NEW_ID, \foobar);
break;
}
cell->setPort(\C, C);
cell->setPort(\D, D);
cell->setPort(\Q, Q);
endmatch endmatch
code clk_port en_port code clk_port en_port
@ -126,12 +150,20 @@ match next
filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()) filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool())
filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()) filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool())
filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R)
//generate 10 generate 10
// SigSpec A = module->addWire(NEW_ID); SigSpec C = chain.back()->getPort(\C);
// SigSpec B = module->addWire(NEW_ID); SigSpec D = module->addWire(NEW_ID);
// SigSpec Y = port(chain.back().first, chain.back().second); SigSpec Q = chain.back()->getPort(\D);
// Cell *c = module->addAndGate(NEW_ID, A, B, Y); Cell *cell = module->addCell(NEW_ID, chain.back()->type);
// c->type = chain.back().first->type; cell->setPort(\C, C);
cell->setPort(\D, D);
cell->setPort(\Q, Q);
if (cell->type == \FDRE) {
cell->setPort(\R, chain.back()->getPort(\R));
cell->setPort(\CE, chain.back()->getPort(\CE));
}
else if (cell->type == $_DFFE_PP_)
cell->setPort(\E, chain.back()->getPort(\E));
endmatch endmatch
code code