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async2sync: inherit src attributes on new_q and new_d wires. Fixes #5674

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abhinavputhran 2026-03-06 16:27:03 -05:00
parent 04113eb95d
commit e5560cb8a9
2 changed files with 21 additions and 0 deletions
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10
passes/sat/async2sync.cc
View file

@ -153,7 +153,10 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q); initvals.remove_init(ff.sig_q);
Wire *new_d = module->addWire(NEW_ID, ff.width); Wire *new_d = module->addWire(NEW_ID, ff.width);
new_d->set_src_attribute(cell->get_src_attribute());
Wire *new_q = module->addWire(NEW_ID, ff.width); Wire *new_q = module->addWire(NEW_ID, ff.width);
new_q->set_src_attribute(cell->get_src_attribute());
SigSpec sig_set = ff.sig_set; SigSpec sig_set = ff.sig_set;
SigSpec sig_clr = ff.sig_clr; SigSpec sig_clr = ff.sig_clr;
@ -199,7 +202,10 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q); initvals.remove_init(ff.sig_q);
Wire *new_d = module->addWire(NEW_ID, ff.width); Wire *new_d = module->addWire(NEW_ID, ff.width);
new_d->set_src_attribute(cell->get_src_attribute());
Wire *new_q = module->addWire(NEW_ID, ff.width); Wire *new_q = module->addWire(NEW_ID, ff.width);
new_q->set_src_attribute(cell->get_src_attribute());
if (ff.pol_aload) { if (ff.pol_aload) {
if (!ff.is_fine) { if (!ff.is_fine) {
@ -232,6 +238,7 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q); initvals.remove_init(ff.sig_q);
Wire *new_q = module->addWire(NEW_ID, ff.width); Wire *new_q = module->addWire(NEW_ID, ff.width);
new_q->set_src_attribute(cell->get_src_attribute());
if (ff.pol_arst) { if (ff.pol_arst) {
if (!ff.is_fine) if (!ff.is_fine)
@ -266,10 +273,13 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q); initvals.remove_init(ff.sig_q);
Wire *new_q = module->addWire(NEW_ID, ff.width); Wire *new_q = module->addWire(NEW_ID, ff.width);
new_q->set_src_attribute(cell->get_src_attribute());
Wire *new_d; Wire *new_d;
if (ff.has_aload) { if (ff.has_aload) {
new_d = module->addWire(NEW_ID, ff.width); new_d = module->addWire(NEW_ID, ff.width);
new_d->set_src_attribute(cell->get_src_attribute());
if (ff.pol_aload) { if (ff.pol_aload) {
if (!ff.is_fine) if (!ff.is_fine)
module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d); module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d);

11
tests/sat/async2sync.ys Normal file
View file

@ -0,0 +1,11 @@
read_verilog << EOT
module top(input clk, arst, d, output reg q);
always @(posedge clk or posedge arst)
if (arst) q <= 0;
else q <= d;
endmodule
EOT
proc
async2sync
dump w:\$auto\$async2sync*