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async2sync: inherit src attributes on new_q and new_d wires. Fixes #5674

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abhinavputhran 2026-03-06 16:27:03 -05:00
parent 04113eb95d
commit e5560cb8a9
2 changed files with 21 additions and 0 deletions
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tests/sat/async2sync.ys Normal file
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read_verilog << EOT
module top(input clk, arst, d, output reg q);
always @(posedge clk or posedge arst)
if (arst) q <= 0;
else q <= d;
endmodule
EOT
proc
async2sync
dump w:\$auto\$async2sync*