Merge from upstream

tests/unit/kernel/hashTest.cc

@@ -0,0 +1,67 @@
+#include <gtest/gtest.h>
+#include "kernel/yosys_common.h"
+
+#include <unordered_set>
+
+YOSYS_NAMESPACE_BEGIN
+
+static Hasher hash(int x)
+{
+	Hasher h;
+	h.eat(x);
+	return h;
+}
+
+TEST(CommutativeTest, basic)
+{
+	hashlib::commutative_hash comm1;
+	comm1.eat(hash(1));
+	comm1.eat(hash(2));
+	hashlib::commutative_hash comm2;
+	comm2.eat(hash(2));
+	comm2.eat(hash(1));
+	EXPECT_EQ(comm1.hash_into(Hasher()).yield(), comm2.hash_into(Hasher()).yield());
+}
+
+TEST(PoolHashTest, collisions)
+{
+	uint64_t collisions = 0;
+	std::unordered_set<Hasher::hash_t> hashes;
+	for (int i = 0; i < 1000; ++i) {
+		for (int j = i + 1; j < 1000; ++j) {
+			pool<int> p1;
+			p1.insert(i);
+			p1.insert(j);
+			auto h = p1.hash_into(Hasher()).yield();
+			if (!hashes.insert(h).second) {
+				++collisions;
+			}
+		}
+	}
+	std::cout << "pool<int> collisions: " << collisions << std::endl;
+	EXPECT_LT(collisions, 10'000);
+}
+
+TEST(PoolHashTest, subset_collisions)
+{
+	uint64_t collisions = 0;
+	std::unordered_set<Hasher::hash_t> hashes;
+	for (int i = 0; i < 1000 * 1000; ++i) {
+
+		pool<int> p1;
+		for (int b = 0; i >> b; ++b) {
+			if ((i >> b) & 1) {
+				p1.insert(b);
+			}
+		}
+		auto h = p1.hash_into(Hasher()).yield();
+		if (!hashes.insert(h).second) {
+			++collisions;
+		}
+
+	}
+	std::cout << "pool<int> subset collisions: " << collisions << std::endl;
+	EXPECT_LT(collisions, 100);
+}
+
+YOSYS_NAMESPACE_END

tests/unit/kernel/ioTest.cc

@@ -69,4 +69,14 @@ TEST(KernelStringfTest, dynamicWidthAndPrecision)
         EXPECT_EQ(stringf("%*.*f", 8, 4, 1.0), "  1.0000");
 }
 
+TEST(KernelStringfTest, dynamicPrecisionInt)
+{
+        EXPECT_EQ(stringf("%.*d", 4, 7), "0007");
+}
+
+TEST(KernelStringfTest, dynamicWidthAndPrecisionInt)
+{
+        EXPECT_EQ(stringf("%*.*d", 8, 4, 7), "    0007");
+}
+
 YOSYS_NAMESPACE_END

tests/various/abstract_initstates.ys

@@ -0,0 +1,30 @@
+read_verilog <<EOT
+
+module half_clock (CLK, Q, magic);
+	input CLK;
+	output reg Q = 0;
+	input magic;
+	always @(posedge CLK)
+		Q <= ~Q;
+endmodule
+
+EOT
+proc
+design -save half_clock
+
+sat -set-init-undef -enable_undef -verify -seq 5 -set-at 1 Q 0
+sat -set-init-undef -enable_undef -falsify -seq 5 -set-at 1 Q 0 -set-at 2 Q 0
+sat -set-init-undef -enable_undef -falsify -seq 5 -set-at 2 Q 0 -set-at 3 Q 0
+abstract -state -initstates 1 */Q
+sat -set-init-undef -enable_undef -verify -seq 5 -set-at 1 Q 0 -set-at 2 Q 0
+sat -set-init-undef -enable_undef -falsify -seq 5 -set-at 2 Q 0 -set-at 3 Q 0
+
+design -load half_clock
+
+sat -set-init-undef -enable_undef -falsify -seq 5 -set-at 1 Q 0 -set-at 2 Q 0
+sat -set-init-undef -enable_undef -falsify -seq 5 -set-at 2 Q 0 -set-at 3 Q 0
+sat -set-init-undef -enable_undef -falsify -seq 5 -set-at 3 Q 0 -set-at 4 Q 0
+abstract -state -initstates 2 */Q
+sat -set-init-undef -enable_undef -verify -seq 5 -set-at 1 Q 0 -set-at 2 Q 0
+sat -set-init-undef -enable_undef -verify -seq 5 -set-at 1 Q 0 -set-at 2 Q 0 -set-at 3 Q 0
+sat -set-init-undef -enable_undef -falsify -seq 5 -set-at 3 Q 0 -set-at 4 Q 0

tests/various/rename_unescape.ys

@@ -39,3 +39,18 @@ select -assert-count 1 w:d__1
 select -assert-count 1 w:_e
 select -assert-count 1 w:wire_
 select -assert-count 1 w:$add$<<EOF:*$1_Y
+
+# Ports are updated during rename
+design -reset
+read_verilog << EOT
+module top(output \$e );
+submod \a$ (\$e );
+endmodule
+
+module submod(output \a[0] );
+    assign \a[0] = 0;
+endmodule
+EOT
+
+rename -unescape
+check