mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

opt_lut: refactor to use a worker. NFC.

Browse source
This commit is contained in:
whitequark 2018-12-05 12:26:41 +00:00
parent ea4870b126
commit e54c7e951c
1 changed files with 186 additions and 179 deletions
Download patch file Download diff file Expand all files Collapse all files

33
passes/opt/opt_lut.cpp
View file

@ -24,8 +24,14 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
static bool evaluate_lut(SigMap &sigmap, RTLIL::Cell *lut, dict<SigBit, bool> inputs)
struct OptLutWorker
{
RTLIL::Module *module;
ModIndex index;
SigMap sigmap;
bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
{
SigSpec lut_input = sigmap(lut->getPort("\\A"));
int lut_width = lut->getParam("\\WIDTH").as_int();
Const lut_table = lut->getParam("\\LUT");
@ -45,17 +51,15 @@ static bool evaluate_lut(SigMap &sigmap, RTLIL::Cell *lut, dict<SigBit, bool> in
}
return lut_table.extract(lut_index).as_int();
}
static void run_lut_opts(Module *module)
{
ModIndex index(module);
SigMap sigmap(module);
log("Discovering LUTs.\n");
}
OptLutWorker(RTLIL::Module *module) :
module(module), index(module), sigmap(module)
{
pool<RTLIL::Cell*> luts;
dict<RTLIL::Cell*, int> luts_arity;
log("Discovering LUTs.\n");
for (auto cell : module->selected_cells())
{
if (cell->type == "$lut")
@ -219,8 +223,8 @@ static void run_lut_opts(Module *module)
{
eval_inputs[lutM_new_inputs[i]] = (eval >> i) & 1;
}
eval_inputs[lutA_output] = evaluate_lut(sigmap, lutA, eval_inputs);
lutM_new_table[eval] = (RTLIL::State) evaluate_lut(sigmap, lutB, eval_inputs);
eval_inputs[lutA_output] = evaluate_lut(lutA, eval_inputs);
lutM_new_table[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs);
}
log(" Old truth table: %s.\n", lutM->getParam("\\LUT").as_string().c_str());
@ -240,7 +244,8 @@ static void run_lut_opts(Module *module)
}
}
}
}
}
};
struct OptLutPass : public Pass {
OptLutPass() : Pass("opt_lut", "optimize LUT cells") { }
@ -267,7 +272,9 @@ struct OptLutPass : public Pass {
extra_args(args, argidx, design);
for (auto module : design->selected_modules())
run_lut_opts(module);
{
OptLutWorker worker(module);
}
}
} OptLutPass;