mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-05 19:00:26 +00:00
Code Activity

Remove need for $currQ port connection

Browse source
This commit is contained in:
Eddie Hung 2019-09-30 16:33:40 -07:00
parent 5e9ae90cbb
commit e529872b01
4 changed files with 129 additions and 114 deletions
Download patch file Download diff file Expand all files Collapse all files

6
backends/aiger/xaiger.cc
View file

@ -483,12 +483,12 @@ struct XAigerWriter
if (box_module->get_bool_attribute("\\abc9_flop")) {
IdString port_name = "\\$currQ";
RTLIL::Wire* w = box_module->wire(port_name);
SigSpec rhs = cell->getPort(port_name);
Wire *w = box_module->wire(port_name);
SigSpec rhs = module->wire(stringf("%s.$currQ", cell->name.c_str()));
log_assert(GetSize(w) == GetSize(rhs));
int offset = 0;
for (auto b : rhs.bits()) {
for (auto b : rhs) {
SigBit I = sigmap(b);
if (b == RTLIL::Sx)
b = State::S0;