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printattrs: Use flags to pretty-print the RTLIL::Const appropriately.

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Co-Authored-By: whitequark <whitequark@whitequark.org>
This commit is contained in:
Alberto Gonzalez 2020-05-27 07:40:40 +00:00
parent b8365547e9
commit e50e4ee285
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GPG key ID: 8395A8BA109708B2
1 changed files with 15 additions and 8 deletions
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23
passes/cmds/printattrs.cc
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@ -34,6 +34,16 @@ struct PrintAttrsPass : public Pass {
log("\n"); log("\n");
log("\n"); log("\n");
} }
static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) {
if (x.flags == RTLIL::CONST_FLAG_STRING)
log("%s(* %s=\"%s\" *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(s), x.decode_string().c_str());
else if (x.flags == RTLIL::CONST_FLAG_NONE)
log("%s(* %s=%s *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(s), x.as_string().c_str());
else
log_assert(x.flags == RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
size_t argidx = 1; size_t argidx = 1;
@ -42,29 +52,26 @@ struct PrintAttrsPass : public Pass {
unsigned int indent = 0; unsigned int indent = 0;
for (auto mod : design->selected_modules()) for (auto mod : design->selected_modules())
{ {
if (design->selected_whole_module(mod)) { if (design->selected_whole_module(mod)) {
log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(mod->name)); log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(mod->name));
indent += 2; indent += 2;
for (auto &it : mod->attributes) for (auto &it : mod->attributes)
log("%s(* %s=\"%s\" %s *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(it.first), it.second.decode_string().c_str(), it.second.as_string().c_str()); log_const(it.first, it.second, indent);
} }
for (auto cell : mod->selected_cells()) { for (auto cell : mod->selected_cells()) {
log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(cell->name)); log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(cell->name));
indent += 2; indent += 2;
for (auto &it : cell->attributes) { for (auto &it : cell->attributes)
log("%s(* %s=\"%s\" %s *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(it.first), it.second.decode_string().c_str(), it.second.as_string().c_str()); log_const(it.first, it.second, indent);
}
indent -= 2; indent -= 2;
} }
for (auto wire : mod->selected_wires()) { for (auto wire : mod->selected_wires()) {
log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(wire->name)); log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(wire->name));
indent += 2; indent += 2;
for (auto &it : wire->attributes) { for (auto &it : wire->attributes)
log("%s(* %s=\"%s\" %s *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(it.first), it.second.decode_string().c_str(), it.second.as_string().c_str()); log_const(it.first, it.second, indent);
}
indent -= 2; indent -= 2;
} }