mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-28 10:19:26 +00:00
Code Activity

Docs: Update internal cells to autoref

Browse source
This commit is contained in:
Krystine Sherwin 2024-05-03 13:14:25 +12:00
parent c0f9828b3c
commit e4ec3717bc
No known key found for this signature in database
12 changed files with 183 additions and 179 deletions
Download patch file Download diff file Expand all files Collapse all files

183
docs/source/yosys_internals/formats/cell_library.rst
View file

@ -73,15 +73,15 @@ also have the following parameters:
:verilog:`Y = !A` $logic_not
================== ============
For the unary cells that output a logical value (``$reduce_and``,
``$reduce_or``, ``$reduce_xor``, ``$reduce_xnor``, ``$reduce_bool``,
``$logic_not``), when the ``\Y_WIDTH`` parameter is greater than 1, the output
For the unary cells that output a logical value (`$reduce_and`,
`$reduce_or`, `$reduce_xor`, `$reduce_xnor`, `$reduce_bool`,
`$logic_not`), when the ``\Y_WIDTH`` parameter is greater than 1, the output
is zero-extended, and only the least significant bit varies.
Note that ``$reduce_or`` and ``$reduce_bool`` actually represent the same logic
Note that `$reduce_or` and `$reduce_bool` actually represent the same logic
function. But the HDL frontends generate them in different situations. A
``$reduce_or`` cell is generated when the prefix ``|`` operator is being used. A
``$reduce_bool`` cell is generated when a bit vector is used as a condition in
`$reduce_or` cell is generated when the prefix ``|`` operator is being used. A
`$reduce_bool` cell is generated when a bit vector is used as a condition in
an ``if``-statement or ``?:``-expression.
Binary operators
@ -130,28 +130,28 @@ All binary RTL cells have two input ports ``\A`` and ``\B`` and one output port
:verilog:`Y = A ** B` $pow ``N/A`` $modfloor
======================= ============= ======================= =========
The ``$shl`` and ``$shr`` cells implement logical shifts, whereas the ``$sshl``
and ``$sshr`` cells implement arithmetic shifts. The ``$shl`` and ``$sshl``
The `$shl` and `$shr` cells implement logical shifts, whereas the `$sshl`
and `$sshr` cells implement arithmetic shifts. The `$shl` and `$sshl`
cells implement the same operation. All four of these cells interpret the second
operand as unsigned, and require ``\B_SIGNED`` to be zero.
Two additional shift operator cells are available that do not directly
correspond to any operator in Verilog, ``$shift`` and ``$shiftx``. The
``$shift`` cell performs a right logical shift if the second operand is positive
(or unsigned), and a left logical shift if it is negative. The ``$shiftx`` cell
performs the same operation as the ``$shift`` cell, but the vacated bit
correspond to any operator in Verilog, `$shift` and `$shiftx`. The
`$shift` cell performs a right logical shift if the second operand is positive
(or unsigned), and a left logical shift if it is negative. The `$shiftx` cell
performs the same operation as the `$shift` cell, but the vacated bit
positions are filled with undef (x) bits, and corresponds to the Verilog indexed
part-select expression.
For the binary cells that output a logical value (``$logic_and``, ``$logic_or``,
``$eqx``, ``$nex``, ``$lt``, ``$le``, ``$eq``, ``$ne``, ``$ge``, ``$gt``), when
For the binary cells that output a logical value (`$logic_and`, `$logic_or`,
`$eqx`, `$nex`, `$lt`, `$le`, `$eq`, `$ne`, `$ge`, `$gt`), when
the ``\Y_WIDTH`` parameter is greater than 1, the output is zero-extended, and
only the least significant bit varies.
Division and modulo cells are available in two rounding modes. The original
``$div`` and ``$mod`` cells are based on truncating division, and correspond to
the semantics of the verilog ``/`` and ``%`` operators. The ``$divfloor`` and
``$modfloor`` cells represent flooring division and flooring modulo, the latter
`$div` and `$mod` cells are based on truncating division, and correspond to
the semantics of the verilog ``/`` and ``%`` operators. The `$divfloor` and
`$modfloor` cells represent flooring division and flooring modulo, the latter
of which is also known as "remainder" in several languages. See
:numref:`tab:CellLib_divmod` for a side-by-side comparison between the different
semantics.
@ -180,14 +180,14 @@ Multiplexers are generated by the Verilog HDL frontend for ``?:``-expressions.
Multiplexers are also generated by the proc pass to map the decision trees from
RTLIL::Process objects to logic.
The simplest multiplexer cell type is ``$mux``. Cells of this type have a
The simplest multiplexer cell type is `$mux`. Cells of this type have a
``\WITDH`` parameter and data inputs ``\A`` and ``\B`` and a data output ``\Y``,
all of the specified width. This cell also has a single bit control input
``\S``. If ``\S`` is 0 the value from the input ``\A`` is sent to the output, if
it is 1 the value from the ``\B`` input is sent to the output. So the ``$mux``
it is 1 the value from the ``\B`` input is sent to the output. So the `$mux`
cell implements the function :verilog:`Y = S ? B : A`.
The ``$pmux`` cell is used to multiplex between many inputs using a one-hot
The `$pmux` cell is used to multiplex between many inputs using a one-hot
select signal. Cells of this type have a ``\WIDTH`` and a ``\S_WIDTH`` parameter
and inputs ``\A``, ``\B``, and ``\S`` and an output ``\Y``. The ``\S`` input is
``\S_WIDTH`` bits wide. The ``\A`` input and the output are both ``\WIDTH`` bits
@ -199,24 +199,24 @@ from ``\S`` is set the output is undefined. Cells of this type are used to model
"parallel cases" (defined by using the ``parallel_case`` attribute or detected
by an optimization).
The ``$tribuf`` cell is used to implement tristate logic. Cells of this type
The `$tribuf` cell is used to implement tristate logic. Cells of this type
have a ``\WIDTH`` parameter and inputs ``\A`` and ``\EN`` and an output ``\Y``. The
``\A`` input and ``\Y`` output are ``\WIDTH`` bits wide, and the ``\EN`` input
is one bit wide. When ``\EN`` is 0, the output is not driven. When ``\EN`` is 1,
the value from ``\A`` input is sent to the ``\Y`` output. Therefore, the
``$tribuf`` cell implements the function :verilog:`Y = EN ? A : 'bz`.
`$tribuf` cell implements the function :verilog:`Y = EN ? A : 'bz`.
Behavioural code with cascaded if-then-else- and case-statements usually results
in trees of multiplexer cells. Many passes (from various optimizations to FSM
extraction) heavily depend on these multiplexer trees to understand dependencies
between signals. Therefore optimizations should not break these multiplexer
trees (e.g. by replacing a multiplexer between a calculated signal and a
constant zero with an ``$and`` gate).
constant zero with an `$and` gate).
Registers
~~~~~~~~~
SR-type latches are represented by ``$sr`` cells. These cells have input ports
SR-type latches are represented by `$sr` cells. These cells have input ports
``\SET`` and ``\CLR`` and an output port ``\Q``. They have the following
parameters:
@ -232,12 +232,12 @@ parameters:
``1'b1`` and active-low if this parameter is ``1'b0``.
Both set and reset inputs have separate bits for every output bit. When both the
set and reset inputs of an ``$sr`` cell are active for a given bit index, the
set and reset inputs of an `$sr` cell are active for a given bit index, the
reset input takes precedence.
D-type flip-flops are represented by ``$dff`` cells. These cells have a clock
D-type flip-flops are represented by `$dff` cells. These cells have a clock
port ``\CLK``, an input port ``\D`` and an output port ``\Q``. The following
parameters are available for ``$dff`` cells:
parameters are available for `$dff` cells:
``\WIDTH``
The width of input ``\D`` and output ``\Q``.
@ -246,8 +246,8 @@ parameters are available for ``$dff`` cells:
Clock is active on the positive edge if this parameter has the value
``1'b1`` and on the negative edge if this parameter is ``1'b0``.
D-type flip-flops with asynchronous reset are represented by ``$adff`` cells. As
the ``$dff`` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they
D-type flip-flops with asynchronous reset are represented by `$adff` cells. As
the `$dff` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they
also have a single-bit ``\ARST`` input port for the reset pin and the following
additional two parameters:
@ -261,8 +261,8 @@ additional two parameters:
Usually these cells are generated by the :cmd:ref:`proc` pass using the
information in the designs RTLIL::Process objects.
D-type flip-flops with synchronous reset are represented by ``$sdff`` cells. As
the ``$dff`` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they
D-type flip-flops with synchronous reset are represented by `$sdff` cells. As
the `$dff` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they
also have a single-bit ``\SRST`` input port for the reset pin and the following
additional two parameters:
@ -273,11 +273,11 @@ additional two parameters:
``\SRST_VALUE``
The state of ``\Q`` will be set to this value when the reset is active.
Note that the ``$adff`` and ``$sdff`` cells can only be used when the reset
Note that the `$adff` and `$sdff` cells can only be used when the reset
value is constant.
D-type flip-flops with asynchronous load are represented by ``$aldff`` cells. As
the ``$dff`` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they
D-type flip-flops with asynchronous load are represented by `$aldff` cells. As
the `$dff` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they
also have a single-bit ``\ALOAD`` input port for the async load enable pin, a
``\AD`` input port with the same width as data for the async load data, and the
following additional parameter:
@ -286,15 +286,15 @@ following additional parameter:
The asynchronous load is active-high if this parameter has the value
``1'b1`` and active-low if this parameter is ``1'b0``.
D-type flip-flops with asynchronous set and reset are represented by ``$dffsr``
cells. As the ``$dff`` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In
D-type flip-flops with asynchronous set and reset are represented by `$dffsr`
cells. As the `$dff` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In
addition they also have multi-bit ``\SET`` and ``\CLR`` input ports and the
corresponding polarity parameters, like ``$sr`` cells.
corresponding polarity parameters, like `$sr` cells.
D-type flip-flops with enable are represented by ``$dffe``, ``$adffe``,
``$aldffe``, ``$dffsre``, ``$sdffe``, and ``$sdffce`` cells, which are enhanced
variants of ``$dff``, ``$adff``, ``$aldff``, ``$dffsr``, ``$sdff`` (with reset
over enable) and ``$sdff`` (with enable over reset) cells, respectively. They
D-type flip-flops with enable are represented by `$dffe`, `$adffe`,
`$aldffe`, `$dffsre`, `$sdffe`, and `$sdffce` cells, which are enhanced
variants of `$dff`, `$adff`, `$aldff`, `$dffsr`, `$sdff` (with reset
over enable) and `$sdff` (with enable over reset) cells, respectively. They
have the same ports and parameters as their base cell. In addition they also
have a single-bit ``\EN`` input port for the enable pin and the following
parameter:
@ -303,9 +303,9 @@ parameter:
The enable input is active-high if this parameter has the value ``1'b1``
and active-low if this parameter is ``1'b0``.
D-type latches are represented by ``$dlatch`` cells. These cells have an enable
D-type latches are represented by `$dlatch` cells. These cells have an enable
port ``\EN``, an input port ``\D``, and an output port ``\Q``. The following
parameters are available for ``$dlatch`` cells:
parameters are available for `$dlatch` cells:
``\WIDTH``
The width of input ``\D`` and output ``\Q``.
@ -316,8 +316,8 @@ parameters are available for ``$dlatch`` cells:
The latch is transparent when the ``\EN`` input is active.
D-type latches with reset are represented by ``$adlatch`` cells. In addition to
``$dlatch`` ports and parameters, they also have a single-bit ``\ARST`` input
D-type latches with reset are represented by `$adlatch` cells. In addition to
`$dlatch` ports and parameters, they also have a single-bit ``\ARST`` input
port for the reset pin and the following additional parameters:
``\ARST_POLARITY``
@ -327,9 +327,9 @@ port for the reset pin and the following additional parameters:
``\ARST_VALUE``
The state of ``\Q`` will be set to this value when the reset is active.
D-type latches with set and reset are represented by ``$dlatchsr`` cells. In
addition to ``$dlatch`` ports and parameters, they also have multi-bit ``\SET``
and ``\CLR`` input ports and the corresponding polarity parameters, like ``$sr``
D-type latches with set and reset are represented by `$dlatchsr` cells. In
addition to `$dlatch` ports and parameters, they also have multi-bit ``\SET``
and ``\CLR`` input ports and the corresponding polarity parameters, like `$sr`
cells.
.. _sec:memcells:
@ -337,20 +337,20 @@ cells.
Memories
~~~~~~~~
Memories are either represented using ``RTLIL::Memory`` objects, ``$memrd_v2``,
``$memwr_v2``, and ``$meminit_v2`` cells, or by ``$mem_v2`` cells alone.
Memories are either represented using ``RTLIL::Memory`` objects, `$memrd_v2`,
`$memwr_v2`, and `$meminit_v2` cells, or by `$mem_v2` cells alone.
In the first alternative the ``RTLIL::Memory`` objects hold the general metadata
for the memory (bit width, size in number of words, etc.) and for each port a
``$memrd_v2`` (read port) or ``$memwr_v2`` (write port) cell is created. Having
`$memrd_v2` (read port) or `$memwr_v2` (write port) cell is created. Having
individual cells for read and write ports has the advantage that they can be
consolidated using resource sharing passes. In some cases this drastically
reduces the number of required ports on the memory cell. In this alternative,
memory initialization data is represented by ``$meminit_v2`` cells, which allow
memory initialization data is represented by `$meminit_v2` cells, which allow
delaying constant folding for initialization addresses and data until after the
frontend finishes.
The ``$memrd_v2`` cells have a clock input ``\CLK``, an enable input ``\EN``, an
The `$memrd_v2` cells have a clock input ``\CLK``, an enable input ``\EN``, an
address input ``\ADDR``, a data output ``\DATA``, an asynchronous reset input
``\ARST``, and a synchronous reset input ``\SRST``. They also have the following
parameters:
@ -411,7 +411,7 @@ parameters:
when ``\EN`` is true. Otherwise, ``\SRST`` is recognized regardless of
``\EN``.
The ``$memwr_v2`` cells have a clock input ``\CLK``, an enable input ``\EN``
The `$memwr_v2` cells have a clock input ``\CLK``, an enable input ``\EN``
(one enable bit for each data bit), an address input ``\ADDR`` and a data input
``\DATA``. They also have the following parameters:
@ -424,7 +424,7 @@ The ``$memwr_v2`` cells have a clock input ``\CLK``, an enable input ``\EN``
``\WIDTH``
The number of data bits (width of the ``\DATA`` output port). Like with
``$memrd_v2`` cells, the width is allowed to be any power-of-two
`$memrd_v2` cells, the width is allowed to be any power-of-two
multiple of memory width, with the corresponding restriction on address.
``\CLK_ENABLE``
@ -448,7 +448,7 @@ The ``$memwr_v2`` cells have a clock input ``\CLK``, an enable input ``\EN``
undefined. Priority can only be set between two synchronous ports sharing
the same clock domain.
The ``$meminit_v2`` cells have an address input ``\ADDR``, a data input
The `$meminit_v2` cells have an address input ``\ADDR``, a data input
``\DATA``, with the width of the ``\DATA`` port equal to ``\WIDTH`` parameter
times ``\WORDS`` parameter, and a bit enable mask input ``\EN`` with width equal
to ``\WIDTH`` parameter. All three of the inputs must resolve to a constant for
@ -472,19 +472,19 @@ synthesis to succeed.
initialization conflict.
The HDL frontend models a memory using ``RTLIL::Memory`` objects and
asynchronous ``$memrd_v2`` and ``$memwr_v2`` cells. The :cmd:ref:`memory` pass
(i.e. its various sub-passes) migrates ``$dff`` cells into the ``$memrd_v2`` and
``$memwr_v2`` cells making them synchronous, then converts them to a single
``$mem_v2`` cell and (optionally) maps this cell type to ``$dff`` cells for the
asynchronous `$memrd_v2` and `$memwr_v2` cells. The :cmd:ref:`memory` pass
(i.e. its various sub-passes) migrates `$dff` cells into the `$memrd_v2` and
`$memwr_v2` cells making them synchronous, then converts them to a single
`$mem_v2` cell and (optionally) maps this cell type to `$dff` cells for the
individual words and multiplexer-based address decoders for the read and write
interfaces. When the last step is disabled or not possible, a ``$mem_v2`` cell
interfaces. When the last step is disabled or not possible, a `$mem_v2` cell
is left in the design.
The ``$mem_v2`` cell provides the following parameters:
The `$mem_v2` cell provides the following parameters:
``\MEMID``
The name of the original ``RTLIL::Memory`` object that became this
``$mem_v2`` cell.
`$mem_v2` cell.
``\SIZE``
The number of words in the memory.
@ -519,12 +519,12 @@ The ``$mem_v2`` cell provides the following parameters:
``\RD_TRANSPARENCY_MASK``
This parameter is ``\RD_PORTS*\WR_PORTS`` bits wide, containing a
concatenation of all ``\TRANSPARENCY_MASK`` values of the original
``$memrd_v2`` cells.
`$memrd_v2` cells.
``\RD_COLLISION_X_MASK``
This parameter is ``\RD_PORTS*\WR_PORTS`` bits wide, containing a
concatenation of all ``\COLLISION_X_MASK`` values of the original
``$memrd_v2`` cells.
`$memrd_v2` cells.
``\RD_CE_OVER_SRST``
This parameter is ``\RD_PORTS`` bits wide, determining relative
@ -560,9 +560,9 @@ The ``$mem_v2`` cell provides the following parameters:
``\WR_PRIORITY_MASK``
This parameter is ``\WR_PORTS*\WR_PORTS`` bits wide, containing a
concatenation of all ``\PRIORITY_MASK`` values of the original
``$memwr_v2`` cells.
`$memwr_v2` cells.
The ``$mem_v2`` cell has the following ports:
The `$mem_v2` cell has the following ports:
``\RD_CLK``
This input is ``\RD_PORTS`` bits wide, containing all clock signals for
@ -605,24 +605,24 @@ The ``$mem_v2`` cell has the following ports:
signals for the write ports.
The :cmd:ref:`memory_collect` pass can be used to convert discrete
``$memrd_v2``, ``$memwr_v2``, and ``$meminit_v2`` cells belonging to the same
memory to a single ``$mem_v2`` cell, whereas the :cmd:ref:`memory_unpack` pass
`$memrd_v2`, `$memwr_v2`, and `$meminit_v2` cells belonging to the same
memory to a single `$mem_v2` cell, whereas the :cmd:ref:`memory_unpack` pass
performs the inverse operation. The :cmd:ref:`memory_dff` pass can combine
asynchronous memory ports that are fed by or feeding registers into synchronous
memory ports. The :cmd:ref:`memory_bram` pass can be used to recognize
``$mem_v2`` cells that can be implemented with a block RAM resource on an FPGA.
The :cmd:ref:`memory_map` pass can be used to implement ``$mem_v2`` cells as
`$mem_v2` cells that can be implemented with a block RAM resource on an FPGA.
The :cmd:ref:`memory_map` pass can be used to implement `$mem_v2` cells as
basic logic: word-wide DFFs and address decoders.
Finite state machines
~~~~~~~~~~~~~~~~~~~~~
Add a brief description of the ``$fsm`` cell type.
Add a brief description of the `$fsm` cell type.
Coarse arithmetics
~~~~~~~~~~~~~~~~~~~~~
The ``$macc`` cell type represents a generalized multiply and accumulate operation. The cell is purely combinational. It outputs the result of summing up a sequence of products and other injected summands.
The `$macc` cell type represents a generalized multiply and accumulate operation. The cell is purely combinational. It outputs the result of summing up a sequence of products and other injected summands.
.. code-block::
@ -708,21 +708,21 @@ in the ``\TABLE`` values.
Specify rules
~~~~~~~~~~~~~
Add information about ``$specify2``, ``$specify3``, and ``$specrule`` cells.
Add information about `$specify2`, `$specify3`, and `$specrule` cells.
Formal verification cells
~~~~~~~~~~~~~~~~~~~~~~~~~
Add information about ``$check``, ``$assert``, ``$assume``, ``$live``, ``$fair``,
``$cover``, ``$equiv``, ``$initstate``, ``$anyconst``, ``$anyseq``,
``$anyinit``, ``$allconst``, ``$allseq`` cells.
Add information about `$check`, `$assert`, `$assume`, `$live`, `$fair`,
`$cover`, `$equiv`, `$initstate`, `$anyconst`, `$anyseq`,
`$anyinit`, `$allconst`, `$allseq` cells.
Add information about ``$ff`` and ``$_FF_`` cells.
Add information about `$ff` and `$_FF_` cells.
Debugging cells
~~~~~~~~~~~~~~~
The ``$print`` cell is used to log the values of signals, akin to (and
The `$print` cell is used to log the values of signals, akin to (and
translatable to) the ``$display`` and ``$write`` family of tasks in Verilog. It
has the following parameters:
@ -746,13 +746,14 @@ If ``\TRG_ENABLE`` is true, the following parameters also apply:
negative-edge triggered.
``\PRIORITY``
When multiple ``$print`` or ``$$check`` cells fire on the same trigger, they\
When multiple `$print` or `$check` cells fire on the same trigger, they
execute in descending priority order.
Ports:
``\TRG``
The signals that control when this ``$print`` cell is triggered.
The signals that control when this `$print` cell is triggered.
If the width of this port is zero and ``\TRG_ENABLE`` is true, the cell is
triggered during initial evaluation (time zero) only.
@ -1040,14 +1041,14 @@ Tables :numref:`%s <tab:CellLib_gates>`, :numref:`%s <tab:CellLib_gates_dffe>`,
:numref:`%s <tab:CellLib_gates_dffsr>`, :numref:`%s <tab:CellLib_gates_dffsre>`,
:numref:`%s <tab:CellLib_gates_adlatch>`, :numref:`%s
<tab:CellLib_gates_dlatchsr>` and :numref:`%s <tab:CellLib_gates_sr>` list all
cell types used for gate level logic. The cell types ``$_BUF_``, ``$_NOT_``,
``$_AND_``, ``$_NAND_``, ``$_ANDNOT_``, ``$_OR_``, ``$_NOR_``, ``$_ORNOT_``,
``$_XOR_``, ``$_XNOR_``, ``$_AOI3_``, ``$_OAI3_``, ``$_AOI4_``, ``$_OAI4_``,
``$_MUX_``, ``$_MUX4_``, ``$_MUX8_``, ``$_MUX16_`` and ``$_NMUX_`` are used to
model combinatorial logic. The cell type ``$_TBUF_`` is used to model tristate
cell types used for gate level logic. The cell types `$_BUF_`, `$_NOT_`,
`$_AND_`, `$_NAND_`, `$_ANDNOT_`, `$_OR_`, `$_NOR_`, `$_ORNOT_`,
`$_XOR_`, `$_XNOR_`, `$_AOI3_`, `$_OAI3_`, `$_AOI4_`, `$_OAI4_`,
`$_MUX_`, `$_MUX4_`, `$_MUX8_`, `$_MUX16_` and `$_NMUX_` are used to
model combinatorial logic. The cell type `$_TBUF_` is used to model tristate
logic.
The ``$_MUX4_``, ``$_MUX8_`` and ``$_MUX16_`` cells are used to model wide
The `$_MUX4_`, `$_MUX8_` and `$_MUX16_` cells are used to model wide
muxes, and correspond to the following Verilog code:
.. code-block:: verilog
@ -1071,7 +1072,7 @@ muxes, and correspond to the following Verilog code:
T ? (S ? D : C) :
(S ? B : A);
The cell types ``$_DFF_N_`` and ``$_DFF_P_`` represent d-type flip-flops.
The cell types `$_DFF_N_` and `$_DFF_P_` represent d-type flip-flops.
The cell types ``$_DFFE_[NP][NP]_`` implement d-type flip-flops with enable. The
values in the table for these cell types relate to the following Verilog code
@ -1186,7 +1187,7 @@ is ``posedge`` if ``SET_LVL`` if ``1``, ``negedge`` otherwise.
else if (E == EN_LVL)
Q <= D;
The cell types ``$_DLATCH_N_`` and ``$_DLATCH_P_`` represent d-type latches.
The cell types `$_DLATCH_N_` and `$_DLATCH_P_` represent d-type latches.
The cell types ``$_DLATCH_[NP][NP][01]_`` implement d-type latches with reset.
The values in the table for these cell types relate to the following Verilog
@ -1234,8 +1235,8 @@ mapped to physical flip-flop cells from a Liberty file using the dfflibmap pass.
The combinatorial logic cells can be mapped to physical cells from a Liberty
file via ABC using the abc pass.
.. todo:: Add information about ``$slice`` and ``$concat`` cells.
.. todo:: Add information about `$slice` and `$concat` cells.
.. todo:: Add information about ``$alu``, ``$fa``, and ``$lcu`` cells.
.. todo:: Add information about `$alu`, `$fa`, and `$lcu` cells.
.. todo:: Add information about ``$demux`` cell.

16
docs/source/yosys_internals/formats/rtlil_rep.rst
View file

@ -79,7 +79,7 @@ This has three advantages:
example, :cmd:ref:`opt_clean` tries to preserve signals with a user-provided
name but doesn't hesitate to delete signals that have auto-generated names
when they just duplicate other signals. Note that this can be overridden
with the `-purge` option to also delete internal nets with user-provided
with the ``-purge`` option to also delete internal nets with user-provided
names.
- Third, the delicate job of finding suitable auto-generated public visible
@ -366,7 +366,7 @@ multiplexer for the enable signal:
end
Different combinations of passes may yield different results. Note that
``$adff`` and ``$mux`` are internal cell types that still need to be mapped to
`$adff` and `$mux` are internal cell types that still need to be mapped to
cell types from the target cell library.
Some passes refuse to operate on modules that still contain ``RTLIL::Process``
@ -389,25 +389,25 @@ A memory object has the following properties:
- The width of an addressable word
- The size of the memory in number of words
All read accesses to the memory are transformed to ``$memrd`` cells and all
write accesses to ``$memwr`` cells by the language frontend. These cells consist
All read accesses to the memory are transformed to `$memrd` cells and all
write accesses to `$memwr` cells by the language frontend. These cells consist
of independent read- and write-ports to the memory. Memory initialization is
transformed to ``$meminit`` cells by the language frontend. The ``\MEMID``
transformed to `$meminit` cells by the language frontend. The ``\MEMID``
parameter on these cells is used to link them together and to the
``RTLIL::Memory`` object they belong to.
The rationale behind using separate cells for the individual ports versus
creating a large multiport memory cell right in the language frontend is that
the separate ``$memrd`` and ``$memwr`` cells can be consolidated using resource
the separate `$memrd` and `$memwr` cells can be consolidated using resource
sharing. As resource sharing is a non-trivial optimization problem where
different synthesis tasks can have different requirements it lends itself to do
the optimisation in separate passes and merge the ``RTLIL::Memory`` objects and
``$memrd`` and ``$memwr`` cells to multiport memory blocks after resource
`$memrd` and `$memwr` cells to multiport memory blocks after resource
sharing is completed.
The memory pass performs this conversion and can (depending on the options
passed to it) transform the memories directly to d-type flip-flops and address
logic or yield multiport memory blocks (represented using ``$mem`` cells).
logic or yield multiport memory blocks (represented using `$mem` cells).
See :ref:`sec:memcells` for details about the memory cell types.