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	Docs: Update internal cells to autoref
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		|  | @ -31,7 +31,7 @@ described in :doc:`/yosys_internals/formats/cell_library`. This means a cell | |||
| with all constant inputs is replaced with the constant value this cell drives. | ||||
| In some cases this pass can also optimize cells with some constant inputs. | ||||
| 
 | ||||
| .. table:: Const folding rules for ``$_AND_`` cells as used in :cmd:ref:`opt_expr`. | ||||
| .. table:: Const folding rules for `$_AND_` cells as used in :cmd:ref:`opt_expr`. | ||||
|    :name: tab:opt_expr_and | ||||
|    :align: center | ||||
| 
 | ||||
|  | @ -54,7 +54,7 @@ In some cases this pass can also optimize cells with some constant inputs. | |||
|    ========= ========= =========== | ||||
| 
 | ||||
| :numref:`Table %s <tab:opt_expr_and>` shows the replacement rules used for | ||||
| optimizing an ``$_AND_`` gate. The first three rules implement the obvious const | ||||
| optimizing an `$_AND_` gate. The first three rules implement the obvious const | ||||
| folding rules. Note that 'any' might include dynamic values calculated by other | ||||
| parts of the circuit. The following three lines propagate undef (X) states. | ||||
| These are the only three cases in which it is allowed to propagate an undef | ||||
|  | @ -66,18 +66,18 @@ substitutions are possible they are performed first, in the hope that the 'any' | |||
| will change to an undef value or a 1 and therefore the output can be set to | ||||
| undef. | ||||
| 
 | ||||
| The last two lines simply replace an ``$_AND_`` gate with one constant-1 input | ||||
| The last two lines simply replace an `$_AND_` gate with one constant-1 input | ||||
| with a buffer. | ||||
| 
 | ||||
| Besides this basic const folding the :cmd:ref:`opt_expr` pass can replace 1-bit | ||||
| wide ``$eq`` and ``$ne`` cells with buffers or not-gates if one input is | ||||
| wide `$eq` and `$ne` cells with buffers or not-gates if one input is | ||||
| constant.  Equality checks may also be reduced in size if there are redundant | ||||
| bits in the arguments (i.e. bits which are constant on both inputs).  This can, | ||||
| for example, result in a 32-bit wide constant like ``255`` being reduced to the | ||||
| 8-bit value of ``8'11111111`` if the signal being compared is only 8-bit as in | ||||
| :ref:`addr_gen_clean` of :doc:`/getting_started/example_synth`. | ||||
| 
 | ||||
| The :cmd:ref:`opt_expr` pass is very conservative regarding optimizing ``$mux`` | ||||
| The :cmd:ref:`opt_expr` pass is very conservative regarding optimizing `$mux` | ||||
| cells, as these cells are often used to model decision-trees and breaking these | ||||
| trees can interfere with other optimizations. | ||||
| 
 | ||||
|  | @ -100,7 +100,7 @@ identifies cells with identical inputs and replaces them with a single instance | |||
| of the cell. | ||||
| 
 | ||||
| The option ``-nomux`` can be used to disable resource sharing for multiplexer | ||||
| cells (``$mux`` and ``$pmux``.) This can be useful as it prevents multiplexer | ||||
| cells (`$mux` and `$pmux`.) This can be useful as it prevents multiplexer | ||||
| trees to be merged, which might prevent :cmd:ref:`opt_muxtree` to identify | ||||
| possible optimizations. | ||||
| 
 | ||||
|  | @ -141,16 +141,16 @@ Simplifying large MUXes and AND/OR gates - :cmd:ref:`opt_reduce` | |||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||||
| 
 | ||||
| This is a simple optimization pass that identifies and consolidates identical | ||||
| input bits to ``$reduce_and`` and ``$reduce_or`` cells. It also sorts the input | ||||
| bits to ease identification of shareable ``$reduce_and`` and ``$reduce_or`` | ||||
| input bits to `$reduce_and` and `$reduce_or` cells. It also sorts the input | ||||
| bits to ease identification of shareable `$reduce_and` and `$reduce_or` | ||||
| cells in other passes. | ||||
| 
 | ||||
| This pass also identifies and consolidates identical inputs to multiplexer | ||||
| cells. In this case the new shared select bit is driven using a ``$reduce_or`` | ||||
| cells. In this case the new shared select bit is driven using a `$reduce_or` | ||||
| cell that combines the original select bits. | ||||
| 
 | ||||
| Lastly this pass consolidates trees of ``$reduce_and`` cells and trees of | ||||
| ``$reduce_or`` cells to single large ``$reduce_and`` or ``$reduce_or`` cells. | ||||
| Lastly this pass consolidates trees of `$reduce_and` cells and trees of | ||||
| `$reduce_or` cells to single large `$reduce_and` or `$reduce_or` cells. | ||||
| 
 | ||||
| These three simple optimizations are performed in a loop until a stable result | ||||
| is produced. | ||||
|  | @ -160,7 +160,7 @@ Merging mutually exclusive cells with shared inputs - :cmd:ref:`opt_share` | |||
| 
 | ||||
| This pass identifies mutually exclusive cells of the same type that: | ||||
|    a. share an input signal, and | ||||
|    b. drive the same ``$mux``, ``$_MUX_``, or ``$pmux`` multiplexing cell, | ||||
|    b. drive the same `$mux`, `$_MUX_`, or `$pmux` multiplexing cell, | ||||
| 
 | ||||
| allowing the cell to be merged and the multiplexer to be moved from | ||||
| multiplexing its output to multiplexing the non-shared input signals. | ||||
|  | @ -176,14 +176,14 @@ multiplexing its output to multiplexing the non-shared input signals. | |||
| 
 | ||||
|    Before and after :cmd:ref:`opt_share` | ||||
| 
 | ||||
| When running :cmd:ref:`opt` in full, the original ``$mux`` (labeled ``$3``) is | ||||
| When running :cmd:ref:`opt` in full, the original `$mux` (labeled ``$3``) is | ||||
| optimized away by :cmd:ref:`opt_expr`. | ||||
| 
 | ||||
| Performing DFF optimizations - :cmd:ref:`opt_dff` | ||||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||||
| 
 | ||||
| This pass identifies single-bit d-type flip-flops (``$_DFF_``, ``$dff``, and | ||||
| ``$adff`` cells) with a constant data input and replaces them with a constant | ||||
| This pass identifies single-bit d-type flip-flops (`$_DFF_`, `$dff`, and | ||||
| `$adff` cells) with a constant data input and replaces them with a constant | ||||
| driver.  It can also merge clock enables and synchronous reset multiplexers, | ||||
| removing unused control inputs. | ||||
| 
 | ||||
|  |  | |||
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