Merge pull request #145 from laanwj/master

Add instructions for building manual on Ubuntu

README

@@ -383,3 +383,32 @@ from SystemVerilog:
 - The keywords "always_comb", "always_ff" and "always_latch", "logic" and
   "bit" are supported.
 
+Building the documentation
+==========================
+
+On Ubuntu, texlive needs these packages to be able to build the manual:
+
+	sudo apt-get install texlive-binaries
+	sudo apt-get install texlive-science      # install algorithm2e.sty
+	sudo apt-get install texlive-bibtex-extra # gets multibib.sty
+	sudo apt-get install texlive-fonts-extra  # gets skull.sty and dsfont.sty
+	sudo apt-get install texlive-publishers   # IEEEtran.cls
+
+Also the non-free font luximono should be installed, there is unfortulately
+no Ubuntu package for this so it should be installed separately using
+`getnonfreefonts`:
+
+	wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
+	sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
+	getnonfreefonts luximono # installs to /home/user/texmf
+
+Then execute, from the root of the repository:
+
+	make manual
+
+Notes:
+
+- To run `make manual` you need to have installed yosys with `make install`,
+  otherwise it will fail on finding `kernel/yosys.h` while building
+  `PRESENTATION_Prog`.
+

manual/manual.tex

@@ -151,14 +151,14 @@ availability of a Free and Open Source (FOSS) synthesis tool that can be used
 as basis for custom tools would be helpful.
 
 In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys) was
-developped. This document covers the design and implementation of this tool.
+developed. This document covers the design and implementation of this tool.
 At the moment the main focus of Yosys lies on the high-level aspects of
 digital synthesis. The pre-existing FOSS logic-synthesis tool ABC is used
 by Yosys to perform advanced gate-level optimizations.
 
 An evaluation of Yosys based on real-world designs is included. It is shown
 that Yosys can be used as-is to synthesize such designs. The results produced
-by Yosys in this tests where successflly verified using formal verification
+by Yosys in this tests where successfully verified using formal verification
 and are comparable in quality to the results produced by a commercial
 synthesis tool.
 
@@ -172,7 +172,7 @@ University of Technology \cite{BACC}.
 AIG         & And-Inverter-Graph \\
 ASIC        & Application-Specific Integrated Circuit \\
 AST         & Abstract Syntax Tree \\
-BDD         & Binary Decicion Diagram \\
+BDD         & Binary Decision Diagram \\
 BLIF        & Berkeley Logic Interchange Format \\
 EDA         & Electronic Design Automation \\
 EDIF        & Electronic Design Interchange Format \\