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gowin: Use memory_libmap pass.

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This commit is contained in:
Marcelina Kościelnicka 2022-02-09 09:25:45 +01:00
parent 0a8eaca322
commit e4d811561c
9 changed files with 565 additions and 255 deletions
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83
techlibs/gowin/lutrams_map.v
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@ -1,32 +1,65 @@
module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 4;
parameter CFG_DBITS = 4;
module $__GOWIN_LUTRAM_(...);
parameter [63:0] INIT = 64'bx;
input CLK1;
parameter INIT = 64'bx;
parameter BITS_USED = 0;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input PORT_W_CLK;
input [3:0] PORT_W_ADDR;
input PORT_W_WR_EN;
input [3:0] PORT_W_WR_DATA;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input B1EN;
input [3:0] PORT_R_ADDR;
output [3:0] PORT_R_RD_DATA;
`include "brams_init3.vh"
function [15:0] init_slice;
input integer idx;
integer i;
for (i = 0; i < 16; i = i + 1)
init_slice[i] = INIT[4*i+idx];
endfunction
RAM16SDP4
#(.INIT_0(INIT_0),
.INIT_1(INIT_1),
.INIT_2(INIT_2),
.INIT_3(INIT_3))
_TECHMAP_REPLACE_
(.WAD(B1ADDR),
.RAD(A1ADDR),
.DI(B1DATA),
.DO(A1DATA),
.CLK(CLK1),
.WRE(B1EN));
generate
casez(BITS_USED)
4'b000z:
RAM16SDP1 #(
.INIT_0(init_slice(0)),
) _TECHMAP_REPLACE_ (
.WAD(PORT_W_ADDR),
.RAD(PORT_R_ADDR),
.DI(PORT_W_WR_DATA[0]),
.DO(PORT_R_RD_DATA[0]),
.CLK(PORT_W_CLK),
.WRE(PORT_W_WR_EN)
);
4'b00zz:
RAM16SDP2 #(
.INIT_0(init_slice(0)),
.INIT_1(init_slice(1)),
) _TECHMAP_REPLACE_ (
.WAD(PORT_W_ADDR),
.RAD(PORT_R_ADDR),
.DI(PORT_W_WR_DATA[1:0]),
.DO(PORT_R_RD_DATA[1:0]),
.CLK(PORT_W_CLK),
.WRE(PORT_W_WR_EN)
);
default:
RAM16SDP4 #(
.INIT_0(init_slice(0)),
.INIT_1(init_slice(1)),
.INIT_2(init_slice(2)),
.INIT_3(init_slice(3)),
) _TECHMAP_REPLACE_ (
.WAD(PORT_W_ADDR),
.RAD(PORT_R_ADDR),
.DI(PORT_W_WR_DATA),
.DO(PORT_R_RD_DATA),
.CLK(PORT_W_CLK),
.WRE(PORT_W_WR_EN)
);
endcase
endgenerate
endmodule