3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00

cxxrtl: don't overwrite buffered inputs.

Before this commit, a cell's input was always assigned like:

    p_cell.p_input = (value...);

If `p_input` is buffered (e.g. if the design is built at -O0), this
is not correct. (In practice, this breaks clocking.) Unfortunately,
the incorrect design was compiled without diagnostics because wire<>
was move-assignable and also implicitly constructible from value<>.

After this commit, cell inputs are no longer incorrectly assumed to
always be unbuffered, and wires are not assignable from values.
This commit is contained in:
whitequark 2020-12-11 23:30:32 +00:00
parent ec410c9b19
commit e4aa8bc96b
2 changed files with 33 additions and 25 deletions

View file

@ -659,7 +659,7 @@ struct wire {
value<Bits> next;
wire() = default;
constexpr wire(const value<Bits> &init) : curr(init), next(init) {}
explicit constexpr wire(const value<Bits> &init) : curr(init), next(init) {}
template<typename... Init>
explicit constexpr wire(Init ...init) : curr{init...}, next{init...} {}