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Fixed wrong declaration in Verilog backend

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This commit is contained in:
dh73 2017-10-01 11:11:32 -05:00
parent cbaba62401
commit e480847753
1 changed files with 3 additions and 3 deletions
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6
backends/verilog/verilog_backend.cc
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@ -175,7 +175,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
if (set_signed && val < 0) if (set_signed && val < 0)
f << stringf("-32'sd%u", -val); f << stringf("-32'sd%u", -val);
else { else {
if(!nobasenradix) if(nobasenradix)
f << stringf("%u", val); // There's no signed parameter on megawizard IP f << stringf("%u", val); // There's no signed parameter on megawizard IP
else else
f << stringf("32'%sd%u", set_signed ? "s" : "", val); f << stringf("32'%sd%u", set_signed ? "s" : "", val);
@ -1585,8 +1585,8 @@ struct VerilogBackend : public Backend {
continue; continue;
} }
if (arg == "-nobasenradix") { if (arg == "-nobasenradix") {
defparam = true; nobasenradix = true;
continue; continue;
} }
if (arg == "-blackboxes") { if (arg == "-blackboxes") {
blackboxes = true; blackboxes = true;