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Tiny fixes to verilog parser

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Clifford Wolf 2013-03-23 18:54:31 +01:00
parent bee57c808a
commit e45d1c8865
2 changed files with 9 additions and 1 deletions
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7
frontends/verilog/parser.y
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@ -209,7 +209,12 @@ module:
};
module_para_opt:
'#' '(' TOK_PARAMETER param_decl_list optional_comma ')' | /* empty */;
'#' '(' module_para_list ')' | /* empty */;
module_para_list:
TOK_PARAMETER single_param_decl |
TOK_PARAMETER single_param_decl ',' module_para_list |
/* empty */;
module_args_opt:
'(' ')' | /* empty */ | '(' module_args optional_comma ')';