From e41ea6788e7fb438536ff41664a0fac4719a22fd Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 24 Jun 2026 17:39:13 +0200 Subject: [PATCH] genrtlil: intern action src as verbatim Twine add(std::string) tags bare strings as public names, so a single-source concat (which returns the lone ref unchanged) decoded with a spurious '\' prefix, splitting one source file into two in linecoverage output. add(Twine{}) stores the location string verbatim like set_src_attr. Co-Authored-By: Claude Opus 4.8 --- frontends/ast/genrtlil.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 72de09b66..cdedcc2dc 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -634,7 +634,7 @@ struct AST_INTERNAL::ProcessGenerator if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute(ID::nosync)) rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size()); remove_unwanted_lvalue_bits(lhs, rhs); - actions.push_back({lhs, rhs, ast ? current_module->design->twines.add(std::string{ast->loc_string()}) : Twine::Null}); + actions.push_back({lhs, rhs, ast ? current_module->design->twines.add(Twine{ast->loc_string()}) : Twine::Null}); offset += lhs.size(); } } @@ -690,7 +690,7 @@ struct AST_INTERNAL::ProcessGenerator current_case_assigned_bits.insert(bit); remove_unwanted_lvalue_bits(lvalue, rvalue); - current_case->actions.push_back({lvalue, rvalue, current_module->design->twines.add(std::string{ast->loc_string()})}); + current_case->actions.push_back({lvalue, rvalue, current_module->design->twines.add(Twine{ast->loc_string()})}); } break; @@ -842,8 +842,8 @@ struct AST_INTERNAL::ProcessGenerator Wire *en = current_module->addWire(current_module->design->twines.add(std::string{sstr.str() + "_EN"}), 1); set_src_attr(en, ast); - proc->root_case.actions.push_back({en, SigSpec(false), current_module->design->twines.add(std::string{ast->loc_string()})}); - current_case->actions.push_back({en, SigSpec(true), current_module->design->twines.add(std::string{ast->loc_string()})}); + proc->root_case.actions.push_back({en, SigSpec(false), current_module->design->twines.add(Twine{ast->loc_string()})}); + current_case->actions.push_back({en, SigSpec(true), current_module->design->twines.add(Twine{ast->loc_string()})}); RTLIL::SigSpec triggers; RTLIL::Const::Builder polarity_builder; @@ -940,8 +940,8 @@ struct AST_INTERNAL::ProcessGenerator Wire *en = current_module->addWire(current_module->design->twines.add(std::string{cellname.str() + "_EN"}), 1); set_src_attr(en, ast); - proc->root_case.actions.push_back({en, SigSpec(false), current_module->design->twines.add(std::string{ast->loc_string()})}); - current_case->actions.push_back({en, SigSpec(true), current_module->design->twines.add(std::string{ast->loc_string()})}); + proc->root_case.actions.push_back({en, SigSpec(false), current_module->design->twines.add(Twine{ast->loc_string()})}); + current_case->actions.push_back({en, SigSpec(true), current_module->design->twines.add(Twine{ast->loc_string()})}); RTLIL::SigSpec triggers; RTLIL::Const::Builder polarity_builder;