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Refactored uses of log_id()

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Codexplorer 2026-05-08 00:01:43 -07:00
parent 89d83a3410
commit e41b969da2
186 changed files with 1219 additions and 1220 deletions
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4
techlibs/xilinx/xilinx_dffopt.cc
View file

@ -131,7 +131,7 @@ struct XilinxDffOptPass : public Pass {
for (auto module : design->selected_modules())
{
log("Optimizing FFs in %s.\n", log_id(module));
log("Optimizing FFs in %s.\n", module);
SigMap sigmap(module);
dict<SigBit, pair<LutData, Cell *>> bit_to_lut;
@ -305,7 +305,7 @@ unmap:
if (worthy_post_r) ports += " + R";
if (worthy_post_s) ports += " + S";
if (worthy_post_ce) ports += " + CE";
log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, cell, sig_Q.wire, GetSize(lut_d.second), GetSize(final_lut.second));
// Okay, we're doing it. Unmap ports.
if (worthy_post_r) {

52
techlibs/xilinx/xilinx_dsp.cc
View file

@ -140,7 +140,7 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
}
}
log("Analysing %s.%s for Xilinx DSP SIMD12 packing.\n", log_id(module), log_id(lane1));
log("Analysing %s.%s for Xilinx DSP SIMD12 packing.\n", module, lane1);
Cell *cell = addDsp(module);
cell->setParam(ID(USE_SIMD), Const("FOUR12"));
@ -221,7 +221,7 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
Cell *lane2 = simd24.front();
simd24.pop_front();
log("Analysing %s.%s for Xilinx DSP SIMD24 packing.\n", log_id(module), log_id(lane1));
log("Analysing %s.%s for Xilinx DSP SIMD24 packing.\n", module, lane1);
Cell *cell = addDsp(module);
cell->setParam(ID(USE_SIMD), Const("TWO24"));
@ -260,7 +260,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
{
auto &st = pm.st_xilinx_dsp_pack;
log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
log("Analysing %s.%s for Xilinx DSP packing.\n", pm.module, st.dsp);
log_debug("preAdd: %s\n", log_id(st.preAdd, "--"));
log_debug("preSub: %s\n", log_id(st.preSub, "--"));
@ -282,7 +282,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (st.preAdd || st.preSub) {
Cell* preAdder = st.preAdd ? st.preAdd : st.preSub;
log(" preadder %s (%s)\n", log_id(preAdder), log_id(preAdder->type));
log(" preadder %s (%s)\n", preAdder, preAdder->type.unescape());
bool A_SIGNED = preAdder->getParam(ID::A_SIGNED).as_bool();
bool D_SIGNED = preAdder->getParam(ID::B_SIGNED).as_bool();
if (st.sigA == preAdder->getPort(ID::B))
@ -312,7 +312,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
pm.autoremove(preAdder);
}
if (st.postAdd) {
log(" postadder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
log(" postadder %s (%s)\n", st.postAdd, st.postAdd->type.unescape());
SigSpec &opmode = cell->connections_.at(ID(OPMODE));
if (st.postAddMux) {
@ -338,7 +338,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
pm.autoremove(st.postAdd);
}
if (st.overflow) {
log(" overflow %s (%s)\n", log_id(st.overflow), log_id(st.overflow->type));
log(" overflow %s (%s)\n", st.overflow, st.overflow->type.unescape());
cell->setParam(ID(USE_PATTERN_DETECT), Const("PATDET"));
cell->setParam(ID(SEL_PATTERN), Const("PATTERN"));
cell->setParam(ID(SEL_MASK), Const("MASK"));
@ -456,28 +456,28 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), "posedge");
if (st.ffA2) {
log(" ffA2:%s", log_id(st.ffA2));
log(" ffA2:%s", st.ffA2);
if (st.ffA1)
log(" ffA1:%s", log_id(st.ffA1));
log(" ffA1:%s", st.ffA1);
}
if (st.ffAD)
log(" ffAD:%s", log_id(st.ffAD));
log(" ffAD:%s", st.ffAD);
if (st.ffB2) {
log(" ffB2:%s", log_id(st.ffB2));
log(" ffB2:%s", st.ffB2);
if (st.ffB1)
log(" ffB1:%s", log_id(st.ffB1));
log(" ffB1:%s", st.ffB1);
}
if (st.ffD)
log(" ffD:%s", log_id(st.ffD));
log(" ffD:%s", st.ffD);
if (st.ffM)
log(" ffM:%s", log_id(st.ffM));
log(" ffM:%s", st.ffM);
if (st.ffP)
log(" ffP:%s", log_id(st.ffP));
log(" ffP:%s", st.ffP);
}
log("\n");
@ -493,7 +493,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
{
auto &st = pm.st_xilinx_dsp48a_pack;
log("Analysing %s.%s for Xilinx DSP48A/DSP48A1 packing.\n", log_id(pm.module), log_id(st.dsp));
log("Analysing %s.%s for Xilinx DSP48A/DSP48A1 packing.\n", pm.module, st.dsp);
log_debug("preAdd: %s\n", log_id(st.preAdd, "--"));
log_debug("ffA1: %s\n", log_id(st.ffA1, "--"));
@ -511,7 +511,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
SigSpec &opmode = cell->connections_.at(ID(OPMODE));
if (st.preAdd) {
log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
log(" preadder %s (%s)\n", st.preAdd, st.preAdd->type.unescape());
bool D_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
st.sigB.extend_u0(18, B_SIGNED);
@ -529,7 +529,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
pm.autoremove(st.preAdd);
}
if (st.postAdd) {
log(" postadder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
log(" postadder %s (%s)\n", st.postAdd, st.postAdd->type.unescape());
if (st.postAddMux) {
log_assert(st.ffP);
@ -639,23 +639,23 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), "posedge");
if (st.ffA0)
log(" ffA0:%s", log_id(st.ffA0));
log(" ffA0:%s", st.ffA0);
if (st.ffA1)
log(" ffA1:%s", log_id(st.ffA1));
log(" ffA1:%s", st.ffA1);
if (st.ffB0)
log(" ffB0:%s", log_id(st.ffB0));
log(" ffB0:%s", st.ffB0);
if (st.ffB1)
log(" ffB1:%s", log_id(st.ffB1));
log(" ffB1:%s", st.ffB1);
if (st.ffD)
log(" ffD:%s", log_id(st.ffD));
log(" ffD:%s", st.ffD);
if (st.ffM)
log(" ffM:%s", log_id(st.ffM));
log(" ffM:%s", st.ffM);
if (st.ffP)
log(" ffP:%s", log_id(st.ffP));
log(" ffP:%s", st.ffP);
}
log("\n");
@ -671,7 +671,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
{
auto &st = pm.st_xilinx_dsp_packC;
log_debug("Analysing %s.%s for Xilinx DSP packing (CREG).\n", log_id(pm.module), log_id(st.dsp));
log_debug("Analysing %s.%s for Xilinx DSP packing (CREG).\n", pm.module, st.dsp);
log_debug("ffC: %s\n", log_id(st.ffC, "--"));
Cell *cell = st.dsp;
@ -724,7 +724,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), "posedge");
if (st.ffC)
log(" ffC:%s", log_id(st.ffC));
log(" ffC:%s", st.ffC);
log("\n");
}

12
techlibs/xilinx/xilinx_srl.cc
View file

@ -30,11 +30,11 @@ void run_fixed(xilinx_srl_pm &pm)
{
auto &st = pm.st_fixed;
auto &ud = pm.ud_fixed;
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), st.first->type.unescape());
SigSpec initval;
for (auto cell : ud.longest_chain) {
log_debug(" %s\n", log_id(cell));
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
SigBit Q = cell->getPort(ID::Q);
log_assert(Q.wire);
@ -100,7 +100,7 @@ void run_fixed(xilinx_srl_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
log(" -> %s (%s)\n", c, c->type.unescape());
}
void run_variable(xilinx_srl_pm &pm)
@ -108,13 +108,13 @@ void run_variable(xilinx_srl_pm &pm)
auto &st = pm.st_variable;
auto &ud = pm.ud_variable;
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type));
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), st.first->type.unescape());
SigSpec initval;
for (const auto &i : ud.chain) {
auto cell = i.first;
auto slice = i.second;
log_debug(" %s\n", log_id(cell));
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
SigBit Q = cell->getPort(ID::Q)[slice];
log_assert(Q.wire);
@ -181,7 +181,7 @@ void run_variable(xilinx_srl_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
log(" -> %s (%s)\n", c, c->type.unescape());
}
struct XilinxSrlPass : public Pass {