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Refactored uses of log_id()

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Codexplorer 2026-05-08 00:01:43 -07:00
parent 89d83a3410
commit e41b969da2
186 changed files with 1219 additions and 1220 deletions
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20
techlibs/ice40/ice40_dsp.cc
View file

@ -29,7 +29,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
{
auto &st = pm.st_ice40_dsp;
log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
log("Checking %s.%s for iCE40 DSP inference.\n", pm.module, st.mul);
log_debug("ffA: %s\n", log_id(st.ffA, "--"));
log_debug("ffB: %s\n", log_id(st.ffB, "--"));
@ -64,7 +64,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
Cell *cell = st.mul;
if (cell->type == ID($mul)) {
log(" replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
log(" replacing %s with SB_MAC16 cell.\n", st.mul->type.unescape());
cell = pm.module->addCell(NEW_ID, ID(SB_MAC16));
pm.module->swap_names(cell, st.mul);
@ -135,22 +135,22 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), st.clock_pol ? "posedge" : "negedge");
if (st.ffA)
log(" ffA:%s", log_id(st.ffA));
log(" ffA:%s", st.ffA);
if (st.ffB)
log(" ffB:%s", log_id(st.ffB));
log(" ffB:%s", st.ffB);
if (st.ffCD)
log(" ffCD:%s", log_id(st.ffCD));
log(" ffCD:%s", st.ffCD);
if (st.ffFJKG)
log(" ffFJKG:%s", log_id(st.ffFJKG));
log(" ffFJKG:%s", st.ffFJKG);
if (st.ffH)
log(" ffH:%s", log_id(st.ffH));
log(" ffH:%s", st.ffH);
if (st.ffO)
log(" ffO:%s", log_id(st.ffO));
log(" ffO:%s", st.ffO);
log("\n");
}
@ -196,9 +196,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
if (st.add) {
accum = (st.ffO && st.add->getPort(st.addAB == ID::A ? ID::B : ID::A) == st.sigO);
if (accum)
log(" accumulator %s (%s)\n", log_id(st.add), log_id(st.add->type));
log(" accumulator %s (%s)\n", st.add, st.add->type.unescape());
else
log(" adder %s (%s)\n", log_id(st.add), log_id(st.add->type));
log(" adder %s (%s)\n", st.add, st.add->type.unescape());
cell->setPort(ID(ADDSUBTOP), st.add->type == ID($add) ? State::S0 : State::S1);
cell->setPort(ID(ADDSUBBOT), st.add->type == ID($add) ? State::S0 : State::S1);
} else {

6
techlibs/ice40/ice40_opt.cc
View file

@ -83,7 +83,7 @@ static void run_ice40_opts(Module *module)
module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
module, cell, log_signal(replacement_output));
module->remove(cell);
}
continue;
@ -137,7 +137,7 @@ static void run_ice40_opts(Module *module)
module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
module, cell, log_signal(replacement_output));
cell->type = ID($lut);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) });
@ -175,7 +175,7 @@ static void run_ice40_opts(Module *module)
remap_lut:
module->design->scratchpad_set_bool("opt.did_something", true);
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", log_id(module), log_id(cell));
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", module, cell);
cell->type = ID($lut);
cell->setParam(ID::WIDTH, 4);