mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-16 07:05:37 +00:00
Code Activity

Refactored uses of log_id()

Browse source
This commit is contained in:
Codexplorer 2026-05-08 00:01:43 -07:00
parent 89d83a3410
commit e41b969da2
186 changed files with 1219 additions and 1220 deletions
Download patch file Download diff file Expand all files Collapse all files

4
techlibs/anlogic/anlogic_fixcarry.cc
View file

@ -69,7 +69,7 @@ static void fix_carry_chain(Module *module)
continue;
adders_to_fix_cells.push_back(cell);
log("Found %s cell named %s with invalid 'c' signal.\n", log_id(cell->type), log_id(cell));
log("Found %s cell named %s with invalid 'c' signal.\n", cell->type.unescape(), cell);
}
}
@ -78,7 +78,7 @@ static void fix_carry_chain(Module *module)
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescape(), cell);
Cell *c = module->addCell(NEW_ID, ID(AL_MAP_ADDER));
SigBit new_bit = module->addWire(NEW_ID);
SigBit dummy_bit = module->addWire(NEW_ID);

4
techlibs/efinix/efinix_fixcarry.cc
View file

@ -65,7 +65,7 @@ static void fix_carry_chain(Module *module)
continue;
adders_to_fix_cells.push_back(cell);
log("Found %s cell named %s with invalid CI signal.\n", log_id(cell->type), log_id(cell));
log("Found %s cell named %s with invalid CI signal.\n", cell->type.unescape(), cell);
}
}
@ -74,7 +74,7 @@ static void fix_carry_chain(Module *module)
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI));
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescape(), cell);
Cell *c = module->addCell(NEW_ID, ID(EFX_ADD));
SigBit new_bit = module->addWire(NEW_ID);
c->setParam(ID(I0_POLARITY), State::S1);

2
techlibs/greenpak4/greenpak4_dffinv.cc
View file

@ -86,7 +86,7 @@ void invert_gp_dff(Cell *cell, bool invert_input)
cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
log("Merged %s inverter into cell %s.%s: %s -> %s\n", invert_input ? "input" : "output",
log_id(cell->module), log_id(cell), cell_type.c_str()+1, log_id(cell->type));
cell->module, cell, cell_type.c_str()+1, cell->type.unescape());
}
struct Greenpak4DffInvPass : public Pass {

20
techlibs/ice40/ice40_dsp.cc
View file

@ -29,7 +29,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
{
auto &st = pm.st_ice40_dsp;
log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
log("Checking %s.%s for iCE40 DSP inference.\n", pm.module, st.mul);
log_debug("ffA: %s\n", log_id(st.ffA, "--"));
log_debug("ffB: %s\n", log_id(st.ffB, "--"));
@ -64,7 +64,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
Cell *cell = st.mul;
if (cell->type == ID($mul)) {
log(" replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
log(" replacing %s with SB_MAC16 cell.\n", st.mul->type.unescape());
cell = pm.module->addCell(NEW_ID, ID(SB_MAC16));
pm.module->swap_names(cell, st.mul);
@ -135,22 +135,22 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), st.clock_pol ? "posedge" : "negedge");
if (st.ffA)
log(" ffA:%s", log_id(st.ffA));
log(" ffA:%s", st.ffA);
if (st.ffB)
log(" ffB:%s", log_id(st.ffB));
log(" ffB:%s", st.ffB);
if (st.ffCD)
log(" ffCD:%s", log_id(st.ffCD));
log(" ffCD:%s", st.ffCD);
if (st.ffFJKG)
log(" ffFJKG:%s", log_id(st.ffFJKG));
log(" ffFJKG:%s", st.ffFJKG);
if (st.ffH)
log(" ffH:%s", log_id(st.ffH));
log(" ffH:%s", st.ffH);
if (st.ffO)
log(" ffO:%s", log_id(st.ffO));
log(" ffO:%s", st.ffO);
log("\n");
}
@ -196,9 +196,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
if (st.add) {
accum = (st.ffO && st.add->getPort(st.addAB == ID::A ? ID::B : ID::A) == st.sigO);
if (accum)
log(" accumulator %s (%s)\n", log_id(st.add), log_id(st.add->type));
log(" accumulator %s (%s)\n", st.add, st.add->type.unescape());
else
log(" adder %s (%s)\n", log_id(st.add), log_id(st.add->type));
log(" adder %s (%s)\n", st.add, st.add->type.unescape());
cell->setPort(ID(ADDSUBTOP), st.add->type == ID($add) ? State::S0 : State::S1);
cell->setPort(ID(ADDSUBBOT), st.add->type == ID($add) ? State::S0 : State::S1);
} else {

6
techlibs/ice40/ice40_opt.cc
View file

@ -83,7 +83,7 @@ static void run_ice40_opts(Module *module)
module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
module, cell, log_signal(replacement_output));
module->remove(cell);
}
continue;
@ -137,7 +137,7 @@ static void run_ice40_opts(Module *module)
module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
module, cell, log_signal(replacement_output));
cell->type = ID($lut);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) });
@ -175,7 +175,7 @@ static void run_ice40_opts(Module *module)
remap_lut:
module->design->scratchpad_set_bool("opt.did_something", true);
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", log_id(module), log_id(cell));
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", module, cell);
cell->type = ID($lut);
cell->setParam(ID::WIDTH, 4);

8
techlibs/lattice/lattice_gsr.cc
View file

@ -57,7 +57,7 @@ struct LatticeGsrPass : public Pass {
for (auto module : design->selected_modules())
{
log("Handling GSR in %s.\n", log_id(module));
log("Handling GSR in %s.\n", module);
SigMap sigmap(module);
@ -69,11 +69,11 @@ struct LatticeGsrPass : public Pass {
if (cell->type != ID(GSR) && cell->type != ID(SGSR))
continue;
if (found_gsr)
log_error("Found more than one GSR or SGSR cell in module %s.\n", log_id(module));
log_error("Found more than one GSR or SGSR cell in module %s.\n", module);
found_gsr = true;
SigSpec sig_gsr = cell->getPort(ID(GSR));
if (GetSize(sig_gsr) < 1)
log_error("GSR cell %s has disconnected GSR input.\n", log_id(cell));
log_error("GSR cell %s has disconnected GSR input.\n", cell);
gsr = sigmap(sig_gsr[0]);
}
@ -97,7 +97,7 @@ struct LatticeGsrPass : public Pass {
// For finding active low FF inputs
pool<SigBit> inverted_gsr;
log_debug("GSR net in module %s is %s.\n", log_id(module), log_signal(gsr));
log_debug("GSR net in module %s is %s.\n", module, log_signal(gsr));
for (auto cell : module->selected_cells())
{
if (cell->type != ID($_NOT_))

4
techlibs/microchip/microchip_dffopt.cc
View file

@ -121,7 +121,7 @@ struct MicrochipDffOptPass : public Pass {
extra_args(args, argidx, design);
for (auto module : design->selected_modules()) {
log("Optimizing FFs in %s.\n", log_id(module));
log("Optimizing FFs in %s.\n", module);
SigMap sigmap(module);
dict<SigBit, pair<LutData, Cell *>> bit_to_lut;
@ -294,7 +294,7 @@ struct MicrochipDffOptPass : public Pass {
ports += " + S";
if (worthy_post_ce)
ports += " + CE";
log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, log_id(cell), log_id(sig_Q.wire),
log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, cell, sig_Q.wire,
GetSize(lut_d.second), GetSize(final_lut.second));
// Okay, we're doing it. Unmap ports.

18
techlibs/microchip/microchip_dsp.cc
View file

@ -31,13 +31,13 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
{
auto &st = pm.st_microchip_dsp_pack;
log("Analysing %s.%s for Microchip MACC_PA packing.\n", log_id(pm.module), log_id(st.dsp));
log("Analysing %s.%s for Microchip MACC_PA packing.\n", pm.module, st.dsp);
Cell *cell = st.dsp;
// pack pre-adder
if (st.preAdderStatic) {
SigSpec &pasub = cell->connections_.at(ID(PASUB));
log(" static PASUB preadder %s (%s)\n", log_id(st.preAdderStatic), log_id(st.preAdderStatic->type));
log(" static PASUB preadder %s (%s)\n", st.preAdderStatic, st.preAdderStatic->type.unescape());
bool D_SIGNED = st.preAdderStatic->getParam(ID::B_SIGNED).as_bool();
bool B_SIGNED = st.preAdderStatic->getParam(ID::A_SIGNED).as_bool();
st.sigB.extend_u0(18, B_SIGNED);
@ -60,7 +60,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
}
// pack post-adder
if (st.postAdderStatic) {
log(" postadder %s (%s)\n", log_id(st.postAdderStatic), log_id(st.postAdderStatic->type));
log(" postadder %s (%s)\n", st.postAdderStatic, st.postAdderStatic->type.unescape());
SigSpec &sub = cell->connections_.at(ID(SUB));
// Post-adder in MACC_PA also supports subtraction
// Determines the sign of the output from the multiplier.
@ -171,13 +171,13 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
log(" clock: %s (%s)\n", log_signal(st.clock), "posedge");
if (st.ffA)
log(" \t ffA:%s\n", log_id(st.ffA));
log(" \t ffA:%s\n", st.ffA);
if (st.ffB)
log(" \t ffB:%s\n", log_id(st.ffB));
log(" \t ffB:%s\n", st.ffB);
if (st.ffD)
log(" \t ffD:%s\n", log_id(st.ffD));
log(" \t ffD:%s\n", st.ffD);
if (st.ffP)
log(" \t ffP:%s\n", log_id(st.ffP));
log(" \t ffP:%s\n", st.ffP);
}
log("\n");
@ -194,7 +194,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
{
auto &st = pm.st_microchip_dsp_packC;
log_debug("Analysing %s.%s for Microchip DSP packing (REG_C).\n", log_id(pm.module), log_id(st.dsp));
log_debug("Analysing %s.%s for Microchip DSP packing (REG_C).\n", pm.module, st.dsp);
log_debug("ffC: %s\n", log_id(st.ffC, "--"));
Cell *cell = st.dsp;
@ -264,7 +264,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), "posedge");
if (st.ffC)
log(" ffC:%s", log_id(st.ffC));
log(" ffC:%s", st.ffC);
log("\n");
}

6
techlibs/quicklogic/ql_bram_merge.cc
View file

@ -128,7 +128,7 @@ struct QlBramMergeWorker {
// Create the new cell
RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type);
log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name));
log_debug("Merging split BRAM cells %s and %s -> %s\n", bram1->name.unescape(), bram2->name.unescape(), merged->name.unescape());
for (auto &it : param_map(false))
{
@ -146,14 +146,14 @@ struct QlBramMergeWorker {
if (bram1->hasPort(it.first))
merged->setPort(it.second, bram1->getPort(it.first));
else
log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name));
log_error("Can't find port %s on cell %s!\n", it.first.unescape(), bram1->name.unescape());
}
for (auto &it : port_map(true))
{
if (bram2->hasPort(it.first))
merged->setPort(it.second, bram2->getPort(it.first));
else
log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name));
log_error("Can't find port %s on cell %s!\n", it.first.unescape(), bram2->name.unescape());
}
merged->attributes = bram1->attributes;
for (auto attr: bram2->attributes)

2
techlibs/quicklogic/ql_bram_types.cc
View file

@ -155,7 +155,7 @@ struct QlBramTypesPass : public Pass {
}
cell->type = RTLIL::escape_id(type);
log_debug("Changed type of memory cell %s to %s\n", log_id(cell->name), log_id(cell->type));
log_debug("Changed type of memory cell %s to %s\n", cell->name.unescape(), cell->type.unescape());
}
}

6
techlibs/quicklogic/ql_dsp_io_regs.cc
View file

@ -83,19 +83,19 @@ struct QlDspIORegs : public Pass {
for (auto cfg_port : {ID(register_inputs), ID(output_select)})
if (!cell->hasPort(cfg_port) || !sigmap(cell->getPort(cfg_port)).is_fully_const())
log_error("Missing or non-constant '%s' port on DSP cell %s\n",
log_id(cfg_port), log_id(cell));
cfg_port, cell);
int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int();
int out_sel_i = sigmap(cell->getPort(ID(output_select))).as_int();
// Get the feedback port
if (!cell->hasPort(ID(feedback)))
log_error("Missing 'feedback' port on %s", log_id(cell));
log_error("Missing 'feedback' port on %s", cell);
SigSpec feedback = sigmap(cell->getPort(ID(feedback)));
// Check the top two bits on 'feedback' to be constant zero.
// That's what we are expecting from inference.
if (feedback.extract(1, 2) != SigSpec(0, 2))
log_error("Unexpected feedback configuration on %s\n", log_id(cell));
log_error("Unexpected feedback configuration on %s\n", cell);
// Build new type name
std::string new_type = "\\QL_DSP2_MULT";

4
techlibs/quicklogic/ql_dsp_macc.cc
View file

@ -73,11 +73,11 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
}
type = RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports");
log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, log_id(type));
log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, type);
for (auto cell : {st.mul, st.add, st.mux, st.ff})
if (cell)
log(" %s (%s)\n", log_id(cell), log_id(cell->type));
log(" %s (%s)\n", cell, cell->type.unescape());
// Add the DSP cell
RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type);

6
techlibs/quicklogic/ql_dsp_simd.cc
View file

@ -150,13 +150,13 @@ struct QlDspSimdPass : public Pass {
// Create the new cell
Cell *simd = module->addCell(NEW_ID, m_SimdDspType);
log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", log_id(dsp_a), log_id(dsp_a->type),
log_id(dsp_b), log_id(dsp_b->type), log_id(simd), log_id(simd->type));
log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", dsp_a, dsp_a->type.unescape(),
dsp_b, dsp_b->type.unescape(), simd, simd->type.unescape());
// Check if the target cell is known (important to know
// its port widths)
if (!simd->known())
log_error(" The target cell type '%s' is not known!", log_id(simd));
log_error(" The target cell type '%s' is not known!", simd);
// Connect common ports
for (const auto &it : m_DspCfgPorts)

4
techlibs/xilinx/xilinx_dffopt.cc
View file

@ -131,7 +131,7 @@ struct XilinxDffOptPass : public Pass {
for (auto module : design->selected_modules())
{
log("Optimizing FFs in %s.\n", log_id(module));
log("Optimizing FFs in %s.\n", module);
SigMap sigmap(module);
dict<SigBit, pair<LutData, Cell *>> bit_to_lut;
@ -305,7 +305,7 @@ unmap:
if (worthy_post_r) ports += " + R";
if (worthy_post_s) ports += " + S";
if (worthy_post_ce) ports += " + CE";
log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, cell, sig_Q.wire, GetSize(lut_d.second), GetSize(final_lut.second));
// Okay, we're doing it. Unmap ports.
if (worthy_post_r) {

52
techlibs/xilinx/xilinx_dsp.cc
View file

@ -140,7 +140,7 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
}
}
log("Analysing %s.%s for Xilinx DSP SIMD12 packing.\n", log_id(module), log_id(lane1));
log("Analysing %s.%s for Xilinx DSP SIMD12 packing.\n", module, lane1);
Cell *cell = addDsp(module);
cell->setParam(ID(USE_SIMD), Const("FOUR12"));
@ -221,7 +221,7 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
Cell *lane2 = simd24.front();
simd24.pop_front();
log("Analysing %s.%s for Xilinx DSP SIMD24 packing.\n", log_id(module), log_id(lane1));
log("Analysing %s.%s for Xilinx DSP SIMD24 packing.\n", module, lane1);
Cell *cell = addDsp(module);
cell->setParam(ID(USE_SIMD), Const("TWO24"));
@ -260,7 +260,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
{
auto &st = pm.st_xilinx_dsp_pack;
log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
log("Analysing %s.%s for Xilinx DSP packing.\n", pm.module, st.dsp);
log_debug("preAdd: %s\n", log_id(st.preAdd, "--"));
log_debug("preSub: %s\n", log_id(st.preSub, "--"));
@ -282,7 +282,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (st.preAdd || st.preSub) {
Cell* preAdder = st.preAdd ? st.preAdd : st.preSub;
log(" preadder %s (%s)\n", log_id(preAdder), log_id(preAdder->type));
log(" preadder %s (%s)\n", preAdder, preAdder->type.unescape());
bool A_SIGNED = preAdder->getParam(ID::A_SIGNED).as_bool();
bool D_SIGNED = preAdder->getParam(ID::B_SIGNED).as_bool();
if (st.sigA == preAdder->getPort(ID::B))
@ -312,7 +312,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
pm.autoremove(preAdder);
}
if (st.postAdd) {
log(" postadder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
log(" postadder %s (%s)\n", st.postAdd, st.postAdd->type.unescape());
SigSpec &opmode = cell->connections_.at(ID(OPMODE));
if (st.postAddMux) {
@ -338,7 +338,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
pm.autoremove(st.postAdd);
}
if (st.overflow) {
log(" overflow %s (%s)\n", log_id(st.overflow), log_id(st.overflow->type));
log(" overflow %s (%s)\n", st.overflow, st.overflow->type.unescape());
cell->setParam(ID(USE_PATTERN_DETECT), Const("PATDET"));
cell->setParam(ID(SEL_PATTERN), Const("PATTERN"));
cell->setParam(ID(SEL_MASK), Const("MASK"));
@ -456,28 +456,28 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), "posedge");
if (st.ffA2) {
log(" ffA2:%s", log_id(st.ffA2));
log(" ffA2:%s", st.ffA2);
if (st.ffA1)
log(" ffA1:%s", log_id(st.ffA1));
log(" ffA1:%s", st.ffA1);
}
if (st.ffAD)
log(" ffAD:%s", log_id(st.ffAD));
log(" ffAD:%s", st.ffAD);
if (st.ffB2) {
log(" ffB2:%s", log_id(st.ffB2));
log(" ffB2:%s", st.ffB2);
if (st.ffB1)
log(" ffB1:%s", log_id(st.ffB1));
log(" ffB1:%s", st.ffB1);
}
if (st.ffD)
log(" ffD:%s", log_id(st.ffD));
log(" ffD:%s", st.ffD);
if (st.ffM)
log(" ffM:%s", log_id(st.ffM));
log(" ffM:%s", st.ffM);
if (st.ffP)
log(" ffP:%s", log_id(st.ffP));
log(" ffP:%s", st.ffP);
}
log("\n");
@ -493,7 +493,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
{
auto &st = pm.st_xilinx_dsp48a_pack;
log("Analysing %s.%s for Xilinx DSP48A/DSP48A1 packing.\n", log_id(pm.module), log_id(st.dsp));
log("Analysing %s.%s for Xilinx DSP48A/DSP48A1 packing.\n", pm.module, st.dsp);
log_debug("preAdd: %s\n", log_id(st.preAdd, "--"));
log_debug("ffA1: %s\n", log_id(st.ffA1, "--"));
@ -511,7 +511,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
SigSpec &opmode = cell->connections_.at(ID(OPMODE));
if (st.preAdd) {
log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
log(" preadder %s (%s)\n", st.preAdd, st.preAdd->type.unescape());
bool D_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
st.sigB.extend_u0(18, B_SIGNED);
@ -529,7 +529,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
pm.autoremove(st.preAdd);
}
if (st.postAdd) {
log(" postadder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
log(" postadder %s (%s)\n", st.postAdd, st.postAdd->type.unescape());
if (st.postAddMux) {
log_assert(st.ffP);
@ -639,23 +639,23 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), "posedge");
if (st.ffA0)
log(" ffA0:%s", log_id(st.ffA0));
log(" ffA0:%s", st.ffA0);
if (st.ffA1)
log(" ffA1:%s", log_id(st.ffA1));
log(" ffA1:%s", st.ffA1);
if (st.ffB0)
log(" ffB0:%s", log_id(st.ffB0));
log(" ffB0:%s", st.ffB0);
if (st.ffB1)
log(" ffB1:%s", log_id(st.ffB1));
log(" ffB1:%s", st.ffB1);
if (st.ffD)
log(" ffD:%s", log_id(st.ffD));
log(" ffD:%s", st.ffD);
if (st.ffM)
log(" ffM:%s", log_id(st.ffM));
log(" ffM:%s", st.ffM);
if (st.ffP)
log(" ffP:%s", log_id(st.ffP));
log(" ffP:%s", st.ffP);
}
log("\n");
@ -671,7 +671,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
{
auto &st = pm.st_xilinx_dsp_packC;
log_debug("Analysing %s.%s for Xilinx DSP packing (CREG).\n", log_id(pm.module), log_id(st.dsp));
log_debug("Analysing %s.%s for Xilinx DSP packing (CREG).\n", pm.module, st.dsp);
log_debug("ffC: %s\n", log_id(st.ffC, "--"));
Cell *cell = st.dsp;
@ -724,7 +724,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
log(" clock: %s (%s)", log_signal(st.clock), "posedge");
if (st.ffC)
log(" ffC:%s", log_id(st.ffC));
log(" ffC:%s", st.ffC);
log("\n");
}

12
techlibs/xilinx/xilinx_srl.cc
View file

@ -30,11 +30,11 @@ void run_fixed(xilinx_srl_pm &pm)
{
auto &st = pm.st_fixed;
auto &ud = pm.ud_fixed;
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), st.first->type.unescape());
SigSpec initval;
for (auto cell : ud.longest_chain) {
log_debug(" %s\n", log_id(cell));
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
SigBit Q = cell->getPort(ID::Q);
log_assert(Q.wire);
@ -100,7 +100,7 @@ void run_fixed(xilinx_srl_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
log(" -> %s (%s)\n", c, c->type.unescape());
}
void run_variable(xilinx_srl_pm &pm)
@ -108,13 +108,13 @@ void run_variable(xilinx_srl_pm &pm)
auto &st = pm.st_variable;
auto &ud = pm.ud_variable;
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type));
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), st.first->type.unescape());
SigSpec initval;
for (const auto &i : ud.chain) {
auto cell = i.first;
auto slice = i.second;
log_debug(" %s\n", log_id(cell));
log_debug(" %s\n", cell);
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
SigBit Q = cell->getPort(ID::Q)[slice];
log_assert(Q.wire);
@ -181,7 +181,7 @@ void run_variable(xilinx_srl_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
log(" -> %s (%s)\n", c, c->type.unescape());
}
struct XilinxSrlPass : public Pass {