mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-18 16:09:36 +00:00
Code Activity

Refactored uses of log_id()

Browse source
This commit is contained in:
Codexplorer 2026-05-08 00:01:43 -07:00
parent 89d83a3410
commit e41b969da2
186 changed files with 1219 additions and 1220 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/techmap/abc.cc
View file

@ -2427,7 +2427,7 @@ struct AbcPass : public Pass {
for (auto mod : design->selected_modules())
{
if (mod->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", log_id(mod));
log("Skipping module %s as it contains processes.\n", mod);
continue;
}

8
passes/techmap/abc9.cc
View file

@ -386,7 +386,7 @@ struct Abc9Pass : public ScriptPass
for (auto mod : selected_modules) {
if (mod->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", log_id(mod));
log("Skipping module %s as it contains processes.\n", mod);
continue;
}
@ -395,7 +395,7 @@ struct Abc9Pass : public ScriptPass
// this check does nothing because the above line adds the whole module to the selection
if (!active_design->selected_whole_module(mod))
log_error("Can't handle partially selected module %s!\n", log_id(mod));
log_error("Can't handle partially selected module %s!\n", mod);
std::string tempdir_name;
if (cleanup)
@ -416,7 +416,7 @@ struct Abc9Pass : public ScriptPass
log("Extracted %d AND gates and %d wires from module `%s' to a netlist network with %d inputs and %d outputs.\n",
active_design->scratchpad_get_int("write_xaiger.num_ands"),
active_design->scratchpad_get_int("write_xaiger.num_wires"),
log_id(mod),
mod,
active_design->scratchpad_get_int("write_xaiger.num_inputs"),
num_outputs);
if (num_outputs) {
@ -429,7 +429,7 @@ struct Abc9Pass : public ScriptPass
else
abc9_exe_cmd += stringf(" -box %s", box_file);
run_nocheck(abc9_exe_cmd);
run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name, tempdir_name));
run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", mod, tempdir_name, tempdir_name));
run_nocheck(stringf("abc9_ops -reintegrate %s", dff_mode ? "-dff" : ""));
}
else

78
passes/techmap/abc9_ops.cc
View file

@ -48,7 +48,7 @@ void check(RTLIL::Design *design, bool dff_mode)
auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
if (!r.second)
log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
log_id(m), id, log_id(r.first->second));
m, id, r.first->second.unescape());
}
// Make carry in the last PI, and carry out the last PO
@ -60,21 +60,21 @@ void check(RTLIL::Design *design, bool dff_mode)
if (w->get_bool_attribute(ID::abc9_carry)) {
if (w->port_input) {
if (carry_in != IdString())
log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", log_id(m));
log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", m);
carry_in = port_name;
}
if (w->port_output) {
if (carry_out != IdString())
log_error("Module '%s' contains more than one (* abc9_carry *) output port.\n", log_id(m));
log_error("Module '%s' contains more than one (* abc9_carry *) output port.\n", m);
carry_out = port_name;
}
}
}
if (carry_in != IdString() && carry_out == IdString())
log_error("Module '%s' contains an (* abc9_carry *) input port but no output port.\n", log_id(m));
log_error("Module '%s' contains an (* abc9_carry *) input port but no output port.\n", m);
if (carry_in == IdString() && carry_out != IdString())
log_error("Module '%s' contains an (* abc9_carry *) output port but no input port.\n", log_id(m));
log_error("Module '%s' contains an (* abc9_carry *) output port but no input port.\n", m);
if (flop) {
int num_outputs = 0;
@ -83,7 +83,7 @@ void check(RTLIL::Design *design, bool dff_mode)
if (wire->port_output) num_outputs++;
}
if (num_outputs != 1)
log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", m, num_outputs);
}
}
@ -121,7 +121,7 @@ void check(RTLIL::Design *design, bool dff_mode)
if (!derived_module->get_bool_attribute(ID::abc9_flop))
continue;
if (derived_module->get_blackbox_attribute(true /* ignore_wb */))
log_error("Module '%s' with (* abc9_flop *) is a blackbox.\n", log_id(derived_type));
log_error("Module '%s' with (* abc9_flop *) is a blackbox.\n", derived_type.unescape());
if (derived_module->has_processes())
Pass::call_on_module(design, derived_module, "proc -noopt");
@ -130,20 +130,20 @@ void check(RTLIL::Design *design, bool dff_mode)
for (auto derived_cell : derived_module->cells()) {
if (derived_cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) {
if (found)
log_error("Whitebox '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", log_id(derived_module));
log_error("Whitebox '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", derived_module);
found = true;
SigBit Q = derived_cell->getPort(ID::Q);
log_assert(GetSize(Q.wire) == 1);
if (!Q.wire->port_output)
log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell where its 'Q' port does not drive a module output.\n", log_id(derived_module), log_id(derived_cell->type));
log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell where its 'Q' port does not drive a module output.\n", derived_module, derived_cell->type.unescape());
Const init = Q.wire->attributes.at(ID::init, State::Sx);
log_assert(GetSize(init) == 1);
}
else if (unsupported.count(derived_cell->type))
log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell, which is not supported for sequential synthesis.\n", log_id(derived_module), log_id(derived_cell->type));
log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell, which is not supported for sequential synthesis.\n", derived_module, derived_cell->type.unescape());
}
}
}
@ -217,7 +217,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
// Block sequential synthesis on cells with (* init *) != 1'b0
// because ABC9 doesn't support them
if (init != State::S0) {
log_warning("Whitebox '%s' with (* abc9_flop *) contains a %s cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.\n", log_id(derived_module), log_id(derived_cell->type));
log_warning("Whitebox '%s' with (* abc9_flop *) contains a %s cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.\n", derived_module, derived_cell->type.unescape());
derived_module->set_bool_attribute(ID::abc9_flop, false);
}
break;
@ -474,7 +474,7 @@ void prep_dff(RTLIL::Design *design)
// be instantiating the derived module which will have had any parameters constant-propagated.
// This task is expected to be performed by `abc9_ops -prep_hier`, but it looks like it failed to do so for this design.
// Please file a bug report!
log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_flop *)\n", log_id(cell->name), log_id(cell->type));
log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_flop *)\n", cell->name.unescape(), cell->type.unescape());
}
modules_sel.select(inst_module);
}
@ -621,7 +621,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
std::vector<Cell*> cells;
for (auto module : design->selected_modules()) {
if (module->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", log_id(module));
log("Skipping module %s as it contains processes.\n", module);
continue;
}
@ -669,7 +669,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
auto port_wire = inst_module->wire(i.first.name);
if (!port_wire)
log_error("Port %s in cell %s (type %s) from module %s does not actually exist",
log_id(i.first.name), log_id(cell), log_id(cell->type), log_id(module));
i.first.name.unescape(), cell, cell->type.unescape(), module);
log_assert(port_wire->port_input);
auto d = i.second.first;
@ -688,7 +688,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
if (ys_debug(1)) {
static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
if (seen.emplace(cell->type, i.first).second) log("%s.%s[%d] abc9_required = %d\n",
log_id(cell->type), log_id(i.first.name), offset, d);
cell->type.unescape(), i.first.name.unescape(), offset, d);
}
#endif
auto r = box_cache.insert(d);
@ -848,7 +848,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
for (auto cell_name : it) {
auto cell = module->cell(cell_name);
log_assert(cell);
log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute());
log("\t%s (%s @ %s)\n", cell, cell->type.unescape(), cell->get_src_attribute());
}
}
}
@ -882,7 +882,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
// be instantiating the derived module which will have had any parameters constant-propagated.
// This task is expected to be performed by `abc9_ops -prep_hier`, but it looks like it failed to do so for this design.
// Please file a bug report!
log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_box *)\n", log_id(cell_name), log_id(cell->type));
log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_box *)\n", cell_name.unescape(), cell->type.unescape());
}
log_assert(box_module->get_blackbox_attribute());
@ -917,7 +917,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
}
}
else if (w->port_output)
conn = holes_module->addWire(stringf("%s.%s", cell->type, log_id(port_name)), GetSize(w));
conn = holes_module->addWire(stringf("%s.%s", cell->type, port_name.unescape()), GetSize(w));
}
}
else // box_module is a blackbox
@ -929,7 +929,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
log_assert(w);
if (!w->port_output)
continue;
Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name, log_id(port_name)), GetSize(w));
Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name, port_name.unescape()), GetSize(w));
holes_wire->port_output = true;
holes_wire->port_id = port_id++;
holes_module->ports.push_back(holes_wire->name);
@ -965,12 +965,12 @@ void prep_lut(RTLIL::Design *design, int maxlut)
if (o == TimingInfo::NameBit())
o = d;
else if (o != d)
log_error("Module '%s' with (* abc9_lut *) has more than one output.\n", log_id(module));
log_error("Module '%s' with (* abc9_lut *) has more than one output.\n", module);
delays.push_back(i.second);
}
if (GetSize(delays) == 0)
log_error("Module '%s' with (* abc9_lut *) has no specify entries.\n", log_id(module));
log_error("Module '%s' with (* abc9_lut *) has no specify entries.\n", module);
if (maxlut && GetSize(delays) > maxlut)
continue;
// ABC requires non-decreasing LUT input delays
@ -981,9 +981,9 @@ void prep_lut(RTLIL::Design *design, int maxlut)
auto r = table.emplace(K, entry);
if (!r.second) {
if (r.first->second.area != entry.area)
log_error("Modules '%s' and '%s' have conflicting (* abc9_lut *) values.\n", log_id(module), log_id(r.first->second.name));
log_error("Modules '%s' and '%s' have conflicting (* abc9_lut *) values.\n", module, r.first->second.name.unescape());
if (r.first->second.delays != entry.delays)
log_error("Modules '%s' and '%s' have conflicting specify entries.\n", log_id(module), log_id(r.first->second.name));
log_error("Modules '%s' and '%s' have conflicting specify entries.\n", module, r.first->second.name.unescape());
}
}
@ -1002,7 +1002,7 @@ void prep_lut(RTLIL::Design *design, int maxlut)
ss << std::endl;
}
for (const auto &i : table) {
ss << "# " << log_id(i.second.name) << std::endl;
ss << "# " << i.second.name.unescape() << std::endl;
ss << i.first << " " << i.second.area;
for (const auto &j : i.second.delays)
ss << " " << j;
@ -1046,7 +1046,7 @@ void prep_box(RTLIL::Design *design)
}
log_assert(num_outputs == 1);
ss << log_id(module) << " " << r.first->second.as_int();
ss << module->name.unescape() << " " << r.first->second.as_int();
log_assert(module->get_bool_attribute(ID::whitebox));
ss << " " << "1";
ss << " " << num_inputs << " " << num_outputs << std::endl;
@ -1061,13 +1061,13 @@ void prep_box(RTLIL::Design *design)
first = false;
else
ss << " ";
ss << log_id(wire);
ss << wire->name.unescape();
}
ss << std::endl;
auto &t = timing.setup_module(module).required;
if (t.empty())
log_error("Module '%s' with (* abc9_flop *) has no clk-to-q timing (and thus no connectivity) information.\n", log_id(module));
log_error("Module '%s' with (* abc9_flop *) has no clk-to-q timing (and thus no connectivity) information.\n", module);
first = true;
for (auto port_name : module->ports) {
@ -1089,8 +1089,8 @@ void prep_box(RTLIL::Design *design)
#ifndef NDEBUG
if (ys_debug(1)) {
static std::set<std::pair<IdString,IdString>> seen;
if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
log_id(port_name), it->second.first);
if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", module,
port_name.unescape(), it->second.first);
}
#endif
}
@ -1135,7 +1135,7 @@ void prep_box(RTLIL::Design *design)
outputs.emplace_back(wire, i);
}
ss << log_id(module) << " " << module->attributes.at(ID::abc9_box_id).as_int();
ss << module->name.unescape() << " " << module->attributes.at(ID::abc9_box_id).as_int();
bool has_model = module->get_bool_attribute(ID::whitebox) || !module->get_bool_attribute(ID::blackbox);
ss << " " << (has_model ? "1" : "0");
ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
@ -1148,15 +1148,15 @@ void prep_box(RTLIL::Design *design)
else
ss << " ";
if (GetSize(i.wire) == 1)
ss << log_id(i.wire);
ss << i.wire->name.unescape();
else
ss << log_id(i.wire) << "[" << i.offset << "]";
ss << i.wire->name.unescape() << "[" << i.offset << "]";
}
ss << std::endl;
auto &t = timing.setup_module(module);
if (t.comb.empty() && !outputs.empty() && !inputs.empty()) {
log_error("Module '%s' with (* abc9_box *) has no timing (and thus no connectivity) information.\n", log_id(module));
log_error("Module '%s' with (* abc9_box *) has no timing (and thus no connectivity) information.\n", module);
}
for (const auto &o : outputs) {
@ -1174,9 +1174,9 @@ void prep_box(RTLIL::Design *design)
}
ss << " # ";
if (GetSize(o.wire) == 1)
ss << log_id(o.wire);
ss << o.wire->name.unescape();
else
ss << log_id(o.wire) << "[" << o.offset << "]";
ss << o.wire->name.unescape() << "[" << o.offset << "]";
ss << std::endl;
}
ss << std::endl;
@ -1206,7 +1206,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name));
if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
log_error("ABC output file does not contain a module `%s$abc'.\n", module);
for (auto w : mapped_mod->wires()) {
auto nw = module->addWire(remap_name(w->name), GetSize(w));
@ -1387,7 +1387,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
else {
RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
if (!existing_cell)
log_error("Cannot find existing box cell with name '%s' in original design.\n", log_id(mapped_cell));
log_error("Cannot find existing box cell with name '%s' in original design.\n", mapped_cell);
if (existing_cell->type.begins_with("$paramod$__ABC9_DELAY\\DELAY=")) {
SigBit I = mapped_cell->getPort(ID(i));
@ -1924,12 +1924,12 @@ struct Abc9OpsPass : public Pass {
for (auto mod : design->selected_modules()) {
if (mod->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", log_id(mod));
log("Skipping module %s as it contains processes.\n", mod);
continue;
}
if (!design->selected_whole_module(mod))
log_error("Can't handle partially selected module %s!\n", log_id(mod));
log_error("Can't handle partially selected module %s!\n", mod);
if (!write_lut_dst.empty())
write_lut(mod, write_lut_dst);

2
passes/techmap/abc_new.cc
View file

@ -178,7 +178,7 @@ struct AbcNewPass : public ScriptPass {
tmpdir = make_temp_dir(tmpdir);
modname = mod->name.str();
exe_options = abc_exe_options;
log_header(active_design, "Mapping module '%s'.\n", log_id(mod));
log_header(active_design, "Mapping module '%s'.\n", mod);
log_push();
active_design->select(mod);
}

6
passes/techmap/aigmap.cc
View file

@ -150,21 +150,21 @@ struct AigmapPass : public Pass {
if (not_replaced_count == 0 && replaced_cells.empty())
continue;
log("Module %s: replaced %d cells with %d new cells, skipped %d cells.\n", log_id(module),
log("Module %s: replaced %d cells with %d new cells, skipped %d cells.\n", module,
GetSize(replaced_cells), GetSize(module->cells()) - orig_num_cells, not_replaced_count);
if (!stat_replaced.empty()) {
stat_replaced.sort();
log(" replaced %d cell types:\n", GetSize(stat_replaced));
for (auto &it : stat_replaced)
log("%8d %s\n", it.second, log_id(it.first));
log("%8d %s\n", it.second, it.first.unescape());
}
if (!stat_not_replaced.empty()) {
stat_not_replaced.sort();
log(" not replaced %d cell types:\n", GetSize(stat_not_replaced));
for (auto &it : stat_not_replaced)
log("%8d %s\n", it.second, log_id(it.first));
log("%8d %s\n", it.second, it.first.unescape());
}
for (auto cell : replaced_cells)

24
passes/techmap/alumacc.cc
View file

@ -156,7 +156,7 @@ struct AlumaccWorker
if (!cell->type.in(ID($pos), ID($neg), ID($add), ID($sub), ID($mul)))
continue;
log(" creating $macc model for %s (%s).\n", log_id(cell), log_id(cell->type));
log(" creating $macc model for %s (%s).\n", cell, cell->type.unescape());
maccnode_t *n = new maccnode_t;
Macc::term_t new_term;
@ -267,7 +267,7 @@ struct AlumaccWorker
if (GetSize(other_n->y) != GetSize(n->y) && macc_may_overflow(other_n->macc, GetSize(other_n->y), port.is_signed))
continue;
log(" merging $macc model for %s into %s.\n", log_id(other_n->cell), log_id(n->cell));
log(" merging $macc model for %s into %s.\n", other_n->cell, n->cell);
bool do_subtract = port.do_subtract;
for (int j = 0; j < GetSize(other_n->macc.terms); j++) {
@ -351,7 +351,7 @@ struct AlumaccWorker
if (!subtract_b && B < A && GetSize(B))
std::swap(A, B);
log(" creating $alu model for $macc %s.\n", log_id(n->cell));
log(" creating $alu model for $macc %s.\n", n->cell);
alunode = new alunode_t;
alunode->cells.push_back(n->cell);
@ -383,7 +383,7 @@ struct AlumaccWorker
macc_counter++;
log(" creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell));
log(" creating $macc cell for %s: %s\n", n->cell, cell);
cell->set_src_attribute(n->cell->get_src_attribute());
@ -412,7 +412,7 @@ struct AlumaccWorker
for (auto cell : lge_cells)
{
log(" creating $alu model for %s (%s):", log_id(cell), log_id(cell->type));
log(" creating $alu model for %s (%s):", cell, cell->type.unescape());
bool cmp_less = cell->type.in(ID($lt), ID($le));
bool cmp_equal = cell->type.in(ID($le), ID($ge));
@ -451,7 +451,7 @@ struct AlumaccWorker
sig_alu[RTLIL::SigSig(A, B)].insert(n);
log(" new $alu\n");
} else {
log(" merged with %s.\n", log_id(n->cells.front()));
log(" merged with %s.\n", n->cells.front());
}
n->cells.push_back(cell);
@ -484,7 +484,7 @@ struct AlumaccWorker
}
if (n != nullptr) {
log(" creating $alu model for %s (%s): merged with %s.\n", log_id(cell), log_id(cell->type), log_id(n->cells.front()));
log(" creating $alu model for %s (%s): merged with %s.\n", cell, cell->type.unescape(), n->cells.front());
n->cells.push_back(cell);
n->cmp.push_back(std::make_tuple(false, false, cmp_equal, !cmp_equal, false, Y));
}
@ -503,8 +503,8 @@ struct AlumaccWorker
log(" creating $pos cell for ");
for (int i = 0; i < GetSize(n->cells); i++)
log("%s%s", i ? ", ": "", log_id(n->cells[i]));
log(": %s\n", log_id(n->alu_cell));
log("%s%s", i ? ", ": "", n->cells[i]);
log(": %s\n", n->alu_cell);
goto delete_node;
}
@ -514,8 +514,8 @@ struct AlumaccWorker
log(" creating $alu cell for ");
for (int i = 0; i < GetSize(n->cells); i++)
log("%s%s", i ? ", ": "", log_id(n->cells[i]));
log(": %s\n", log_id(n->alu_cell));
log("%s%s", i ? ", ": "", n->cells[i]);
log(": %s\n", n->alu_cell);
if (n->cells.size() > 0)
n->alu_cell->set_src_attribute(n->cells[0]->get_src_attribute());
@ -562,7 +562,7 @@ struct AlumaccWorker
void run()
{
log("Extracting $alu and $macc cells in module %s:\n", log_id(module));
log("Extracting $alu and $macc cells in module %s:\n", module);
count_bit_users();
extract_macc();

2
passes/techmap/arith_tree.cc
View file

@ -316,7 +316,7 @@ struct Rewriter {
int compressor_count;
auto [a, b] = wallace_reduce_scheduled(module, extended, width, &compressor_count);
log(" %s -> %d $fa + 1 $add (%d operands, module %s)\n", desc, compressor_count, (int)operands.size(), log_id(module));
log(" %s -> %d $fa + 1 $add (%d operands, module %s)\n", desc, compressor_count, (int)operands.size(), module);
// Emit final add
module->addAdd(NEW_ID, a, b, result_y, false);

14
passes/techmap/attrmap.cc
View file

@ -131,13 +131,13 @@ void attrmap_apply(string objname, vector<std::unique_ptr<AttrmapAction>> &actio
if (new_attr != attr)
log("Changed attribute on %s: %s=%s -> %s=%s\n", objname,
log_id(attr.first), log_const(attr.second), log_id(new_attr.first), log_const(new_attr.second));
attr.first.unescape(), log_const(attr.second), new_attr.first.unescape(), log_const(new_attr.second));
new_attributes[new_attr.first] = new_attr.second;
if (0)
delete_this_attr:
log("Removed attribute on %s: %s=%s\n", objname, log_id(attr.first), log_const(attr.second));
log("Removed attribute on %s: %s=%s\n", objname, attr.first.unescape(), log_const(attr.second));
}
attributes.swap(new_attributes);
@ -264,14 +264,14 @@ struct AttrmapPass : public Pass {
if (modattr_mode)
{
for (auto module : design->all_selected_whole_modules())
attrmap_apply(stringf("%s", log_id(module)), actions, module->attributes);
attrmap_apply(stringf("%s", module), actions, module->attributes);
}
else
{
for (auto module : design->all_selected_modules())
{
for (auto memb : module->selected_members())
attrmap_apply(stringf("%s.%s", log_id(module), log_id(memb)), actions, memb->attributes);
attrmap_apply(stringf("%s.%s", module, memb), actions, memb->attributes);
// attrmap already applied to process itself during above loop, but not its children
for (auto proc : module->selected_processes())
@ -280,10 +280,10 @@ struct AttrmapPass : public Pass {
while (!all_cases.empty()) {
RTLIL::CaseRule *cs = all_cases.back();
all_cases.pop_back();
attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc)), actions, cs->attributes);
attrmap_apply(stringf("%s.%s (case)", module, proc), actions, cs->attributes);
for (auto &sw : cs->switches) {
attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc)), actions, sw->attributes);
attrmap_apply(stringf("%s.%s (switch)", module, proc), actions, sw->attributes);
all_cases.insert(all_cases.end(), sw->cases.begin(), sw->cases.end());
}
}
@ -328,7 +328,7 @@ struct ParamapPass : public Pass {
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells())
attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->parameters);
attrmap_apply(stringf("%s.%s", module, cell), actions, cell->parameters);
}
} ParamapPass;

4
passes/techmap/attrmvcp.cc
View file

@ -121,8 +121,8 @@ struct AttrmvcpPass : public Pass {
for (auto bit : sigmap(wire))
if (net2cells.count(bit))
for (auto cell : net2cells.at(bit)) {
log("Moving attribute %s=%s from %s.%s to %s.%s.\n", log_id(attr.first), log_const(attr.second),
log_id(module), log_id(wire), log_id(module), log_id(cell));
log("Moving attribute %s=%s from %s.%s to %s.%s.\n", attr.first.unescape(), log_const(attr.second),
module, wire, module, cell);
cell->attributes[attr.first] = attr.second;
did_something = true;
}

6
passes/techmap/booth.cc
View file

@ -224,7 +224,7 @@ struct BoothPassWorker {
macc.from_cell(cell);
if (!macc.is_simple_product()) {
log_debug("Not mapping cell %s: not a simple macc cell\n", log_id(cell));
log_debug("Not mapping cell %s: not a simple macc cell\n", cell);
continue;
}
@ -240,11 +240,11 @@ struct BoothPassWorker {
if (x_sz < 4 || y_sz < 4 || z_sz < 8) {
log_debug("Not mapping cell %s sized at %dx%x, %x: size below threshold\n",
log_id(cell), x_sz, y_sz, z_sz);
cell, x_sz, y_sz, z_sz);
continue;
}
log("Mapping cell %s to %s Booth multiplier\n", log_id(cell), is_signed ? "signed" : "unsigned");
log("Mapping cell %s to %s Booth multiplier\n", cell, is_signed ? "signed" : "unsigned");
// To simplify the generator size the arguments
// to be the same. Then allow logic synthesis to

8
passes/techmap/bufnorm.cc
View file

@ -249,7 +249,7 @@ struct BufnormPass : public Pass {
for (auto module : design->selected_modules())
{
log("Buffer-normalizing module %s.\n", log_id(module));
log("Buffer-normalizing module %s.\n", module);
SigMap sigmap(module);
module->new_connections({});
@ -293,7 +293,7 @@ struct BufnormPass : public Pass {
bit2wires[keybit].insert(wire);
if (wire->port_input) {
log(" primary input: %s\n", log_id(wire));
log(" primary input: %s\n", wire);
for (auto bit : SigSpec(wire))
mapped_bits[sigmap(bit)] = bit;
} else {
@ -392,7 +392,7 @@ struct BufnormPass : public Pass {
if (w->name.isPublic())
log(" directly driven by cell %s port %s: %s\n",
log_id(cell), log_id(conn.first), log_id(w));
cell, conn.first.unescape(), w);
for (auto bit : SigSpec(w))
mapped_bits[sigmap(bit)] = bit;
@ -502,7 +502,7 @@ struct BufnormPass : public Pass {
if (conn.second != newsig) {
log(" fixing input signal on cell %s port %s: %s\n",
log_id(cell), log_id(conn.first), log_signal(newsig));
cell, conn.first.unescape(), newsig);
cell->setPort(conn.first, newsig);
count_updated_cellports++;
}

18
passes/techmap/cellmatch.cc
View file

@ -20,7 +20,7 @@ SigSpec module_inputs(Module *m)
continue;
if (w->width != 1)
log_error("Unsupported wide port (%s) of non-unit width found in module %s.\n",
log_id(w), log_id(m));
w, m);
ret.append(w);
}
return ret;
@ -36,7 +36,7 @@ SigSpec module_outputs(Module *m)
continue;
if (w->width != 1)
log_error("Unsupported wide port (%s) of non-unit width found in module %s.\n",
log_id(w), log_id(m));
w, m);
ret.append(w);
}
return ret;
@ -96,7 +96,7 @@ bool derive_module_luts(Module *m, std::vector<uint64_t> &luts)
ff_types.setup_stdcells_mem();
for (auto cell : m->cells()) {
if (ff_types.cell_known(cell->type)) {
log("Ignoring module '%s' which isn't purely combinational.\n", log_id(m));
log("Ignoring module '%s' which isn't purely combinational.\n", m);
return false;
}
}
@ -106,7 +106,7 @@ bool derive_module_luts(Module *m, std::vector<uint64_t> &luts)
int ninputs = inputs.size(), noutputs = outputs.size();
if (ninputs > 6) {
log_warning("Skipping module %s with more than 6 inputs bits.\n", log_id(m));
log_warning("Skipping module %s with more than 6 inputs bits.\n", m);
return false;
}
@ -123,7 +123,7 @@ bool derive_module_luts(Module *m, std::vector<uint64_t> &luts)
if (!ceval.eval(bit)) {
log("Failed to evaluate output '%s' in module '%s'.\n",
log_signal(outputs[j]), log_id(m));
log_signal(outputs[j]), m);
return false;
}
@ -203,7 +203,7 @@ struct CellmatchPass : Pass {
for (auto lut : luts)
p_classes.insert(p_class(ninputs, lut));
log_debug("Registered %s\n", log_id(m));
log_debug("Registered %s\n", m);
// save as a viable target
targets[p_classes].push_back(Target{m, luts});
@ -237,7 +237,7 @@ struct CellmatchPass : Pass {
p_classes.insert(p_class(inputs.size(), lut));
for (auto target : targets[p_classes]) {
log_debug("Candidate %s for matching to %s\n", log_id(target.module), log_id(m));
log_debug("Candidate %s for matching to %s\n", target.module, m);
SigSpec target_inputs = module_inputs(target.module);
SigSpec target_outputs = module_outputs(target.module);
@ -271,10 +271,10 @@ struct CellmatchPass : Pass {
}
if (match) {
log("Module %s matches %s\n", log_id(m), log_id(target.module));
log("Module %s matches %s\n", m, target.module);
// Add target.module to map_design ("$cellmatch")
// as a techmap rule to match m and replace it with target.module
Module *map = map_design->addModule(stringf("\\_60_%s_%s", log_id(m), log_id(target.module)));
Module *map = map_design->addModule(stringf("\\_60_%s_%s", m, target.module));
Cell *cell = map->addCell(ID::_TECHMAP_REPLACE_, target.module->name);
map->attributes[ID(techmap_celltype)] = m->name.str();

4
passes/techmap/clkbufmap.cc
View file

@ -257,14 +257,14 @@ struct ClkbufmapPass : public Pass {
RTLIL::Cell *cell = nullptr;
bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top);
if (!buf_celltype.empty() && (!is_input || buffer_inputs)) {
log("Inserting %s on %s.%s[%d].\n", buf_celltype, log_id(module), log_id(wire), i);
log("Inserting %s on %s.%s[%d].\n", buf_celltype, module, wire, i);
cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
iwire = module->addWire(NEW_ID);
cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
}
if (is_input) {
log("Inserting %s on %s.%s[%d].\n", inpad_celltype, log_id(module), log_id(wire), i);
log("Inserting %s on %s.%s[%d].\n", inpad_celltype, module, wire, i);
RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
if (iwire) {
cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);

2
passes/techmap/deminout.cc
View file

@ -126,7 +126,7 @@ struct DeminoutPass : public Pass {
}
if (new_input != new_output) {
log("Demoting inout port %s.%s to %s.\n", log_id(module), log_id(wire), new_input ? "input" : "output");
log("Demoting inout port %s.%s to %s.\n", module, wire, new_input ? "input" : "output");
wire->port_input = new_input;
wire->port_output = new_output;
keep_running = true;

8
passes/techmap/dffinit.cc
View file

@ -123,14 +123,14 @@ struct DffinitPass : public Pass {
if (noreinit && value[i] != State::Sx && value[i] != initval[i])
log_error("Trying to assign a different init value for %s.%s.%s which technically "
"have a conflicted init value.\n",
log_id(module), log_id(cell), log_id(it.second));
module, cell, it.second.unescape());
value.set(i, initval[i]);
}
if (highlow_mode && GetSize(value) != 0) {
if (GetSize(value) != 1)
log_error("Multi-bit init value for %s.%s.%s is incompatible with -highlow mode.\n",
log_id(module), log_id(cell), log_id(it.second));
module, cell, it.second.unescape());
if (value[0] == State::S1)
value = Const(high_string);
else
@ -138,8 +138,8 @@ struct DffinitPass : public Pass {
}
if (value.size() != 0) {
log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", log_id(module), log_id(cell), log_id(it.second),
log_id(it.first), log_signal(sig), log_signal(value));
log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", module, cell, it.second.unescape(),
it.first.unescape(), log_signal(sig), log_signal(value));
cell->setParam(it.second, value);
}
}

8
passes/techmap/dfflegalize.cc
View file

@ -263,7 +263,7 @@ struct DffLegalizePass : public Pass {
}
void fail_ff(const FfData &ff, const char *reason) {
log_error("FF %s.%s (type %s) cannot be legalized: %s\n", log_id(ff.module->name), log_id(ff.cell->name), log_id(ff.cell->type), reason);
log_error("FF %s.%s (type %s) cannot be legalized: %s\n", ff.module->name.unescape(), ff.cell->name.unescape(), ff.cell->type.unescape(), reason);
}
bool try_flip(FfData &ff, int supported_mask) {
@ -381,7 +381,7 @@ struct DffLegalizePass : public Pass {
if (ff.has_ce && !supported_cells[FF_ADFFE])
ff.unmap_ce();
log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", log_id(ff.module->name), log_id(ff.cell->name));
log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->name.unescape());
log_assert(ff.width == 1);
ff.remove();
@ -600,7 +600,7 @@ struct DffLegalizePass : public Pass {
ff.unmap_ce();
if (ff.cell)
log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", log_id(ff.module->name), log_id(ff.cell->name));
log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->name.unescape());
emulate_split_init_arst(ff);
return;
}
@ -752,7 +752,7 @@ struct DffLegalizePass : public Pass {
// The only hope left is breaking down to adlatch + dlatch + dlatch + mux.
if (ff.cell)
log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", log_id(ff.module->name), log_id(ff.cell->name));
log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->name.unescape());
ff.remove();
emulate_split_init_arst(ff);

12
passes/techmap/extract.cc
View file

@ -155,12 +155,12 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
std::map<RTLIL::SigBit, bit_ref_t> sig_bit_ref;
if (sel && !sel->selected(mod)) {
log(" Skipping module %s as it is not selected.\n", log_id(mod->name));
log(" Skipping module %s as it is not selected.\n", mod->name.unescape());
return false;
}
if (mod->processes.size() > 0) {
log(" Skipping module %s as it contains unprocessed processes.\n", log_id(mod->name));
log(" Skipping module %s as it contains unprocessed processes.\n", mod->name.unescape());
return false;
}
@ -674,7 +674,7 @@ struct ExtractPass : public Pass {
}
RTLIL::Cell *new_cell = replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result);
design->select(haystack_map.at(result.haystackGraphId), new_cell);
log(" new cell: %s\n", log_id(new_cell->name));
log(" new cell: %s\n", new_cell->name.unescape());
}
}
}
@ -691,12 +691,12 @@ struct ExtractPass : public Pass {
for (auto &result: results)
{
log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits);
log(" primary match in %s:", log_id(haystack_map.at(result.graphId)->name));
log(" primary match in %s:", haystack_map.at(result.graphId)->name.unescape());
for (auto &node : result.nodes)
log(" %s", RTLIL::unescape_id(node.nodeId));
log("\n");
for (auto &it : result.matchesPerGraph)
log(" matches in %s: %d\n", log_id(haystack_map.at(it.first)->name), it.second);
log(" matches in %s: %d\n", haystack_map.at(it.first)->name.unescape(), it.second);
RTLIL::Module *mod = haystack_map.at(result.graphId);
std::set<RTLIL::Cell*> cells;
@ -716,7 +716,7 @@ struct ExtractPass : public Pass {
}
RTLIL::Module *newMod = new RTLIL::Module;
newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, log_id(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, haystack_map.at(result.graphId)->name.unescape(), result.totalMatchesAfterLimits);
map->add(newMod);
for (auto wire : wires) {

14
passes/techmap/extract_counter.cc
View file

@ -541,7 +541,7 @@ void counter_worker(
{
extract_value = *sa.begin();
log(" Signal %s declared at %s has COUNT_EXTRACT = %s\n",
log_id(port_wire),
port_wire,
count_reg_src.c_str(),
extract_value.c_str());
@ -604,14 +604,14 @@ void counter_worker(
{
log_error(
"Counter extraction is set to FORCE on register %s, but a counter could not be inferred (%s)\n",
log_id(port_wire),
port_wire,
reasons[reason]);
}
return;
}
//Get new cell name
string countname = string("$COUNTx$") + log_id(extract.rwire->name.str());
string countname = string("$COUNTx$") + extract.rwire->name.unescape();
//Wipe all of the old connections to the ALU
cell->unsetPort(ID::A);
@ -697,7 +697,7 @@ void counter_worker(
//Hook up any parallel outputs
for(auto load : extract.pouts)
{
log(" Counter has parallel output to cell %s port %s\n", log_id(load.cell->name), log_id(load.port));
log(" Counter has parallel output to cell %s port %s\n", load.cell->name.unescape(), load.port.unescape());
}
if(extract.has_pout)
{
@ -731,7 +731,7 @@ void counter_worker(
countname.c_str(),
extract.count_is_up ? "to" : "from",
extract.count_value,
log_id(extract.rwire->name),
extract.rwire->name.unescape(),
count_reg_src.c_str());
//Optimize the counter
@ -887,13 +887,13 @@ struct ExtractCounterPass : public Pass {
for(auto cell : cells_to_remove)
{
//log("Removing cell %s\n", log_id(cell->name));
//log("Removing cell %s\n", cell);
module->remove(cell);
}
for(auto cpair : cells_to_rename)
{
//log("Renaming cell %s to %s\n", log_id(cpair.first->name), cpair.second);
//log("Renaming cell %s to %s\n", cpair.first, cpair.second);
module->rename(cpair.first, cpair.second);
}
}

14
passes/techmap/extract_fa.cc
View file

@ -289,7 +289,7 @@ struct ExtractFaWorker
void run()
{
log("Extracting full/half adders from %s:\n", log_id(module));
log("Extracting full/half adders from %s:\n", module);
for (auto it : driver)
{
@ -381,7 +381,7 @@ struct ExtractFaWorker
auto &fa = facache.at(fakey);
X = get<0>(fa);
Y = get<1>(fa);
log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
log(" Reusing $fa cell %s.\n", get<2>(fa));
}
else
if (facache.count(fakey_inv))
@ -390,14 +390,14 @@ struct ExtractFaWorker
invert_xy = true;
X = get<0>(fa);
Y = get<1>(fa);
log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
log(" Reusing $fa cell %s.\n", get<2>(fa));
}
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", log_id(cell));
log(" Created $fa cell %s.\n", cell);
cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
@ -488,7 +488,7 @@ struct ExtractFaWorker
auto &fa = facache.at(fakey);
X = get<0>(fa);
Y = get<1>(fa);
log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
log(" Reusing $fa cell %s.\n", get<2>(fa));
}
else
if (facache.count(fakey_inv))
@ -497,14 +497,14 @@ struct ExtractFaWorker
invert_xy = true;
X = get<0>(fa);
Y = get<1>(fa);
log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
log(" Reusing $fa cell %s.\n", get<2>(fa));
}
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", log_id(cell));
log(" Created $fa cell %s.\n", cell);
cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);

4
passes/techmap/extractinv.cc
View file

@ -100,7 +100,7 @@ struct ExtractinvPass : public Pass {
continue;
SigSpec sig = port.second;
if (it2->second.size() != sig.size())
log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", log_id(module->name), log_id(cell->type), log_id(port.first), log_id(param_name));
log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", module->name.unescape(), cell->type.unescape(), port.first.unescape(), param_name.unescape());
RTLIL::Const invmask = it2->second;
cell->parameters.erase(param_name);
if (invmask.is_fully_zero())
@ -111,7 +111,7 @@ struct ExtractinvPass : public Pass {
RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype));
icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, log_id(module), log_id(cell->type), log_id(port.first), i);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, module, cell->type.unescape(), port.first.unescape(), i);
sig[i] = SigBit(iwire, i);
}
cell->setPort(port.first, sig);

18
passes/techmap/flowmap.cc
View file

@ -598,7 +598,7 @@ struct FlowmapWorker
continue;
if (!cell->known())
log_error("Cell %s (%s.%s) is unknown.\n", cell->type, log_id(module), log_id(cell));
log_error("Cell %s (%s.%s) is unknown.\n", cell->type, module, cell);
pool<RTLIL::SigBit> fanout;
for (auto conn : cell->connections())
@ -636,7 +636,7 @@ struct FlowmapWorker
if (fanin > order)
log_error("Cell %s (%s.%s) with fan-in %d cannot be mapped to a %d-LUT.\n",
cell->type.c_str(), log_id(module), log_id(cell), fanin, order);
cell->type.c_str(), module, cell, fanin, order);
gate_count++;
gate_area += 1 << fanin;
@ -1356,14 +1356,14 @@ struct FlowmapWorker
auto origin = node_origins[node];
if (origin.cell->getPort(origin.port).size() == 1)
log("Packing %s.%s.%s (%s).\n",
log_id(module), log_id(origin.cell), origin.port.c_str(), log_signal(node));
module, origin.cell, origin.port.c_str(), log_signal(node));
else
log("Packing %s.%s.%s [%d] (%s).\n",
log_id(module), log_id(origin.cell), origin.port.c_str(), origin.offset, log_signal(node));
module, origin.cell, origin.port.c_str(), origin.offset, log_signal(node));
}
else
{
log("Packing %s.%s.\n", log_id(module), log_signal(node));
log("Packing %s.%s.\n", module, log_signal(node));
}
for (auto gate_node : lut_gates[node])
@ -1376,10 +1376,10 @@ struct FlowmapWorker
auto gate_origin = node_origins[gate_node];
if (gate_origin.cell->getPort(gate_origin.port).size() == 1)
log(" Packing %s.%s.%s (%s).\n",
log_id(module), log_id(gate_origin.cell), gate_origin.port.c_str(), log_signal(gate_node));
module, gate_origin.cell, gate_origin.port.c_str(), log_signal(gate_node));
else
log(" Packing %s.%s.%s [%d] (%s).\n",
log_id(module), log_id(gate_origin.cell), gate_origin.port.c_str(), gate_origin.offset, log_signal(gate_node));
module, gate_origin.cell, gate_origin.port.c_str(), gate_origin.offset, log_signal(gate_node));
}
vector<RTLIL::SigBit> input_nodes(lut_edges_bw[node].begin(), lut_edges_bw[node].end());
@ -1423,9 +1423,9 @@ struct FlowmapWorker
lut_area += lut_table.size();
if ((int)input_nodes.size() >= minlut)
log(" Packed into a %d-LUT %s.%s.\n", GetSize(input_nodes), log_id(module), log_id(lut));
log(" Packed into a %d-LUT %s.%s.\n", GetSize(input_nodes), module, lut);
else
log(" Packed into a %d-LUT %s.%s (implemented as %d-LUT).\n", GetSize(input_nodes), log_id(module), log_id(lut), minlut);
log(" Packed into a %d-LUT %s.%s (implemented as %d-LUT).\n", GetSize(input_nodes), module, lut, minlut);
}
for (auto node : mapped_nodes)

8
passes/techmap/insbuf.cc
View file

@ -83,7 +83,7 @@ struct InsbufPass : public Pass {
if (!lhs.wire || !design->selected(module, lhs.wire)) {
new_conn.first.append(lhs);
new_conn.second.append(rhs);
log("Skip %s: %s -> %s\n", log_id(module), log_signal(rhs), log_signal(lhs));
log("Skip %s: %s -> %s\n", module, log_signal(rhs), log_signal(lhs));
continue;
}
@ -98,7 +98,7 @@ struct InsbufPass : public Pass {
cell->setPort(in_portname, rhs);
cell->setPort(out_portname, lhs);
log("Add %s/%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs));
log("Add %s/%s: %s -> %s\n", module, cell, log_signal(rhs), log_signal(lhs));
bufcells.insert(cell);
}
@ -115,8 +115,8 @@ struct InsbufPass : public Pass {
auto s = sigmap(port.second);
if (s == port.second)
continue;
log("Rewrite %s/%s/%s: %s -> %s\n", log_id(module), log_id(cell),
log_id(port.first), log_signal(port.second), log_signal(s));
log("Rewrite %s/%s/%s: %s -> %s\n", module, cell,
port.first.unescape(), log_signal(port.second), log_signal(s));
cell->setPort(port.first, s);
}
}

18
passes/techmap/iopadmap.cc
View file

@ -231,7 +231,7 @@ struct IopadmapPass : public Pass {
for (int i = 0; i < GetSize(wire); i++)
if (buf_bits.count(sigmap(SigBit(wire, i)))) {
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
log("Marking already mapped port: %s.%s[%d].\n", log_id(module), log_id(wire), i);
log("Marking already mapped port: %s.%s[%d].\n", module, wire, i);
}
}
@ -324,10 +324,10 @@ struct IopadmapPass : public Pass {
if (wire->port_input)
{
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype);
log("Mapping port %s.%s[%d] using %s.\n", module, wire, i, tinoutpad_celltype);
Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)),
module->uniquify(stringf("$iopadmap$%s.%s[%d]", module, wire, i)),
RTLIL::escape_id(tinoutpad_celltype));
if (tinoutpad_neg_oe)
@ -348,10 +348,10 @@ struct IopadmapPass : public Pass {
if (!tinoutpad_portname_pad.empty())
rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(tinoutpad_portname_pad));
} else {
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype);
log("Mapping port %s.%s[%d] using %s.\n", module, wire, i, toutpad_celltype);
Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)),
module->uniquify(stringf("$iopadmap$%s.%s[%d]", module, wire, i)),
RTLIL::escape_id(toutpad_celltype));
if (toutpad_neg_oe)
@ -433,7 +433,7 @@ struct IopadmapPass : public Pass {
SigBit wire_bit(wire, i);
RTLIL::Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s", log_id(module->name), log_id(wire->name))),
module->uniquify(stringf("$iopadmap$%s.%s", module->name.unescape(), wire->name.unescape())),
RTLIL::escape_id(celltype));
cell->setPort(RTLIL::escape_id(portname_int), wire_bit);
@ -449,14 +449,14 @@ struct IopadmapPass : public Pass {
else
{
RTLIL::Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s", log_id(module->name), log_id(wire->name))),
module->uniquify(stringf("$iopadmap$%s.%s", module->name.unescape(), wire->name.unescape())),
RTLIL::escape_id(celltype));
cell->setPort(RTLIL::escape_id(portname_int), RTLIL::SigSpec(wire));
if (!portname_pad.empty()) {
RTLIL::Wire *new_wire = NULL;
new_wire = module->addWire(
module->uniquify(stringf("$iopadmap$%s", log_id(wire))),
module->uniquify(stringf("$iopadmap$%s", wire)),
wire);
module->swap_names(new_wire, wire);
wire->attributes.clear();
@ -500,7 +500,7 @@ struct IopadmapPass : public Pass {
for (auto &it : rewrite_bits) {
RTLIL::Wire *wire = it.first;
RTLIL::Wire *new_wire = module->addWire(
module->uniquify(stringf("$iopadmap$%s", log_id(wire))),
module->uniquify(stringf("$iopadmap$%s", wire)),
wire);
module->swap_names(new_wire, wire);
wire->attributes.clear();

2
passes/techmap/lut2bmux.cc
View file

@ -49,7 +49,7 @@ struct Lut2BmuxPass : public Pass {
cell->setPort(ID::A, cell->getParam(ID::LUT));
cell->unsetParam(ID::LUT);
cell->fixup_parameters();
log("Converted %s.%s to BMUX cell.\n", log_id(module), log_id(cell));
log("Converted %s.%s to BMUX cell.\n", module, cell);
}
}
}

2
passes/techmap/lut2mux.cc
View file

@ -97,7 +97,7 @@ struct Lut2muxPass : public Pass {
if (cell->type == ID($lut)) {
IdString cell_name = cell->name;
int count = lut2mux(cell, word_mode);
log("Converted %s.%s to %d MUX cells.\n", log_id(module), log_id(cell_name), count);
log("Converted %s.%s to %d MUX cells.\n", module, cell_name.unescape(), count);
}
}
}

2
passes/techmap/maccmap.cc
View file

@ -404,7 +404,7 @@ struct MaccmapPass : public Pass {
for (auto mod : design->selected_modules())
for (auto cell : mod->selected_cells())
if (cell->type.in(ID($macc), ID($macc_v2))) {
log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type));
log("Mapping %s.%s (%s).\n", mod, cell, cell->type.unescape());
maccmap(mod, cell, unmap_mode);
mod->remove(cell);
}

2
passes/techmap/muxcover.cc
View file

@ -596,7 +596,7 @@ struct MuxcoverWorker
void run()
{
log("Covering MUX trees in module %s..\n", log_id(module));
log("Covering MUX trees in module %s..\n", module);
treeify();

2
passes/techmap/shregmap.cc
View file

@ -284,7 +284,7 @@ struct ShregmapWorker
Cell *last_cell = chain[cursor+depth-1];
log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
module, first_cell, module, last_cell, depth);
dff_count += depth;
shreg_count += 1;

2
passes/techmap/simplemap.cc
View file

@ -580,7 +580,7 @@ struct SimplemapPass : public Pass {
continue;
if (!design->selected(mod, cell))
continue;
log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type));
log("Mapping %s.%s (%s).\n", mod, cell, cell->type.unescape());
mappers.at(cell->type)(mod, cell);
mod->remove(cell);
}

88
passes/techmap/techmap.cc
View file

@ -93,17 +93,17 @@ struct TechmapWorker
RTLIL::SigBit bit = sigmap(conn.second[i]);
if (bit.wire == nullptr) {
if (verbose)
log(" Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit));
constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data);
log(" Constant input on bit %d of port %s: %s\n", i, conn.first.unescape(), log_signal(bit));
constmap_info += stringf("|%s %d %d", conn.first.unescape(), i, bit.data);
} else if (connbits_map.count(bit)) {
if (verbose)
log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first),
connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, conn.first.unescape(),
connbits_map.at(bit).second, connbits_map.at(bit).first.unescape());
constmap_info += stringf("|%s %d %s %d", conn.first.unescape(), i,
connbits_map.at(bit).first.unescape(), connbits_map.at(bit).second);
} else {
connbits_map.emplace(bit, std::make_pair(conn.first, i));
constmap_info += stringf("|%s %d", log_id(conn.first), i);
constmap_info += stringf("|%s %d", conn.first.unescape(), i);
}
}
@ -146,7 +146,7 @@ struct TechmapWorker
if (tpl->processes.size() != 0) {
log("Technology map yielded processes:");
for (auto &it : tpl->processes)
log(" %s",log_id(it.first));
log(" %s",it.first.unescape());
log("\n");
if (autoproc_mode) {
Pass::call_on_module(tpl->design, tpl, "proc");
@ -435,7 +435,7 @@ struct TechmapWorker
if (celltypeMap.count(cell->type) == 0) {
if (assert_mode && !cell->type.ends_with("_"))
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type));
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", cell->type.unescape());
continue;
}
@ -498,10 +498,10 @@ struct TechmapWorker
{
if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
{
std::string m_name = stringf("$extern:%s:%s", extmapper_name, log_id(cell->type));
std::string m_name = stringf("$extern:%s:%s", extmapper_name, cell->type.unescape());
for (auto &c : cell->parameters)
m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
m_name += stringf(":%s=%s", c.first.unescape(), log_signal(c.second));
if (extmapper_name == "wrap")
m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
@ -531,24 +531,24 @@ struct TechmapWorker
extmapper_module->check();
if (extmapper_name == "simplemap") {
log("Creating %s with simplemap.\n", log_id(extmapper_module));
log("Creating %s with simplemap.\n", extmapper_module);
if (simplemap_mappers.count(extmapper_cell->type) == 0)
log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
log_error("No simplemap mapper for cell type %s found!\n", extmapper_cell->type.unescape());
simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
extmapper_module->remove(extmapper_cell);
}
if (extmapper_name == "maccmap") {
log("Creating %s with maccmap.\n", log_id(extmapper_module));
log("Creating %s with maccmap.\n", extmapper_module);
if (!extmapper_cell->type.in(ID($macc), ID($macc_v2)))
log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", log_id(extmapper_cell->type));
log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", extmapper_cell->type.unescape());
maccmap(extmapper_module, extmapper_cell);
extmapper_module->remove(extmapper_cell);
}
if (extmapper_name == "wrap") {
std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
log("Running \"%s\" on wrapper %s.\n", cmd_string, log_id(extmapper_module));
log("Running \"%s\" on wrapper %s.\n", cmd_string, extmapper_module);
mkdebug.on();
Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
log_continue = true;
@ -563,31 +563,31 @@ struct TechmapWorker
goto use_wrapper_tpl;
}
auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_module, cell->type.unescape());
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix, log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix, module, cell, cell->type.unescape(), extmapper_module);
}
else
{
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, log_id(cell->type));
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, cell->type.unescape());
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix, log_id(module), log_id(cell), log_id(cell->type), extmapper_name);
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix, module, cell, cell->type.unescape(), extmapper_name);
if (extmapper_name == "simplemap") {
if (simplemap_mappers.count(cell->type) == 0)
log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type));
log_error("No simplemap mapper for cell type %s found!\n", cell->type.unescape());
simplemap_mappers.at(cell->type)(module, cell);
}
if (extmapper_name == "maccmap") {
if (!cell->type.in(ID($macc), ID($macc_v2)))
log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", log_id(cell->type));
log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", cell->type.unescape());
maccmap(module, cell);
}
@ -621,21 +621,21 @@ struct TechmapWorker
parameters.emplace(ID::_TECHMAP_CELLNAME_, RTLIL::unescape_id(cell->name));
for (auto &conn : cell->connections()) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", conn.first.unescape())) != 0) {
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
for (auto &bit : v)
bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0);
parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", conn.first.unescape()), RTLIL::SigSpec(v).as_const());
}
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", conn.first.unescape())) != 0) {
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
for (auto &bit : v)
if (bit.wire != nullptr)
bit = RTLIL::SigBit(RTLIL::State::Sx);
parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", conn.first.unescape()), RTLIL::SigSpec(v).as_const());
}
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) {
parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), initvals(conn.second));
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", conn.first.unescape())) != 0) {
parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", conn.first.unescape()), initvals(conn.second));
}
}
@ -648,7 +648,7 @@ struct TechmapWorker
unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
for (auto &conn : cell->connections())
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", conn.first.unescape())) != 0) {
for (auto &bit : sigmap(conn.second))
if (unique_bit_id.count(bit) == 0)
unique_bit_id[bit] = unique_bit_id_counter++;
@ -665,7 +665,7 @@ struct TechmapWorker
parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits;
for (auto &conn : cell->connections())
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", conn.first.unescape())) != 0) {
SigSpec sm = sigmap(conn.second);
RTLIL::Const::Builder builder(GetSize(sm) * bits);
for (auto &bit : sm) {
@ -675,7 +675,7 @@ struct TechmapWorker
val = val >> 1;
}
}
parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), builder.build());
parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", conn.first.unescape()), builder.build());
}
}
@ -724,7 +724,7 @@ struct TechmapWorker
RTLIL::SigSpec value = elem.value;
if (value.is_fully_const() && value.as_bool()) {
log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
derived_name.c_str(), log_id(elem.wire->name), log_signal(value));
derived_name.c_str(), elem.wire->name.unescape(), log_signal(value));
techmap_do_cache[tpl] = false;
}
}
@ -741,7 +741,7 @@ struct TechmapWorker
auto &data = it.second.front();
if (!data.value.is_fully_const())
log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(data.wire->name), log_signal(data.value));
log_error("Techmap yielded config wire %s with non-const value %s.\n", data.wire->name.unescape(), log_signal(data.value));
techmap_wire_names.erase(it.first);
@ -758,7 +758,7 @@ struct TechmapWorker
log("Analyzing pattern of constant bits for this cell:\n");
IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
log("Creating constmapped module `%s'.\n", new_tpl_name.unescape());
log_assert(map->module(new_tpl_name) == nullptr);
RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
@ -865,16 +865,16 @@ struct TechmapWorker
TechmapWires twd = techmap_find_special_wires(tpl);
for (auto &it : twd) {
if (!it.first.ends_with("_TECHMAP_FAIL_") && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.contains("_TECHMAP_DO_") && !it.first.contains("_TECHMAP_DONE_"))
log_error("Techmap yielded unknown config wire %s.\n", log_id(it.first));
log_error("Techmap yielded unknown config wire %s.\n", it.first.unescape());
if (techmap_do_cache[tpl])
for (auto &it2 : it.second)
if (!it2.value.is_fully_const())
log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(it2.wire->name), log_signal(it2.value));
log_error("Techmap yielded config wire %s with non-const value %s.\n", it2.wire->name.unescape(), log_signal(it2.value));
techmap_wire_names.erase(it.first);
}
for (auto &it : techmap_wire_names)
log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", log_id(it));
log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", it.unescape());
if (recursive_mode) {
if (log_continue) {
@ -914,7 +914,7 @@ struct TechmapWorker
if (extern_mode && !in_recursion)
{
std::string m_name = stringf("$extern:%s", log_id(tpl));
std::string m_name = stringf("$extern:%s", tpl);
if (!design->module(m_name))
{
@ -924,18 +924,18 @@ struct TechmapWorker
module_queue.insert(m);
}
log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix, log_id(module), log_id(cell), log_id(m_name));
log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix, module, cell, m_name);
cell->type = m_name;
cell->parameters.clear();
}
else
{
auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
auto msg = stringf("Using template %s for cells of type %s.", tpl, cell->type.unescape());
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix, log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix, module, cell, cell->type.unescape(), tpl);
techmap_module_worker(design, module, cell, tpl);
cell = nullptr;
}
@ -945,7 +945,7 @@ struct TechmapWorker
}
if (assert_mode && !mapped_cell)
log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", module, cell, cell->type.unescape());
handled_cells.insert(cell);
}
@ -1265,8 +1265,8 @@ struct TechmapPass : public Pass {
i.second.sort(RTLIL::sort_by_id_str());
std::string maps = "";
for (auto &map : i.second)
maps += stringf(" %s", log_id(map));
log_debug(" %s:%s\n", log_id(i.first), maps);
maps += stringf(" %s", map);
log_debug(" %s:%s\n", i.first.unescape(), maps);
}
log_debug("\n");

2
passes/techmap/tribuf.cc
View file

@ -142,7 +142,7 @@ struct TribufWorker {
auto conflict = module->And(NEW_ID, cell_s, other_s);
std::string name = stringf("$tribuf_conflict$%s", log_id(cell->name));
std::string name = stringf("$tribuf_conflict$%s", cell->name.unescape());
auto assert_cell = module->addAssert(name, module->Not(NEW_ID, conflict), SigSpec(true));
assert_cell->set_src_attribute(cell->get_src_attribute());

2
passes/techmap/zinit.cc
View file

@ -68,7 +68,7 @@ struct ZinitPass : public Pass {
FfData ff(&initvals, cell);
log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type),
log("FF init value for cell %s (%s): %s = %s\n", cell, cell->type.unescape(),
log_signal(ff.sig_q), log_signal(ff.val_init));
pool<int> bits;