mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-02 07:07:56 +00:00
Code Activity

Refactored uses of log_id()

Browse source
This commit is contained in:
Codexplorer 2026-05-08 00:01:43 -07:00
parent 89d83a3410
commit e41b969da2
186 changed files with 1219 additions and 1220 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/pmgen/generate.h
View file

@ -106,7 +106,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
if (found_match) {
Module *m = design->addModule(stringf("\\pmtest_%s_%s_%05d",
pmclass, pattern, modcnt++));
log("Creating module %s with %d cells.\n", log_id(m), cellcnt);
log("Creating module %s with %d cells.\n", m, cellcnt);
mod->cloneInto(m);
pmtest_addports(m);
mods.push_back(m);
@ -126,7 +126,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
}
Module *m = design->addModule(stringf("\\pmtest_%s_%s", pmclass, pattern));
log("Creating module %s with %d cells.\n", log_id(m), GetSize(mods));
log("Creating module %s with %d cells.\n", m, GetSize(mods));
for (auto mod : mods) {
Cell *c = m->addCell(mod->name, mod->name);
for (auto port : mod->ports) {

16
passes/pmgen/test_pmgen.cc
View file

@ -37,7 +37,7 @@ void reduce_chain(test_pmgen_pm &pm)
if (ud.longest_chain.empty())
return;
log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), st.first->type.unescape());
SigSpec A;
SigSpec Y = ud.longest_chain.front().first->getPort(ID::Y);
@ -51,7 +51,7 @@ void reduce_chain(test_pmgen_pm &pm)
} else {
A.append(cell->getPort(it.second == ID::A ? ID::B : ID::A));
}
log(" %s\n", log_id(cell));
log(" %s\n", cell);
pm.autoremove(cell);
}
@ -66,7 +66,7 @@ void reduce_chain(test_pmgen_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
log(" -> %s (%s)\n", c, c->type.unescape());
}
void reduce_tree(test_pmgen_pm &pm)
@ -81,8 +81,8 @@ void reduce_tree(test_pmgen_pm &pm)
SigSpec Y = st.first->getPort(ID::Y);
pm.autoremove(st.first);
log("Found %s tree with %d leaves for %s (%s).\n", log_id(st.first->type),
GetSize(A), log_signal(Y), log_id(st.first));
log("Found %s tree with %d leaves for %s (%s).\n", st.first->type.unescape(),
GetSize(A), log_signal(Y), st.first);
Cell *c;
@ -95,7 +95,7 @@ void reduce_tree(test_pmgen_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
log(" -> %s (%s)\n", c, c->type.unescape());
}
void opt_eqpmux(test_pmgen_pm &pm)
@ -109,11 +109,11 @@ void opt_eqpmux(test_pmgen_pm &pm)
SigSpec NE = st.pmux->getPort(ID::B).extract(st.pmux_slice_ne*width, width);
log("Found eqpmux circuit driving %s (eq=%s, ne=%s, pmux=%s).\n",
log_signal(Y), log_id(st.eq), log_id(st.ne), log_id(st.pmux));
log_signal(Y), st.eq, st.ne, st.pmux);
pm.autoremove(st.pmux);
Cell *c = pm.module->addMux(NEW_ID, NE, EQ, st.eq->getPort(ID::Y), Y);
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
log(" -> %s (%s)\n", c, c->type.unescape());
}
struct TestPmgenPass : public Pass {