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Refactored uses of log_id()

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Codexplorer 2026-05-08 00:01:43 -07:00
parent 89d83a3410
commit e41b969da2
186 changed files with 1219 additions and 1220 deletions
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10
passes/hierarchy/flatten.cc
View file

@ -149,7 +149,7 @@ struct FlattenWorker
hier_wire->attributes.erase(ID::hierconn);
if (GetSize(hier_wire) < GetSize(tpl_wire)) {
log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n",
log_id(module), log_id(hier_wire), log_id(tpl), log_id(tpl_wire), log_id(module), log_id(cell));
module, hier_wire, tpl, tpl_wire, module, cell);
hier_wire->width = GetSize(tpl_wire);
}
new_wire = hier_wire;
@ -261,7 +261,7 @@ struct FlattenWorker
if (sigmap(new_conn.first).has_const())
log_error("Cell port %s.%s.%s is driving constant bits: %s <= %s\n",
log_id(module), log_id(cell), log_id(port_it.first), log_signal(new_conn.first), log_signal(new_conn.second));
module, cell, port_it.first.unescape(), log_signal(new_conn.first), log_signal(new_conn.second));
module->connect(new_conn);
sigmap.add(new_conn.first, new_conn.second);
@ -316,12 +316,12 @@ struct FlattenWorker
continue;
if (cell->get_bool_attribute(ID::keep_hierarchy) || tpl->get_bool_attribute(ID::keep_hierarchy)) {
log("Keeping %s.%s (found keep_hierarchy attribute).\n", log_id(module), log_id(cell));
log("Keeping %s.%s (found keep_hierarchy attribute).\n", module, cell);
used_modules.insert(tpl);
continue;
}
log_debug("Flattening %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
log_debug("Flattening %s.%s (%s).\n", module, cell, cell->type.unescape());
// If a design is fully selected and has a top module defined, topological sorting ensures that all cells
// added during flattening are black boxes, and flattening is finished in one pass. However, when flattening
// individual modules, this isn't the case, and the newly added cells might have to be flattened further.
@ -443,7 +443,7 @@ struct FlattenPass : public Pass {
if (cleanup && top != nullptr)
for (auto module : design->modules().to_vector())
if (!used_modules[module] && !module->get_blackbox_attribute(worker.ignore_wb)) {
log("Deleting now unused module %s.\n", log_id(module));
log("Deleting now unused module %s.\n", module);
design->remove(module);
}

40
passes/hierarchy/hierarchy.cc
View file

@ -225,7 +225,7 @@ struct IFExpander
// about it and don't set has_interfaces_not_found (to avoid a
// loop).
log_warning("Could not find interface instance for `%s' in `%s'\n",
log_id(interface_name), log_id(&module));
interface_name.unescape(), &module);
}
// Handle an interface connection from the module
@ -268,12 +268,12 @@ struct IFExpander
// Go over all wires in interface, and add replacements to lists.
for (auto mod_wire : mod_replace_ports->wires()) {
std::string signal_name1 = conn_name.str() + "." + log_id(mod_wire->name);
std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire);
std::string signal_name1 = conn_name.str() + "." + mod_wire->name.unescape();
std::string signal_name2 = interface_name.str() + "." + mod_wire->name.unescape();
connections_to_add_name.push_back(RTLIL::IdString(signal_name1));
if(module.wire(signal_name2) == nullptr) {
log_error("Could not find signal '%s' in '%s'\n",
signal_name2.c_str(), log_id(module.name));
signal_name2.c_str(), module.name.unescape());
}
else {
RTLIL::Wire *wire_in_parent = module.wire(signal_name2);
@ -432,7 +432,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
if (id <= 0 || id > GetSize(mod.ports))
log_error("Module `%s' referenced in module `%s' in cell `%s' "
"has only %d ports, requested port %d.\n",
log_id(cell.type), log_id(&module), log_id(&cell),
cell.type.unescape(), &module, &cell,
GetSize(mod.ports), id);
continue;
}
@ -441,8 +441,8 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
if (!wire || wire->port_id == 0) {
log_error("Module `%s' referenced in module `%s' in cell `%s' "
"does not have a port named '%s'.\n",
log_id(cell.type), log_id(&module), log_id(&cell),
log_id(conn.first));
cell.type.unescape(), &module, &cell,
conn.first.unescape());
}
}
for (auto &param : cell.parameters) {
@ -450,7 +450,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
if (id <= 0 || id > GetSize(mod.avail_parameters))
log_error("Module `%s' referenced in module `%s' in cell `%s' "
"has only %d parameters, requested parameter %d.\n",
log_id(cell.type), log_id(&module), log_id(&cell),
cell.type.unescape(), &module, &cell,
GetSize(mod.avail_parameters), id);
continue;
}
@ -460,8 +460,8 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
strchr(param.first.c_str(), '.') == NULL) {
log_error("Module `%s' referenced in module `%s' in cell `%s' "
"does not have a parameter named '%s'.\n",
log_id(cell.type), log_id(&module), log_id(&cell),
log_id(param.first));
cell.type.unescape(), &module, &cell,
param.first.unescape());
}
}
}
@ -1036,7 +1036,7 @@ struct HierarchyPass : public Pass {
if (top_mod == nullptr)
for (auto mod : design->modules())
if (mod->get_bool_attribute(ID::top)) {
log("Attribute `top' found on module `%s'. Setting top module to %s.\n", log_id(mod), log_id(mod));
log("Attribute `top' found on module `%s'. Setting top module to %s.\n", mod, mod);
top_mod = mod;
}
@ -1057,12 +1057,12 @@ struct HierarchyPass : public Pass {
dict<Module*, int> db;
for (Module *mod : design->selected_modules()) {
int score = find_top_mod_score(design, mod, db);
log("root of %3d design levels: %-20s\n", score, log_id(mod));
log("root of %3d design levels: %-20s\n", score, mod);
if (!top_mod || score > db[top_mod])
top_mod = mod;
}
if (top_mod != nullptr)
log("Automatically selected %s as design top module.\n", log_id(top_mod));
log("Automatically selected %s as design top module.\n", top_mod);
}
if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) {
@ -1162,7 +1162,7 @@ struct HierarchyPass : public Pass {
std::map<RTLIL::Module*, bool> cache;
for (auto mod : design->modules())
if (set_keep_print(cache, mod)) {
log("Module %s directly or indirectly displays text -> setting \"keep\" attribute.\n", log_id(mod));
log("Module %s directly or indirectly displays text -> setting \"keep\" attribute.\n", mod);
mod->set_bool_attribute(ID::keep);
}
}
@ -1171,7 +1171,7 @@ struct HierarchyPass : public Pass {
std::map<RTLIL::Module*, bool> cache;
for (auto mod : design->modules())
if (set_keep_assert(cache, mod)) {
log("Module %s directly or indirectly contains formal properties -> setting \"keep\" attribute.\n", log_id(mod));
log("Module %s directly or indirectly contains formal properties -> setting \"keep\" attribute.\n", mod);
mod->set_bool_attribute(ID::keep);
}
}
@ -1190,7 +1190,7 @@ struct HierarchyPass : public Pass {
src += ": ";
log_error("%sProperty `%s' in module `%s' uses unsupported SVA constructs. See frontend warnings for details, run `chformal -remove a:unsupported_sva' to ignore.\n",
src, log_id(cell->name), log_id(mod->name));
src, cell->name.unescape(), mod->name.unescape());
}
}
}
@ -1499,7 +1499,7 @@ struct HierarchyPass : public Pass {
bool resize_widths = !keep_portwidths && GetSize(w) != GetSize(conn.second);
if (resize_widths && verific_mod && boxed_params)
log_debug("Ignoring width mismatch on %s.%s.%s from verific, is port width parametrizable?\n",
log_id(module), log_id(cell), log_id(conn.first)
module, cell, conn.first.unescape()
);
else if (resize_widths) {
if (GetSize(w) < GetSize(conn.second))
@ -1523,14 +1523,14 @@ struct HierarchyPass : public Pass {
}
if (!conn.second.is_fully_const() || !w->port_input || w->port_output)
log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell),
log_id(conn.first), GetSize(conn.second), GetSize(sig));
log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", module, cell,
conn.first.unescape(), GetSize(conn.second), GetSize(sig));
cell->setPort(conn.first, sig);
}
if (w->port_output && !w->port_input && sig.has_const())
log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n",
log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig));
module, cell, conn.first.unescape(), cell->type.unescape(), log_signal(sig));
}
}
}

8
passes/hierarchy/keep_hierarchy.cc
View file

@ -42,7 +42,7 @@ struct ThresholdHierarchyKeeping {
return 0;
if (module->get_blackbox_attribute())
log_error("Missing cost information on instanced blackbox %s\n", log_id(module));
log_error("Missing cost information on instanced blackbox %s\n", module);
if (done.count(module))
return done.at(module);
@ -61,13 +61,13 @@ struct ThresholdHierarchyKeeping {
RTLIL::Module *submodule = design->module(cell->type);
if (!submodule)
log_error("Hierarchy contains unknown module '%s' (instanced as %s in %s)\n",
log_id(cell->type), log_id(cell), log_id(module));
cell->type.unescape(), cell, module);
size += visit(submodule);
}
}
if (size > threshold) {
log("Keeping %s (estimated size above threshold: %" PRIu64 " > %" PRIu64 ").\n", log_id(module), size, threshold);
log("Keeping %s (estimated size above threshold: %" PRIu64 " > %" PRIu64 ").\n", module, size, threshold);
module->set_bool_attribute(ID::keep_hierarchy);
size = 0;
}
@ -124,7 +124,7 @@ struct KeepHierarchyPass : public Pass {
worker.visit(top);
} else {
for (auto module : design->selected_modules()) {
log("Marking %s.\n", log_id(module));
log("Marking %s.\n", module);
module->set_bool_attribute(ID::keep_hierarchy);
}
}

6
passes/hierarchy/uniquify.cc
View file

@ -71,7 +71,7 @@ struct UniquifyPass : public Pass {
for (auto cell : module->selected_cells())
{
Module *tmod = design->module(cell->type);
IdString newname = module->name.str() + "." + log_id(cell->name);
IdString newname = module->name.str() + "." + cell->name.unescape();
if (tmod == nullptr)
continue;
@ -82,14 +82,14 @@ struct UniquifyPass : public Pass {
if (tmod->get_bool_attribute(ID::unique) && newname == tmod->name)
continue;
log("Creating module %s from %s.\n", log_id(newname), log_id(tmod));
log("Creating module %s from %s.\n", newname.unescape(), tmod);
auto smod = tmod->clone();
smod->name = newname;
cell->type = newname;
smod->set_bool_attribute(ID::unique);
if (smod->attributes.count(ID::hdlname) == 0)
smod->attributes[ID::hdlname] = string(log_id(tmod->name));
smod->attributes[ID::hdlname] = string(tmod->name.unescape());
design->add(smod);
did_something = true;