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Refactored uses of log_id()

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Codexplorer 2026-05-08 00:01:43 -07:00
parent 89d83a3410
commit e41b969da2
186 changed files with 1219 additions and 1220 deletions
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10
passes/fsm/fsm_detect.cc
View file

@ -132,7 +132,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
if (wire->width <= 1) {
if (has_fsm_encoding_attr) {
log_warning("Removing fsm_encoding attribute from 1-bit net: %s.%s\n", log_id(wire->module), log_id(wire));
log_warning("Removing fsm_encoding attribute from 1-bit net: %s.%s\n", wire->module, wire);
wire->attributes.erase(ID::fsm_encoding);
}
return;
@ -230,23 +230,23 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
warnings.push_back("FSM seems to be self-resetting. Possible simulation-synthesis mismatch!\n");
if (!warnings.empty()) {
string warnmsg = stringf("Regarding the user-specified fsm_encoding attribute on %s.%s:\n", log_id(wire->module), log_id(wire));
string warnmsg = stringf("Regarding the user-specified fsm_encoding attribute on %s.%s:\n", wire->module, wire);
for (auto w : warnings) warnmsg += " " + w;
log_warning("%s", warnmsg);
} else {
log("FSM state register %s.%s already has fsm_encoding attribute.\n", log_id(wire->module), log_id(wire));
log("FSM state register %s.%s already has fsm_encoding attribute.\n", wire->module, wire);
}
}
else
if (looks_like_state_reg && looks_like_good_state_reg && !has_init_attr && !is_module_port && !is_self_resetting)
{
log("Found FSM state register %s.%s.\n", log_id(wire->module), log_id(wire));
log("Found FSM state register %s.%s.\n", wire->module, wire);
wire->attributes[ID::fsm_encoding] = RTLIL::Const("auto");
}
else
if (looks_like_state_reg)
{
log("Not marking %s.%s as FSM state register:\n", log_id(wire->module), log_id(wire));
log("Not marking %s.%s as FSM state register:\n", wire->module, wire);
if (is_module_port)
log(" Register is connected to module port.\n");

6
passes/fsm/fsm_expand.cc
View file

@ -189,12 +189,12 @@ struct FsmExpand
if (GetSize(input_sig) > 10)
log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n",
log_id(cell->module), log_id(cell), log_id(cell->type),
GetSize(input_sig), log_id(fsm_cell->module), log_id(fsm_cell));
cell->module, cell, cell->type.unescape(),
GetSize(input_sig), fsm_cell->module, fsm_cell);
if (GetSize(fsm_data.transition_table) > 10000)
log_warning("Transition table for FSM %s.%s already has %d rows, merging more cells "
"into this FSM might be problematic.\n", log_id(fsm_cell->module), log_id(fsm_cell),
"into this FSM might be problematic.\n", fsm_cell->module, fsm_cell,
GetSize(fsm_data.transition_table));
std::vector<FsmData::transition_t> new_transition_table;

2
passes/fsm/fsm_export.cc
View file

@ -64,7 +64,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
kiss_name.assign(attr_it->second.decode_string());
}
else {
kiss_name.assign(log_id(module) + std::string("-") + log_id(cell) + ".kiss2");
kiss_name.assign(module->name.unescape() + std::string("-") + cell->name.unescape() + ".kiss2");
}
log("\n");

2
passes/fsm/fsm_info.cc
View file

@ -50,7 +50,7 @@ struct FsmInfoPass : public Pass {
for (auto cell : mod->selected_cells())
if (cell->type == ID($fsm)) {
log("\n");
log("FSM `%s' from module `%s':\n", log_id(cell), log_id(mod));
log("FSM `%s' from module `%s':\n", cell, mod);
FsmData fsm_data;
fsm_data.copy_from_cell(cell);
fsm_data.log_info(cell);

2
passes/fsm/fsm_recode.cc
View file

@ -96,7 +96,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
log_error("FSM encoding `%s' is not supported!\n", encoding);
if (encfile)
fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str());
fprintf(encfile, ".fsm %s %s\n", module, RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str());
int state_idx_counter = fsm_data.reset_state >= 0 ? 1 : 0;
for (int i = 0; i < int(fsm_data.state_table.size()); i++)