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https://github.com/YosysHQ/yosys
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Refactored uses of log_id()
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parent
89d83a3410
commit
e41b969da2
186 changed files with 1219 additions and 1220 deletions
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@ -38,9 +38,9 @@ public:
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[[noreturn]]
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void formatted_error(std::string err)
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{
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log("Module A: %s\n", log_id(mod_a->name));
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log("Module A: %s\n", mod_a->name.unescape());
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log_module(mod_a, " ");
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log("Module B: %s\n", log_id(mod_b->name));
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log("Module B: %s\n", mod_b->name.unescape());
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log_module(mod_b, " ");
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log_cmd_error("Designs are different: %s\n", err);
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}
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@ -68,20 +68,20 @@ public:
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{
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for (const auto &it : a->attributes) {
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if (b->attributes.count(it.first) == 0)
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return "missing attribute " + std::string(log_id(it.first)) + " in second design";
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return "missing attribute " + std::string(it.first.unescape()) + " in second design";
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if (it.second != b->attributes.at(it.first))
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return "attribute " + std::string(log_id(it.first)) + " mismatch: " + log_const(it.second) + " != " + log_const(b->attributes.at(it.first));
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return "attribute " + std::string(it.first.unescape()) + " mismatch: " + log_const(it.second) + " != " + log_const(b->attributes.at(it.first));
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}
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for (const auto &it : b->attributes)
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if (a->attributes.count(it.first) == 0)
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return "missing attribute " + std::string(log_id(it.first)) + " in first design";
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return "missing attribute " + std::string(it.first.unescape()) + " in first design";
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return "";
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}
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std::string compare_wires(const RTLIL::Wire *a, const RTLIL::Wire *b)
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{
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if (a->name != b->name)
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return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
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return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape();
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if (a->width != b->width)
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return "width mismatch: " + std::to_string(a->width) + " != " + std::to_string(b->width);
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if (a->start_offset != b->start_offset)
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@ -105,19 +105,19 @@ public:
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{
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for (const auto &it : mod_a->wires_) {
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if (mod_b->wires_.count(it.first) == 0)
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error("Module %s missing wire %s in second design.\n", log_id(mod_a->name), log_id(it.first));
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error("Module %s missing wire %s in second design.\n", mod_a->name.unescape(), it.first.unescape());
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if (std::string mismatch = compare_wires(it.second, mod_b->wires_.at(it.first)); !mismatch.empty())
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error("Module %s wire %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
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error("Module %s wire %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch);
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}
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for (const auto &it : mod_b->wires_)
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if (mod_a->wires_.count(it.first) == 0)
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error("Module %s missing wire %s in first design.\n", log_id(mod_b->name), log_id(it.first));
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error("Module %s missing wire %s in first design.\n", mod_b->name.unescape(), it.first.unescape());
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}
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std::string compare_memories(const RTLIL::Memory *a, const RTLIL::Memory *b)
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{
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if (a->name != b->name)
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return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
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return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape();
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if (a->width != b->width)
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return "width mismatch: " + std::to_string(a->width) + " != " + std::to_string(b->width);
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if (a->start_offset != b->start_offset)
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@ -132,31 +132,31 @@ public:
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std::string compare_cells(const RTLIL::Cell *a, const RTLIL::Cell *b)
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{
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if (a->name != b->name)
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return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
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return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape();
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if (a->type != b->type)
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return "type mismatch: " + std::string(log_id(a->type)) + " != " + log_id(b->type);
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return "type mismatch: " + std::string(a->type.unescape()) + " != " + b->type.unescape();
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if (std::string mismatch = compare_attributes(a, b); !mismatch.empty())
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return mismatch;
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for (const auto &it : a->parameters) {
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if (b->parameters.count(it.first) == 0)
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return "parameter mismatch: missing parameter " + std::string(log_id(it.first)) + " in second design";
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return "parameter mismatch: missing parameter " + std::string(it.first.unescape()) + " in second design";
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if (it.second != b->parameters.at(it.first))
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return "parameter mismatch: " + std::string(log_id(it.first)) + " mismatch: " + log_const(it.second) + " != " + log_const(b->parameters.at(it.first));
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return "parameter mismatch: " + std::string(it.first.unescape()) + " mismatch: " + log_const(it.second) + " != " + log_const(b->parameters.at(it.first));
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}
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for (const auto &it : b->parameters)
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if (a->parameters.count(it.first) == 0)
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return "parameter mismatch: missing parameter " + std::string(log_id(it.first)) + " in first design";
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return "parameter mismatch: missing parameter " + std::string(it.first.unescape()) + " in first design";
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for (const auto &it : a->connections()) {
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if (b->connections().count(it.first) == 0)
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return "connection mismatch: missing connection " + std::string(log_id(it.first)) + " in second design";
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return "connection mismatch: missing connection " + std::string(it.first.unescape()) + " in second design";
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if (!compare_sigspec(it.second, b->connections().at(it.first)))
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return "connection " + std::string(log_id(it.first)) + " mismatch: " + log_signal(it.second) + " != " + log_signal(b->connections().at(it.first));
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return "connection " + std::string(it.first.unescape()) + " mismatch: " + log_signal(it.second) + " != " + log_signal(b->connections().at(it.first));
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}
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for (const auto &it : b->connections())
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if (a->connections().count(it.first) == 0)
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return "connection mismatch: missing connection " + std::string(log_id(it.first)) + " in first design";
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return "connection mismatch: missing connection " + std::string(it.first.unescape()) + " in first design";
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return "";
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}
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@ -165,26 +165,26 @@ public:
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{
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for (const auto &it : mod_a->cells_) {
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if (mod_b->cells_.count(it.first) == 0)
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error("Module %s missing cell %s in second design.\n", log_id(mod_a->name), log_id(it.first));
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error("Module %s missing cell %s in second design.\n", mod_a->name.unescape(), it.first.unescape());
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if (std::string mismatch = compare_cells(it.second, mod_b->cells_.at(it.first)); !mismatch.empty())
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error("Module %s cell %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
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error("Module %s cell %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch);
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}
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for (const auto &it : mod_b->cells_)
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if (mod_a->cells_.count(it.first) == 0)
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error("Module %s missing cell %s in first design.\n", log_id(mod_b->name), log_id(it.first));
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error("Module %s missing cell %s in first design.\n", mod_b->name.unescape(), it.first.unescape());
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}
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void check_memories()
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{
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for (const auto &it : mod_a->memories) {
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if (mod_b->memories.count(it.first) == 0)
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error("Module %s missing memory %s in second design.\n", log_id(mod_a->name), log_id(it.first));
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error("Module %s missing memory %s in second design.\n", mod_a->name.unescape(), it.first.unescape());
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if (std::string mismatch = compare_memories(it.second, mod_b->memories.at(it.first)); !mismatch.empty())
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error("Module %s memory %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
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error("Module %s memory %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch);
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}
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for (const auto &it : mod_b->memories)
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if (mod_a->memories.count(it.first) == 0)
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error("Module %s missing memory %s in first design.\n", log_id(mod_b->name), log_id(it.first));
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error("Module %s missing memory %s in first design.\n", mod_b->name.unescape(), it.first.unescape());
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}
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std::string compare_case_rules(const RTLIL::CaseRule *a, const RTLIL::CaseRule *b)
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@ -251,7 +251,7 @@ public:
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const auto &ma = a->mem_write_actions[i];
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const auto &mb = b->mem_write_actions[i];
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if (ma.memid != mb.memid)
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return "mem_write_actions " + std::to_string(i) + " memid mismatch: " + log_id(ma.memid) + " != " + log_id(mb.memid);
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return "mem_write_actions " + std::to_string(i) + " memid mismatch: " + ma.memid.unescape() + " != " + mb.memid.unescape();
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if (!compare_sigspec(ma.address, mb.address))
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return "mem_write_actions " + std::to_string(i) + " address mismatch: " + log_signal(ma.address) + " != " + log_signal(mb.address);
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if (!compare_sigspec(ma.data, mb.data))
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@ -268,7 +268,7 @@ public:
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std::string compare_processes(const RTLIL::Process *a, const RTLIL::Process *b)
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{
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if (a->name != b->name) return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
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if (a->name != b->name) return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape();
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if (std::string mismatch = compare_attributes(a, b); !mismatch.empty())
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return mismatch;
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if (std::string mismatch = compare_case_rules(&a->root_case, &b->root_case); !mismatch.empty())
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@ -285,13 +285,13 @@ public:
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{
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for (auto &it : mod_a->processes) {
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if (mod_b->processes.count(it.first) == 0)
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error("Module %s missing process %s in second design.\n", log_id(mod_a->name), log_id(it.first));
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error("Module %s missing process %s in second design.\n", mod_a->name.unescape(), it.first.unescape());
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if (std::string mismatch = compare_processes(it.second, mod_b->processes.at(it.first)); !mismatch.empty())
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error("Module %s process %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch.c_str());
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error("Module %s process %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch.c_str());
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}
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for (auto &it : mod_b->processes)
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if (mod_a->processes.count(it.first) == 0)
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error("Module %s missing process %s in first design.\n", log_id(mod_b->name), log_id(it.first));
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error("Module %s missing process %s in first design.\n", mod_b->name.unescape(), it.first.unescape());
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}
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void check_connections()
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@ -299,13 +299,13 @@ public:
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const auto &conns_a = mod_a->connections();
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const auto &conns_b = mod_b->connections();
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if (conns_a.size() != conns_b.size()) {
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error("Module %s connection count differs: %zu != %zu\n", log_id(mod_a->name), conns_a.size(), conns_b.size());
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error("Module %s connection count differs: %zu != %zu\n", mod_a->name.unescape(), conns_a.size(), conns_b.size());
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} else {
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for (size_t i = 0; i < conns_a.size(); i++) {
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if (!compare_sigspec(conns_a[i].first, conns_b[i].first))
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error("Module %s connection %zu LHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first));
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error("Module %s connection %zu LHS %s != %s.\n", mod_a->name.unescape(), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first));
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if (!compare_sigspec(conns_a[i].second, conns_b[i].second))
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error("Module %s connection %zu RHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second));
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error("Module %s connection %zu RHS %s != %s.\n", mod_a->name.unescape(), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second));
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}
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}
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}
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@ -313,9 +313,9 @@ public:
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void check()
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{
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if (mod_a->name != mod_b->name)
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error("Modules have different names: %s != %s\n", log_id(mod_a->name), log_id(mod_b->name));
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error("Modules have different names: %s != %s\n", mod_a->name.unescape(), mod_b->name.unescape());
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if (std::string mismatch = compare_attributes(mod_a, mod_b); !mismatch.empty())
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error("Module %s %s.\n", log_id(mod_a->name), mismatch);
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error("Module %s %s.\n", mod_a->name.unescape(), mismatch);
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check_wires();
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check_cells();
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check_memories();
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@ -349,7 +349,7 @@ struct DesignEqualPass : public Pass {
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for (auto &it : design->modules_) {
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RTLIL::Module *mod = it.second;
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if (!other->has(mod->name))
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log_error("Second design missing module %s.\n", log_id(mod->name));
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log_error("Second design missing module %s.\n", mod->name.unescape());
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ModuleComparator cmp(mod, other->module(mod->name));
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cmp.check();
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@ -357,7 +357,7 @@ struct DesignEqualPass : public Pass {
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for (auto &it : other->modules_) {
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RTLIL::Module *mod = it.second;
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if (!design->has(mod->name))
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log_error("First design missing module %s.\n", log_id(mod->name));
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log_error("First design missing module %s.\n", mod->name.unescape());
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}
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log("Designs are identical.\n");
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