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https://github.com/YosysHQ/yosys
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Refactored uses of log_id()
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parent
89d83a3410
commit
e41b969da2
186 changed files with 1219 additions and 1220 deletions
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@ -212,7 +212,7 @@ struct BugpointPass : public Pass {
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if (index++ == seed)
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{
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log_header(design, "Trying to remove module %s.\n", log_id(module));
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log_header(design, "Trying to remove module %s.\n", module);
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removed_module = module;
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break;
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}
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@ -242,7 +242,7 @@ struct BugpointPass : public Pass {
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if (index++ == seed)
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{
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log_header(design, "Trying to remove module port %s.\n", log_id(wire));
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log_header(design, "Trying to remove module port %s.\n", wire);
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wire->port_input = wire->port_output = false;
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mod->fixup_ports();
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return design_copy;
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@ -265,7 +265,7 @@ struct BugpointPass : public Pass {
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if (index++ == seed)
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{
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log_header(design, "Trying to remove cell %s.%s.\n", log_id(mod), log_id(cell));
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log_header(design, "Trying to remove cell %s.%s.\n", mod, cell);
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removed_cell = cell;
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break;
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}
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@ -296,7 +296,7 @@ struct BugpointPass : public Pass {
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if (index++ == seed)
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{
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log_header(design, "Trying to remove cell port %s.%s.%s.\n", log_id(mod), log_id(cell), log_id(it.first));
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log_header(design, "Trying to remove cell port %s.%s.%s.\n", mod, cell, it.first.unescape());
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RTLIL::SigSpec port_x(State::Sx, port.size());
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cell->unsetPort(it.first);
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cell->setPort(it.first, port_x);
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@ -305,7 +305,7 @@ struct BugpointPass : public Pass {
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if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed)
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{
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log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", log_id(mod), log_id(cell), log_id(it.first));
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log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", mod, cell, it.first.unescape());
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RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
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wire->set_bool_attribute(ID($bugpoint));
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wire->port_input = cell->input(it.first);
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@ -334,7 +334,7 @@ struct BugpointPass : public Pass {
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if (index++ == seed)
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{
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log_header(design, "Trying to remove process %s.%s.\n", log_id(mod), log_id(process.first));
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log_header(design, "Trying to remove process %s.%s.\n", mod, process.first.unescape());
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removed_process = process.second;
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break;
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}
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@ -363,7 +363,7 @@ struct BugpointPass : public Pass {
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{
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if (index++ == seed)
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{
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log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->first), log_signal(it->second), log_id(mod), log_id(pr.first));
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log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->first), log_signal(it->second), mod, pr.first.unescape());
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cs->actions.erase(it);
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return design_copy;
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}
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@ -389,7 +389,7 @@ struct BugpointPass : public Pass {
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{
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if (index++ == seed)
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{
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log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->first), log_signal(it->second), log_id(mod), log_id(pr.first));
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log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->first), log_signal(it->second), mod, pr.first.unescape());
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sy->actions.erase(it);
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return design_copy;
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}
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@ -399,7 +399,7 @@ struct BugpointPass : public Pass {
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{
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if (index++ == seed)
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{
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log_header(design, "Trying to remove sync %s memwr %s %s %s %s in %s.%s.\n", log_signal(sy->signal), log_id(it->memid), log_signal(it->address), log_signal(it->data), log_signal(it->enable), log_id(mod), log_id(pr.first));
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log_header(design, "Trying to remove sync %s memwr %s %s %s %s in %s.%s.\n", log_signal(sy->signal), it->memid.unescape(), log_signal(it->address), log_signal(it->data), log_signal(it->enable), mod, pr.first.unescape());
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sy->mem_write_actions.erase(it);
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// Remove the bit for removed action from other actions' priority masks.
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for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) {
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@ -437,7 +437,7 @@ struct BugpointPass : public Pass {
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if (index++ == seed)
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{
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log_header(design, "Trying to remove wire %s.%s.\n", log_id(mod), log_id(wire));
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log_header(design, "Trying to remove wire %s.%s.\n", mod, wire);
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removed_wire = wire;
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break;
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}
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