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Refactored uses of log_id()

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Codexplorer 2026-05-08 00:01:43 -07:00
parent 89d83a3410
commit e41b969da2
186 changed files with 1219 additions and 1220 deletions
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2
kernel/cost.cc
View file

@ -210,6 +210,6 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
// TODO: $fsm
// ignored: $pow $memrd $memwr $meminit (and v2 counterparts)
log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters));
log_warning("Can't determine cost of %s cell (%d parameters).\n", cell->type.unescape(), GetSize(cell->parameters));
return 1;
}

6
kernel/drivertools.cc
View file

@ -866,7 +866,7 @@ DriveSpec DriverMap::operator()(DriveSpec spec)
std::string log_signal(DriveChunkWire const &chunk)
{
const char *id = log_id(chunk.wire->name);
std::string id = chunk.wire->name.unescape();
if (chunk.is_whole())
return id;
if (chunk.width == 1)
@ -877,8 +877,8 @@ std::string log_signal(DriveChunkWire const &chunk)
std::string log_signal(DriveChunkPort const &chunk)
{
const char *cell_id = log_id(chunk.cell->name);
const char *port_id = log_id(chunk.port);
std::string cell_id = chunk.cell->name.unescape();
std::string port_id = chunk.port.unescape();
if (chunk.is_whole())
return stringf("%s <%s>", cell_id, port_id);
if (chunk.width == 1)

2
kernel/ff.cc
View file

@ -792,7 +792,7 @@ void FfData::flip_bits(const pool<int> &bits) {
Wire *new_q = module->addWire(NEW_ID, width);
if (has_sr && cell) {
log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", log_id(module->name), log_id(cell->name), log_id(cell->type));
log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", module->name.unescape(), cell->name.unescape(), cell->type.unescape());
}
if (is_fine) {

8
kernel/functional.cc
View file

@ -572,7 +572,7 @@ private:
const auto &wr = mem->wr_ports[i];
if (wr.clk_enable)
log_error("Write port %zd of memory %s.%s is clocked. This is not supported by the functional backend. "
"Call async2sync or clk2fflogic to avoid this error.\n", i, log_id(mem->module), log_id(mem->memid));
"Call async2sync or clk2fflogic to avoid this error.\n", i, mem->module, mem->memid.unescape());
Node en = enqueue(driver_map(DriveSpec(wr.en)));
Node addr = enqueue(driver_map(DriveSpec(wr.addr)));
Node new_data = enqueue(driver_map(DriveSpec(wr.data)));
@ -582,12 +582,12 @@ private:
}
if (mem->rd_ports.empty())
log_error("Memory %s.%s has no read ports. This is not supported by the functional backend. "
"Call opt_clean to remove it.", log_id(mem->module), log_id(mem->memid));
"Call opt_clean to remove it.", mem->module, mem->memid.unescape());
for (size_t i = 0; i < mem->rd_ports.size(); i++) {
const auto &rd = mem->rd_ports[i];
if (rd.clk_enable)
log_error("Read port %zd of memory %s.%s is clocked. This is not supported by the functional backend. "
"Call memory_nordff to avoid this error.\n", i, log_id(mem->module), log_id(mem->memid));
"Call memory_nordff to avoid this error.\n", i, mem->module, mem->memid.unescape());
Node addr = enqueue(driver_map(DriveSpec(rd.addr)));
read_results.push_back(factory.memory_read(node, addr));
}
@ -609,7 +609,7 @@ private:
FfData ff(&ff_initvals, cell);
if (!ff.has_gclk)
log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. "
"Call async2sync or clk2fflogic to avoid this error.\n", log_id(cell->type), log_id(cell));
"Call async2sync or clk2fflogic to avoid this error.\n", cell->type.unescape(), cell);
auto &state = factory.add_state(ff.name, ID($state), Sort(ff.width));
Node q_value = factory.value(state);
factory.suggest_name(q_value, ff.name);

2
kernel/log.cc
View file

@ -586,7 +586,7 @@ void log_flush()
}
void log_dump_val_worker(RTLIL::IdString v) {
log("%s", log_id(v));
log("%s", v.unescape());
}
void log_dump_val_worker(RTLIL::SigSpec v) {

8
kernel/mem.cc
View file

@ -663,15 +663,15 @@ namespace {
auto addr = cell->getPort(ID::ADDR);
auto data = cell->getPort(ID::DATA);
if (!addr.is_fully_const())
log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), log_id(cell));
log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), cell);
if (!data.is_fully_const())
log_error("Non-constant data %s in memory initialization %s.\n", log_signal(data), log_id(cell));
log_error("Non-constant data %s in memory initialization %s.\n", log_signal(data), cell);
init.addr = addr.as_const();
init.data = data.as_const();
if (cell->type == ID($meminit_v2)) {
auto en = cell->getPort(ID::EN);
if (!en.is_fully_const())
log_error("Non-constant enable %s in memory initialization %s.\n", log_signal(en), log_id(cell));
log_error("Non-constant enable %s in memory initialization %s.\n", log_signal(en), cell);
init.en = en.as_const();
} else {
init.en = RTLIL::Const(State::S1, mem->width);
@ -1022,7 +1022,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
if (c)
log("Extracted %s FF from read port %d of %s.%s: %s\n", trans_use_addr ? "addr" : "data",
idx, log_id(module), log_id(memid), log_id(c));
idx, module, memid.unescape(), c);
port.en = State::S1;
port.clk = State::S0;

4
kernel/modtools.h
View file

@ -320,8 +320,8 @@ struct ModIndex : public RTLIL::Monitor
if (it.second.is_output)
log(" PRIMARY OUTPUT\n");
for (auto &port : it.second.ports)
log(" PORT: %s.%s[%d] (%s)\n", log_id(port.cell),
log_id(port.port), port.offset, log_id(port.cell->type));
log(" PORT: %s.%s[%d] (%s)\n", port.cell,
port.port.unescape(), port.offset, port.cell->type.unescape());
}
}
};

32
kernel/rtlil.cc
View file

@ -1226,7 +1226,7 @@ void RTLIL::Design::add(RTLIL::Module *module)
mon->notify_module_add(module);
if (yosys_xtrace) {
log("#X# New Module: %s\n", log_id(module));
log("#X# New Module: %s\n", module);
log_backtrace("-X- ", yosys_xtrace-1);
}
}
@ -1252,7 +1252,7 @@ RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
mon->notify_module_add(module);
if (yosys_xtrace) {
log("#X# New Module: %s\n", log_id(module));
log("#X# New Module: %s\n", module);
log_backtrace("-X- ", yosys_xtrace-1);
}
@ -1330,7 +1330,7 @@ void RTLIL::Design::remove(RTLIL::Module *module)
mon->notify_module_del(module);
if (yosys_xtrace) {
log("#X# Remove Module: %s\n", log_id(module));
log("#X# Remove Module: %s\n", module);
log_backtrace("-X- ", yosys_xtrace-1);
}
@ -1472,22 +1472,22 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartial
switch (boxes)
{
case RTLIL::SB_UNBOXED_WARN:
log_warning("Ignoring boxed module %s.\n", log_id(it.first));
log_warning("Ignoring boxed module %s.\n", it.first.unescape());
break;
case RTLIL::SB_EXCL_BB_WARN:
log_warning("Ignoring blackbox module %s.\n", log_id(it.first));
log_warning("Ignoring blackbox module %s.\n", it.first.unescape());
break;
case RTLIL::SB_UNBOXED_ERR:
log_error("Unsupported boxed module %s.\n", log_id(it.first));
log_error("Unsupported boxed module %s.\n", it.first.unescape());
break;
case RTLIL::SB_EXCL_BB_ERR:
log_error("Unsupported blackbox module %s.\n", log_id(it.first));
log_error("Unsupported blackbox module %s.\n", it.first.unescape());
break;
case RTLIL::SB_UNBOXED_CMDERR:
log_cmd_error("Unsupported boxed module %s.\n", log_id(it.first));
log_cmd_error("Unsupported boxed module %s.\n", it.first.unescape());
break;
case RTLIL::SB_EXCL_BB_CMDERR:
log_cmd_error("Unsupported blackbox module %s.\n", log_id(it.first));
log_cmd_error("Unsupported blackbox module %s.\n", it.first.unescape());
break;
default:
break;
@ -1496,13 +1496,13 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartial
switch(partials)
{
case RTLIL::SELECT_WHOLE_WARN:
log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
log_warning("Ignoring partially selected module %s.\n", it.first.unescape());
break;
case RTLIL::SELECT_WHOLE_ERR:
log_error("Unsupported partially selected module %s.\n", log_id(it.first));
log_error("Unsupported partially selected module %s.\n", it.first.unescape());
break;
case RTLIL::SELECT_WHOLE_CMDERR:
log_cmd_error("Unsupported partially selected module %s.\n", log_id(it.first));
log_cmd_error("Unsupported partially selected module %s.\n", it.first.unescape());
break;
default:
break;
@ -2796,14 +2796,14 @@ bool RTLIL::Module::has_processes() const
bool RTLIL::Module::has_memories_warn() const
{
if (!memories.empty())
log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", this);
return !memories.empty();
}
bool RTLIL::Module::has_processes_warn() const
{
if (!processes.empty())
log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", this);
return !processes.empty();
}
@ -3095,7 +3095,7 @@ void RTLIL::Module::connect(const RTLIL::SigSig &conn)
}
if (yosys_xtrace) {
log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", this, log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
log_backtrace("-X- ", yosys_xtrace-1);
}
@ -3118,7 +3118,7 @@ void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
mon->notify_connect(this, new_conn);
if (yosys_xtrace) {
log("#X# New connections vector in %s:\n", log_id(this));
log("#X# New connections vector in %s:\n", this);
for (auto &conn: new_conn)
log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
log_backtrace("-X- ", yosys_xtrace-1);

12
kernel/rtlil_bufnorm.cc
View file

@ -146,7 +146,7 @@ void RTLIL::Module::bufNormalize()
// already enqueued or becomes reachable when denormalizing $buf or
// $connect cells.
auto enqueue_cell_port = [&](Cell *cell, IdString port) {
xlog("processing cell port %s.%s\n", log_id(cell), log_id(port));
xlog("processing cell port %s.%s\n", cell, port.unescape());
// An empty cell type means the cell got removed
if (cell->type.empty())
@ -270,7 +270,7 @@ void RTLIL::Module::bufNormalize()
// normalized mode).
while (wire_queue_pos < GetSize(wire_queue_entries)) {
auto wire = wire_queue_entries[wire_queue_pos++];
xlog("processing wire %s\n", log_id(wire));
xlog("processing wire %s\n", wire);
if (wire->driverCell_) {
Cell *cell = wire->driverCell_;
@ -287,7 +287,7 @@ void RTLIL::Module::bufNormalize()
log_assert(connect_cell->type == ID($connect));
SigSpec const &sig_a = connect_cell->getPort(ID::A);
SigSpec const &sig_b = connect_cell->getPort(ID::B);
xlog("found $connect cell %s: %s <-> %s\n", log_id(connect_cell), log_signal(sig_a), log_signal(sig_b));
xlog("found $connect cell %s: %s <-> %s\n", connect_cell, log_signal(sig_a), log_signal(sig_b));
for (auto &side : {sig_a, sig_b})
for (auto chunk : side.chunks())
if (chunk.wire)
@ -452,7 +452,7 @@ void RTLIL::Module::bufNormalize()
}
if (wire->driverCell_ == nullptr) {
xlog("wire %s drivers %s\n", log_id(wire), log_signal(wire_drivers));
xlog("wire %s drivers %s\n", wire, log_signal(wire_drivers));
addBuf(NEW_ID, wire_drivers, wire);
}
}
@ -541,7 +541,7 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
mon->notify_connect(this, conn_it->first, conn_it->second, signal);
if (yosys_xtrace) {
log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
log("#X# Unconnect %s.%s.%s\n", this->module, this, portname.unescape());
log_backtrace("-X- ", yosys_xtrace-1);
}
@ -601,7 +601,7 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
mon->notify_connect(this, conn_it->first, conn_it->second, signal);
if (yosys_xtrace) {
log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
log("#X# Connect %s.%s.%s = %s (%d)\n", this->module, this, portname.unescape(), log_signal(signal), GetSize(signal));
log_backtrace("-X- ", yosys_xtrace-1);
}

4
kernel/satgen.cc
View file

@ -1395,9 +1395,9 @@ void report_missing_model(bool warn_only, RTLIL::Cell* cell)
{
std::string s;
if (cell->is_builtin_ff())
s = stringf("No SAT model available for async FF cell %s (%s). Consider running `async2sync` or `clk2fflogic` first.\n", log_id(cell), log_id(cell->type));
s = stringf("No SAT model available for async FF cell %s (%s). Consider running `async2sync` or `clk2fflogic` first.\n", cell, cell->type.unescape());
else
s = stringf("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type));
s = stringf("No SAT model available for cell %s (%s).\n", cell, cell->type.unescape());
if (warn_only) {
log_formatted_warning_noprefix(s);

2
kernel/scopeinfo.h
View file

@ -328,7 +328,7 @@ struct ModuleItem {
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(ptr); return h; }
};
static inline void log_dump_val_worker(typename IdTree<ModuleItem>::Cursor cursor ) { log("%p %s", cursor.target, log_id(cursor.scope_name)); }
static inline void log_dump_val_worker(typename IdTree<ModuleItem>::Cursor cursor ) { log("%p %s", cursor.target, cursor.scope_name.unescape()); }
template<typename T>
static inline void log_dump_val_worker(const typename std::unique_ptr<T> &cursor ) { log("unique %p", cursor.get()); }

22
kernel/timinginfo.h
View file

@ -105,21 +105,21 @@ struct TimingInfo
auto dst = cell->getPort(ID::DST);
for (const auto &c : src.chunks())
if (!c.wire || !c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src));
for (const auto &c : dst.chunks())
if (!c.wire || !c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", module, cell, log_signal(dst));
int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
int max = std::max(rise_max,fall_max);
if (max < 0)
log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", module, cell);
if (cell->getParam(ID::FULL).as_bool()) {
for (const auto &s : src)
for (const auto &d : dst) {
auto r = t.comb.insert(BitBit(s,d));
if (!r.second)
log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", module, log_signal(s), log_signal(d));
r.first->second = max;
}
}
@ -130,7 +130,7 @@ struct TimingInfo
const auto &d = dst[i];
auto r = t.comb.insert(BitBit(s,d));
if (!r.second)
log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", module, log_signal(s), log_signal(d));
r.first->second = max;
}
}
@ -139,15 +139,15 @@ struct TimingInfo
auto src = cell->getPort(ID::SRC).as_bit();
auto dst = cell->getPort(ID::DST);
if (!src.wire || !src.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src));
for (const auto &c : dst.chunks())
if (!c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", module, cell, log_signal(dst));
int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
int max = std::max(rise_max,fall_max);
if (max < 0) {
log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell));
log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\n", module, cell);
max = 0;
}
for (const auto &d : dst) {
@ -167,12 +167,12 @@ struct TimingInfo
auto dst = cell->getPort(ID::DST).as_bit();
for (const auto &c : src.chunks())
if (!c.wire || !c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src));
if (!dst.wire || !dst.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", module, cell, log_signal(dst));
int max = cell->getParam(ID::T_LIMIT_MAX).as_int();
if (max < 0) {
log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell));
log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\n", module, cell);
max = 0;
}
for (const auto &s : src) {

12
kernel/yosys.cc
View file

@ -954,7 +954,7 @@ static char *readline_obj_generator(const char *text, int state)
{
for (auto mod : design->modules())
if (RTLIL::unescape_id(mod->name).compare(0, len, text) == 0)
obj_names.push_back(strdup(log_id(mod->name)));
obj_names.push_back(strdup(mod->name.unescape().c_str()));
}
else if (design->module(design->selected_active_module) != nullptr)
{
@ -962,19 +962,19 @@ static char *readline_obj_generator(const char *text, int state)
for (auto w : module->wires())
if (RTLIL::unescape_id(w->name).compare(0, len, text) == 0)
obj_names.push_back(strdup(log_id(w->name)));
obj_names.push_back(strdup(w->name.unescape().c_str()));
for (auto &it : module->memories)
if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
obj_names.push_back(strdup(log_id(it.first)));
obj_names.push_back(strdup(it.first.unescape().c_str()));
for (auto cell : module->cells())
if (RTLIL::unescape_id(cell->name).compare(0, len, text) == 0)
obj_names.push_back(strdup(log_id(cell->name)));
obj_names.push_back(strdup(cell->name.unescape().c_str()));
for (auto &it : module->processes)
if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
obj_names.push_back(strdup(log_id(it.first)));
obj_names.push_back(strdup(it.first.unescape().c_str()));
}
std::sort(obj_names.begin(), obj_names.end());
@ -1179,7 +1179,7 @@ struct ScriptCmdPass : public Pass {
if (!mod->selected(w))
continue;
if (!c.second.is_fully_const())
log_error("RHS of selected wire %s.%s is not constant.\n", log_id(mod), log_id(w));
log_error("RHS of selected wire %s.%s is not constant.\n", mod, w);
auto v = c.second.as_const();
Pass::call_on_module(design, mod, v.decode_string());
}