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https://github.com/YosysHQ/yosys
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Refactored uses of log_id()
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parent
89d83a3410
commit
e41b969da2
186 changed files with 1219 additions and 1220 deletions
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@ -224,7 +224,7 @@ AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString
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module = new RTLIL::Module;
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module->name = module_name;
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if (design->module(module->name))
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log_error("Duplicate definition of module %s!\n", log_id(module->name));
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log_error("Duplicate definition of module %s!\n", module->name.unescape());
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}
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void AigerReader::parse_aiger()
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@ -821,7 +821,7 @@ void AigerReader::post_process()
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RTLIL::Wire* wire = inputs[variable];
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log_assert(wire);
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log_assert(wire->port_input);
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log_debug("Renaming input %s", log_id(wire));
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log_debug("Renaming input %s", wire);
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RTLIL::Wire *existing = nullptr;
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if (index == 0) {
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@ -835,7 +835,7 @@ void AigerReader::post_process()
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wire->port_input = false;
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module->connect(wire, existing);
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}
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log_debug(" -> %s\n", log_id(escaped_s));
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log_debug(" -> %s\n", escaped_s.unescape());
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}
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else {
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RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
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@ -846,7 +846,7 @@ void AigerReader::post_process()
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module->connect(wire, existing);
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wire->port_input = false;
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}
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log_debug(" -> %s\n", log_id(indexed_name));
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log_debug(" -> %s\n", indexed_name.unescape());
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}
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if (wideports && !existing) {
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@ -866,7 +866,7 @@ void AigerReader::post_process()
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RTLIL::Wire* wire = outputs[variable + co_count];
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log_assert(wire);
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log_assert(wire->port_output);
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log_debug("Renaming output %s", log_id(wire));
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log_debug("Renaming output %s", wire);
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RTLIL::Wire *existing;
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if (index == 0) {
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@ -882,7 +882,7 @@ void AigerReader::post_process()
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module->connect(wire, existing);
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wire = existing;
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}
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log_debug(" -> %s\n", log_id(escaped_s));
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log_debug(" -> %s\n", escaped_s.unescape());
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}
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else {
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RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
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@ -894,7 +894,7 @@ void AigerReader::post_process()
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existing->port_output = true;
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module->connect(wire, existing);
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}
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log_debug(" -> %s\n", log_id(indexed_name));
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log_debug(" -> %s\n", indexed_name.unescape());
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}
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if (wideports && !existing) {
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@ -912,7 +912,7 @@ void AigerReader::post_process()
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else if (type == "box") {
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RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));
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if (!cell)
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log_debug("Box %d (%s) no longer exists.\n", variable, log_id(escaped_s));
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log_debug("Box %d (%s) no longer exists.\n", variable, escaped_s.unescape());
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else
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module->rename(cell, escaped_s);
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}
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