mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-31 08:23:19 +00:00
Code Activity

Docs: Update for properties

Browse source 
Add properties page, move cell_gate and cell_word under a singular cell_index along with properties.  Fix links accordingly.

Also drop x-aware and x-output todos since they are resolved.
This commit is contained in:
Krystine Sherwin 2024-09-06 15:40:22 +12:00
parent 4d84d7e69f
commit e40134c856
No known key found for this signature in database
9 changed files with 34 additions and 18 deletions
Download patch file Download diff file Expand all files Collapse all files

10
docs/source/cell/word_binary.rst
View file

@ -6,16 +6,6 @@ Binary operators
.. TODO:: display cell titles
.. todo:: 'x' aware warning
some passes will treat cell as the non 'x' aware cell, i.e. synthesis; `$eqx`
`$nex` `$bweqx`
.. todo:: 'x' output
shiftx, div, mod, pmux (less-so) can produce 'x' output even if all inputs
are defined
All binary RTL cells have two input ports ``A`` and ``B`` and one output port
``Y``. They also have the following parameters: