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Docs: Update for properties

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Add properties page, move cell_gate and cell_word under a singular cell_index along with properties.  Fix links accordingly.

Also drop x-aware and x-output todos since they are resolved.
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Krystine Sherwin 2024-09-06 15:40:22 +12:00
parent 4d84d7e69f
commit e40134c856
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docs/source/cell/index_word.rst Normal file
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Word-level cells
----------------
Most of the RTL cells closely resemble the operators available in HDLs such as
Verilog or VHDL. Therefore Verilog operators are used in the following sections
to define the behaviour of the RTL cells.
Note that all RTL cells have parameters indicating the size of inputs and
outputs. When passes modify RTL cells they must always keep the values of these
parameters in sync with the size of the signals connected to the inputs and
outputs.
Simulation models for the RTL cells can be found in the file
:file:`techlibs/common/simlib.v` in the Yosys source tree.
.. toctree::
:maxdepth: 2
/cell/word_unary
/cell/word_binary
/cell/word_mux
/cell/word_reg
/cell/word_mem
/cell/word_fsm
/cell/word_arith
/cell/word_spec
/cell/word_formal
/cell/word_debug
/cell/word_wire