Docs: Update for properties

Add properties page, move cell_gate and cell_word under a singular cell_index along with properties.  Fix links accordingly.

Also drop x-aware and x-output todos since they are resolved.

docs/source/cell/index_gate.rst

@@ -0,0 +1,25 @@
+.. _sec:celllib_gates:
+
+Gate-level cells
+----------------
+
+For gate level logic networks, fixed function single bit cells are used that do
+not provide any parameters.
+
+Simulation models for these cells can be found in the file
+:file:`techlibs/common/simcells.v` in the Yosys source tree.
+
+In most cases gate level logic networks are created from RTL networks using the
+techmap pass. The flip-flop cells from the gate level logic network can be
+mapped to physical flip-flop cells from a Liberty file using the dfflibmap pass.
+The combinatorial logic cells can be mapped to physical cells from a Liberty
+file via ABC using the abc pass.
+
+.. toctree::
+   :maxdepth: 2
+
+   /cell/gate_comb_simple
+   /cell/gate_comb_combined
+   /cell/gate_reg_ff
+   /cell/gate_reg_latch
+   /cell/gate_other

docs/source/cell/index_word.rst

@@ -0,0 +1,29 @@
+Word-level cells
+----------------
+
+Most of the RTL cells closely resemble the operators available in HDLs such as
+Verilog or VHDL. Therefore Verilog operators are used in the following sections
+to define the behaviour of the RTL cells.
+
+Note that all RTL cells have parameters indicating the size of inputs and
+outputs. When passes modify RTL cells they must always keep the values of these
+parameters in sync with the size of the signals connected to the inputs and
+outputs.
+
+Simulation models for the RTL cells can be found in the file
+:file:`techlibs/common/simlib.v` in the Yosys source tree.
+
+.. toctree::
+   :maxdepth: 2
+
+   /cell/word_unary
+   /cell/word_binary
+   /cell/word_mux
+   /cell/word_reg
+   /cell/word_mem
+   /cell/word_fsm
+   /cell/word_arith
+   /cell/word_spec
+   /cell/word_formal
+   /cell/word_debug
+   /cell/word_wire

docs/source/cell/properties.rst

@@ -0,0 +1,18 @@
+Cell properties
+---------------
+
+.. TODO:: Fill :cell:ref:`is_evaluable`
+
+.. cell:defprop:: is_evaluable
+
+.. cell:defprop:: x-aware
+
+   Some passes will treat these cells as the non 'x' aware cell.  For example,
+   during synthesis `$eqx` will typically be treated as `$eq`.
+
+.. cell:defprop:: x-output
+
+   These cells can produce 'x' output even if all inputs are defined.  For
+   example, a `$div` cell with ``B=0`` has undefined output.
+
+Refer to the :ref:`propindex` for the list of cells with a given property.

docs/source/cell/word_binary.rst

@@ -6,16 +6,6 @@ Binary operators
 
 .. TODO:: display cell titles
 
-.. todo:: 'x' aware warning
-
-   some passes will treat cell as the non 'x' aware cell, i.e. synthesis; `$eqx`
-   `$nex` `$bweqx`
-
-.. todo:: 'x' output
-
-   shiftx, div, mod, pmux (less-so) can produce 'x' output even if all inputs
-   are defined
-
 All binary RTL cells have two input ports ``A`` and ``B`` and one output port
 ``Y``. They also have the following parameters: