mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-07 03:31:24 +00:00
Merge remote-tracking branch 'origin/master' into xc7dsp
This commit is contained in:
Eddie Hung
commit
e3d898dccb
49 changed files with 1136 additions and 554 deletions
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@ -17,11 +17,10 @@
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*
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*/
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#include "kernel/register.h"
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#include "kernel/yosys.h"
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#include "kernel/celltypes.h"
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#include "passes/techmap/libparse.h"
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#include "kernel/log.h"
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#include "kernel/cost.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -228,21 +227,16 @@ struct statdata_t
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{
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int tran_cnt = 0;
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bool tran_cnt_exact = true;
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auto &gate_costs = CellCosts::cmos_gate_cost();
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for (auto it : num_cells_by_type) {
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auto ctype = it.first;
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auto cnum = it.second;
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if (ctype == "$_NOT_")
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tran_cnt += 2*cnum;
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else if (ctype.in("$_NAND_", "$_NOR_"))
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tran_cnt += 4*cnum;
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else if (ctype.in("$_AOI3_", "$_OAI3_"))
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tran_cnt += 6*cnum;
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else if (ctype.in("$_AOI4_", "$_OAI4_"))
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tran_cnt += 8*cnum;
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if (gate_costs.count(ctype))
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tran_cnt += cnum * gate_costs.at(ctype);
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else if (ctype.in("$_DFF_P_", "$_DFF_N_"))
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tran_cnt += 16*cnum;
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tran_cnt += cnum * 16;
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else
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tran_cnt_exact = false;
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}
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@ -641,6 +641,31 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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did_something = true;
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}
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}
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if (cell->type.in("$add", "$sub")) {
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RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
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RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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bool sub = cell->type == "$sub";
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int i;
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for (i = 0; i < GetSize(sig_y); i++) {
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if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx)
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module->connect(sig_y[i], sig_a[i]);
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else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx)
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module->connect(sig_y[i], sig_b[i]);
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else
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break;
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}
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if (i > 0) {
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cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
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cell->setPort("\\A", sig_a.extract_end(i));
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cell->setPort("\\B", sig_b.extract_end(i));
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cell->setPort("\\Y", sig_y.extract_end(i));
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cell->fixup_parameters();
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did_something = true;
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}
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}
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}
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if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$shift" || cell->type == "$shiftx" ||
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@ -81,7 +81,7 @@ struct OptLutWorker
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}
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}
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log("Number of LUTs: %8zu\n", luts.size());
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log("Number of LUTs: %8d\n", GetSize(luts));
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for (int arity = 1; arity <= max_arity; arity++)
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{
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if (arity_counts[arity])
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@ -351,14 +351,14 @@ struct OptLutWorker
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int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
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if (lutA_dlogic_inputs.size())
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log_debug(" Cell A is a %d-LUT with %zu dedicated connections. ", lutA_arity, lutA_dlogic_inputs.size());
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log_debug(" Cell A is a %d-LUT with %d dedicated connections. ", lutA_arity, GetSize(lutA_dlogic_inputs));
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else
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log_debug(" Cell A is a %d-LUT. ", lutA_arity);
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if (lutB_dlogic_inputs.size())
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log_debug("Cell B is a %d-LUT with %zu dedicated connections.\n", lutB_arity, lutB_dlogic_inputs.size());
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log_debug("Cell B is a %d-LUT with %d dedicated connections.\n", lutB_arity, GetSize(lutB_dlogic_inputs));
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else
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log_debug("Cell B is a %d-LUT.\n", lutB_arity);
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log_debug(" Cells share %zu input(s) and can be merged into one %d-LUT.\n", common_inputs.size(), lutM_arity);
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log_debug(" Cells share %d input(s) and can be merged into one %d-LUT.\n", GetSize(common_inputs), lutM_arity);
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const int COMBINE_A = 1, COMBINE_B = 2, COMBINE_EITHER = COMBINE_A | COMBINE_B;
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int combine_mask = 0;
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@ -171,7 +171,7 @@ struct RmportsPassPass : public Pass {
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wire->port_output = false;
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wire->port_id = 0;
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}
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log("Removed %zu unused ports.\n", unused_ports.size());
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log("Removed %d unused ports.\n", GetSize(unused_ports));
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// Re-number all of the wires that DO have ports still on them
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for(size_t i=0; i<module->ports.size(); i++)
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@ -365,29 +365,6 @@ struct WreduceWorker
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}
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}
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if (cell->type.in("$add", "$sub")) {
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SigSpec A = mi.sigmap(cell->getPort("\\A"));
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SigSpec B = mi.sigmap(cell->getPort("\\B"));
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bool sub = cell->type == "$sub";
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int i;
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for (i = 0; i < GetSize(sig); i++) {
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if (B.at(i, Sx) != S0 && (sub || A.at(i, Sx) != S0))
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break;
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if (B[i] == S0)
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module->connect(sig[i], A[i]);
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else if (A[i] == S0)
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module->connect(sig[i], B[i]);
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else log_abort();
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}
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if (i > 0) {
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cell->setPort("\\A", A.extract(i, -1));
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cell->setPort("\\B", B.extract(i, -1));
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sig.remove(0, i);
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bits_removed += i;
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}
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}
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if (GetSize(sig) == 0) {
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log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
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module->remove(cell);
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@ -395,7 +372,7 @@ struct WreduceWorker
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}
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if (bits_removed) {
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log("Removed %d bits (of %d) from port Y of cell %s.%s (%s).\n",
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log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
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bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
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cell->setPort("\\Y", sig);
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did_something = true;
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@ -82,14 +82,23 @@ struct PruneWorker
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if (root) {
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bool promotable = true;
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for (auto &bit : lhs) {
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if (bit.wire && affected[bit]) {
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if (bit.wire && affected[bit] && !assigned[bit]) {
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promotable = false;
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break;
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}
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}
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if (promotable) {
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RTLIL::SigSpec rhs = sigmap(it->second);
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RTLIL::SigSig conn;
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for (int i = 0; i < GetSize(lhs); i++) {
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RTLIL::SigBit lhs_bit = lhs[i];
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if (lhs_bit.wire && !assigned[lhs_bit]) {
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conn.first.append_bit(lhs_bit);
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conn.second.append(rhs.extract(i));
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}
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}
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promoted_count++;
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module->connect(*it);
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module->connect(conn);
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remove.insert(*it);
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}
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}
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@ -49,6 +49,7 @@
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <cctype>
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#include <cerrno>
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#include <sstream>
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#include <climits>
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@ -81,6 +82,7 @@ enum class gate_type_t {
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G_ANDNOT,
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G_ORNOT,
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G_MUX,
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G_NMUX,
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G_AOI3,
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G_OAI3,
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G_AOI4,
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@ -111,7 +113,7 @@ std::vector<gate_t> signal_list;
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std::map<RTLIL::SigBit, int> signal_map;
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std::map<RTLIL::SigBit, RTLIL::State> signal_init;
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pool<std::string> enabled_gates;
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bool recover_init;
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bool recover_init, cmos_cost;
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bool clk_polarity, en_polarity;
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RTLIL::SigSpec clk_sig, en_sig;
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@ -257,7 +259,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
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return;
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}
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if (cell->type == "$_MUX_")
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if (cell->type.in("$_MUX_", "$_NMUX_"))
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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@ -273,7 +275,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
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int mapped_b = map_signal(sig_b);
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int mapped_s = map_signal(sig_s);
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map_signal(sig_y, G(MUX), mapped_a, mapped_b, mapped_s);
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map_signal(sig_y, cell->type == "$_MUX_" ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
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module->remove(cell);
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return;
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@ -885,6 +887,10 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
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fprintf(f, "1-0 1\n");
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fprintf(f, "-11 1\n");
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} else if (si.type == G(NMUX)) {
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
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fprintf(f, "0-0 1\n");
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fprintf(f, "-01 1\n");
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} else if (si.type == G(AOI3)) {
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
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fprintf(f, "-00 1\n");
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@ -925,46 +931,50 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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{
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log_header(design, "Executing ABC.\n");
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auto &cell_cost = cmos_cost ? CellCosts::cmos_gate_cost() : CellCosts::default_gate_cost();
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buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
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f = fopen(buffer.c_str(), "wt");
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if (f == NULL)
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log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
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fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
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fprintf(f, "GATE ONE 1 Y=CONST1;\n");
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fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_BUF_"));
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fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOT_"));
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fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_BUF_"));
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fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NOT_"));
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if (enabled_gates.empty() || enabled_gates.count("AND"))
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fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_AND_"));
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fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_AND_"));
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if (enabled_gates.empty() || enabled_gates.count("NAND"))
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fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NAND_"));
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fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NAND_"));
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if (enabled_gates.empty() || enabled_gates.count("OR"))
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fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_OR_"));
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fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_OR_"));
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if (enabled_gates.empty() || enabled_gates.count("NOR"))
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fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOR_"));
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fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NOR_"));
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if (enabled_gates.empty() || enabled_gates.count("XOR"))
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fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XOR_"));
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fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_XOR_"));
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if (enabled_gates.empty() || enabled_gates.count("XNOR"))
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fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XNOR_"));
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fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_XNOR_"));
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if (enabled_gates.empty() || enabled_gates.count("ANDNOT"))
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fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ANDNOT_"));
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fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_ANDNOT_"));
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if (enabled_gates.empty() || enabled_gates.count("ORNOT"))
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fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ORNOT_"));
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fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_ORNOT_"));
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if (enabled_gates.empty() || enabled_gates.count("AOI3"))
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fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI3_"));
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fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_AOI3_"));
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if (enabled_gates.empty() || enabled_gates.count("OAI3"))
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fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI3_"));
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fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_OAI3_"));
|
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if (enabled_gates.empty() || enabled_gates.count("AOI4"))
|
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fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI4_"));
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fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_AOI4_"));
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if (enabled_gates.empty() || enabled_gates.count("OAI4"))
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fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI4_"));
|
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fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_OAI4_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("MUX"))
|
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fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_MUX_"));
|
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fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_MUX_"));
|
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if (enabled_gates.empty() || enabled_gates.count("NMUX"))
|
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fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_NMUX_"));
|
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if (map_mux4)
|
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fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*get_cell_cost("$_MUX_"));
|
||||
fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at("$_MUX_"));
|
||||
if (map_mux8)
|
||||
fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*get_cell_cost("$_MUX_"));
|
||||
fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at("$_MUX_"));
|
||||
if (map_mux16)
|
||||
fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*get_cell_cost("$_MUX_"));
|
||||
fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at("$_MUX_"));
|
||||
fclose(f);
|
||||
|
||||
if (!lut_costs.empty()) {
|
||||
|
|
@ -1065,8 +1075,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
|
|||
design->select(module, cell);
|
||||
continue;
|
||||
}
|
||||
if (c->type == "\\MUX") {
|
||||
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
|
||||
if (c->type == "\\MUX" || c->type == "\\NMUX") {
|
||||
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
|
||||
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
|
||||
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
|
||||
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
|
||||
|
|
@ -1406,11 +1416,12 @@ struct AbcPass : public Pass {
|
|||
log("\n");
|
||||
log(" The following aliases can be used to reference common sets of gate types:\n");
|
||||
log(" simple: AND OR XOR MUX\n");
|
||||
log(" cmos2: NAND NOR\n");
|
||||
log(" cmos3: NAND NOR AOI3 OAI3\n");
|
||||
log(" cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4\n");
|
||||
log(" gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT\n");
|
||||
log(" aig: AND NAND OR NOR ANDNOT ORNOT\n");
|
||||
log(" cmos2: NAND NOR\n");
|
||||
log(" cmos3: NAND NOR AOI3 OAI3\n");
|
||||
log(" cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4\n");
|
||||
log(" cmos: NAND NOR AOI3 OAI3 AOI4 OAI4 NMUX MUX XOR XNOR\n");
|
||||
log(" gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT\n");
|
||||
log(" aig: AND NAND OR NOR ANDNOT ORNOT\n");
|
||||
log("\n");
|
||||
log(" Prefix a gate type with a '-' to remove it from the list. For example\n");
|
||||
log(" the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.\n");
|
||||
|
|
@ -1488,6 +1499,7 @@ struct AbcPass : public Pass {
|
|||
map_mux8 = false;
|
||||
map_mux16 = false;
|
||||
enabled_gates.clear();
|
||||
cmos_cost = false;
|
||||
|
||||
#ifdef _WIN32
|
||||
#ifndef ABCEXTERNAL
|
||||
|
|
@ -1628,11 +1640,15 @@ struct AbcPass : public Pass {
|
|||
goto ok_alias;
|
||||
}
|
||||
if (g == "cmos2") {
|
||||
if (!remove_gates)
|
||||
cmos_cost = true;
|
||||
gate_list.push_back("NAND");
|
||||
gate_list.push_back("NOR");
|
||||
goto ok_alias;
|
||||
}
|
||||
if (g == "cmos3") {
|
||||
if (!remove_gates)
|
||||
cmos_cost = true;
|
||||
gate_list.push_back("NAND");
|
||||
gate_list.push_back("NOR");
|
||||
gate_list.push_back("AOI3");
|
||||
|
|
@ -1640,6 +1656,8 @@ struct AbcPass : public Pass {
|
|||
goto ok_alias;
|
||||
}
|
||||
if (g == "cmos4") {
|
||||
if (!remove_gates)
|
||||
cmos_cost = true;
|
||||
gate_list.push_back("NAND");
|
||||
gate_list.push_back("NOR");
|
||||
gate_list.push_back("AOI3");
|
||||
|
|
@ -1648,6 +1666,21 @@ struct AbcPass : public Pass {
|
|||
gate_list.push_back("OAI4");
|
||||
goto ok_alias;
|
||||
}
|
||||
if (g == "cmos") {
|
||||
if (!remove_gates)
|
||||
cmos_cost = true;
|
||||
gate_list.push_back("NAND");
|
||||
gate_list.push_back("NOR");
|
||||
gate_list.push_back("AOI3");
|
||||
gate_list.push_back("OAI3");
|
||||
gate_list.push_back("AOI4");
|
||||
gate_list.push_back("OAI4");
|
||||
gate_list.push_back("NMUX");
|
||||
gate_list.push_back("MUX");
|
||||
gate_list.push_back("XOR");
|
||||
gate_list.push_back("XNOR");
|
||||
goto ok_alias;
|
||||
}
|
||||
if (g == "gates") {
|
||||
gate_list.push_back("AND");
|
||||
gate_list.push_back("NAND");
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@ void handle_loops(RTLIL::Design *design)
|
|||
{
|
||||
Pass::call(design, "scc -set_attr abc_scc_id {}");
|
||||
|
||||
dict<IdString, vector<IdString>> abc_scc_break;
|
||||
dict<IdString, vector<IdString>> abc_scc_break;
|
||||
|
||||
// For every unique SCC found, (arbitrarily) find the first
|
||||
// cell in the component, and select (and mark) all its output
|
||||
|
|
@ -290,7 +290,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
|
||||
bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
|
||||
bool show_tempdir, std::string box_file, std::string lut_file,
|
||||
std::string wire_delay)
|
||||
std::string wire_delay, const dict<int,IdString> &box_lookup)
|
||||
{
|
||||
module = current_module;
|
||||
map_autoidx = autoidx++;
|
||||
|
|
@ -429,10 +429,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
RTLIL::Selection& sel = design->selection_stack.back();
|
||||
sel.select(module);
|
||||
|
||||
Pass::call(design, "aigmap");
|
||||
|
||||
handle_loops(design);
|
||||
|
||||
Pass::call(design, "aigmap");
|
||||
|
||||
//log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
|
||||
// count_gates, GetSize(signal_list), count_input, count_output);
|
||||
|
||||
|
|
@ -476,7 +476,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
}
|
||||
module->fixup_ports();
|
||||
|
||||
|
||||
log_header(design, "Executing ABC9.\n");
|
||||
|
||||
if (!lut_costs.empty()) {
|
||||
|
|
@ -520,8 +519,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
|
||||
buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
|
||||
log_assert(!design->module("$__abc9__"));
|
||||
|
||||
AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
|
||||
reader.parse_xaiger();
|
||||
reader.parse_xaiger(box_lookup);
|
||||
ifs.close();
|
||||
|
||||
#if 0
|
||||
|
|
@ -646,6 +646,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
}
|
||||
else {
|
||||
existing_cell = module->cell(c->name);
|
||||
log_assert(existing_cell);
|
||||
cell = module->addCell(remap_name(c->name), c->type);
|
||||
module->swap_names(cell, existing_cell);
|
||||
}
|
||||
|
|
@ -1081,6 +1082,21 @@ struct Abc9Pass : public Pass {
|
|||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
dict<int,IdString> box_lookup;
|
||||
for (auto m : design->modules()) {
|
||||
auto it = m->attributes.find("\\abc_box_id");
|
||||
if (it == m->attributes.end())
|
||||
continue;
|
||||
if (m->name.begins_with("$paramod"))
|
||||
continue;
|
||||
auto id = it->second.as_int();
|
||||
auto r = box_lookup.insert(std::make_pair(id, m->name));
|
||||
if (!r.second)
|
||||
log_error("Module '%s' has the same abc_box_id = %d value as '%s'.\n",
|
||||
log_id(m), id, log_id(r.first->second));
|
||||
log_assert(r.second);
|
||||
}
|
||||
|
||||
for (auto mod : design->selected_modules())
|
||||
{
|
||||
if (mod->attributes.count("\\abc_box_id"))
|
||||
|
|
@ -1096,7 +1112,7 @@ struct Abc9Pass : public Pass {
|
|||
if (!dff_mode || !clk_str.empty()) {
|
||||
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
|
||||
delay_target, lutin_shared, fast_mode, show_tempdir,
|
||||
box_file, lut_file, wire_delay);
|
||||
box_file, lut_file, wire_delay, box_lookup);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -1242,15 +1258,16 @@ struct Abc9Pass : public Pass {
|
|||
en_sig = assign_map(std::get<3>(it.first));
|
||||
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$",
|
||||
keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
|
||||
box_file, lut_file, wire_delay);
|
||||
box_file, lut_file, wire_delay, box_lookup);
|
||||
assign_map.set(mod);
|
||||
}
|
||||
}
|
||||
|
||||
Pass::call(design, "clean");
|
||||
|
||||
assign_map.clear();
|
||||
|
||||
// The "clean" pass also contains a design->check() call
|
||||
Pass::call(design, "clean");
|
||||
|
||||
log_pop();
|
||||
}
|
||||
} Abc9Pass;
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@ struct ExtractFaWorker
|
|||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
if (cell->type.in( "$_BUF_", "$_NOT_", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_",
|
||||
"$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$_MUX_",
|
||||
"$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$_MUX_", "$_NMUX_",
|
||||
"$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_"))
|
||||
{
|
||||
SigBit y = sigmap(SigBit(cell->getPort("\\Y")));
|
||||
|
|
|
|||
|
|
@ -783,7 +783,7 @@ struct FlowmapWorker
|
|||
int depth = 0;
|
||||
for (auto label : labels)
|
||||
depth = max(depth, label.second);
|
||||
log("Mapped to %zu LUTs with maximum depth %d.\n", lut_nodes.size(), depth);
|
||||
log("Mapped to %d LUTs with maximum depth %d.\n", GetSize(lut_nodes), depth);
|
||||
|
||||
if (debug)
|
||||
{
|
||||
|
|
@ -1195,7 +1195,7 @@ struct FlowmapWorker
|
|||
|
||||
bool relax_depth_for_bound(bool first, int depth_bound, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> &lut_critical_outputs)
|
||||
{
|
||||
size_t initial_count = lut_nodes.size();
|
||||
int initial_count = GetSize(lut_nodes);
|
||||
|
||||
for (auto node : lut_nodes)
|
||||
{
|
||||
|
|
@ -1215,7 +1215,7 @@ struct FlowmapWorker
|
|||
|
||||
if (potentials.empty())
|
||||
{
|
||||
log(" Relaxed to %zu (+%zu) LUTs.\n", lut_nodes.size(), lut_nodes.size() - initial_count);
|
||||
log(" Relaxed to %d (+%d) LUTs.\n", GetSize(lut_nodes), GetSize(lut_nodes) - initial_count);
|
||||
if (!first && break_num == 1)
|
||||
{
|
||||
log(" Design fully relaxed.\n");
|
||||
|
|
@ -1419,9 +1419,9 @@ struct FlowmapWorker
|
|||
lut_area += lut_table.size();
|
||||
|
||||
if ((int)input_nodes.size() >= minlut)
|
||||
log(" Packed into a %zu-LUT %s.%s.\n", input_nodes.size(), log_id(module), log_id(lut));
|
||||
log(" Packed into a %d-LUT %s.%s.\n", GetSize(input_nodes), log_id(module), log_id(lut));
|
||||
else
|
||||
log(" Packed into a %zu-LUT %s.%s (implemented as %d-LUT).\n", input_nodes.size(), log_id(module), log_id(lut), minlut);
|
||||
log(" Packed into a %d-LUT %s.%s (implemented as %d-LUT).\n", GetSize(input_nodes), log_id(module), log_id(lut), minlut);
|
||||
}
|
||||
|
||||
for (auto node : mapped_nodes)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue