3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-03 09:50:24 +00:00

move microchip tests from techlibs/microchip/tests to tests/arch/microchip

This commit is contained in:
chunlin min 2024-07-04 14:16:52 -04:00
parent 19d3214861
commit e3c4791e5b
42 changed files with 0 additions and 0 deletions

View file

@ -1,24 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
# read verilog files
read_verilog mac.v
# run the synth flow, specifies top module and additional parameters
synth_microchip -top mac -abc9 -family polarfire -noiopad
# write final outputfile
write_verilog -noexpr mac.vm